Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9476
-gerrit
commit 456d8ac9877fcb6b6aee19503c0cdd5c96109019
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Sun Nov 23 17:07:50 2014 -0800
tpm: Remove error message for unknown resource type
This is being triggered because the base address is added, but
there is nothing that needs done with it in set_resources step
and the ERROR message is tripping suspend resume test scripts.
BUG=chrome-os-partner:33385
BRANCH=samus,auron
TEST=boot on samus and check for ERROR strings,
successfully run suspend_stress_test without failures
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/231603
(cherry picked from commit bb789492965d92e309a913dc7b9f09f7036c5480)
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Change-Id: I565c8af954f1c5a406d2c65f01c274e9259e43ec
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 9062734d884f814dc880589ee615b4d7e1fdc61a
Original-Change-Id: I2b5f44795f1ee445d509b29bd56f498aea7b7fe3
Original-Reviewed-on: https://chromium-review.googlesource.com/231604
Original-Commit-Queue: Duncan Laurie <dlaurie(a)chromium.org>
Original-Tested-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/drivers/pc80/tpm/tpm.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/drivers/pc80/tpm/tpm.c b/src/drivers/pc80/tpm/tpm.c
index f1c5d97..68758aa 100644
--- a/src/drivers/pc80/tpm/tpm.c
+++ b/src/drivers/pc80/tpm/tpm.c
@@ -749,9 +749,6 @@ static void lpc_tpm_set_resources(struct device *dev)
tis_setup_interrupt((int)res->base,
config->irq_polarity);
} else {
- printk(BIOS_ERR,
- "ERROR: %s %02lx unknown resource type\n",
- dev_path(dev), res->index);
continue;
}
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9474
-gerrit
commit 45108eb93ee77f64bf9945a2da2ebf501ce26692
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Nov 10 13:00:27 2014 -0800
broadwell: Only do pre-graphics delay when running option rom
This changes the broadwell graphics init path to only do the delay
before initializing graphics when running chromeos if we are also
going to execute the option rom.
BUG=chrome-os-partner:33671
BRANCH=samus
TEST=build and boot on samus
Change-Id: Idb7d39b22f7f6dc3be6dfbd2fa3cc2e33d78a397
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: f7ed93504a74760f16acb8fb3c6c57ac514b7260
Original-Change-Id: I350f85738efe3d17152de4f025adbfd52ae15b95
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228882
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/broadwell/igd.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index 41a6961..4257ff3 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -33,6 +33,7 @@
#include <soc/ramstage.h>
#include <soc/systemagent.h>
#include <soc/intel/broadwell/chip.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#define GT_RETRY 1000
#define GT_CDCLK_337 0
@@ -487,7 +488,13 @@ static void igd_init(struct device *dev)
return;
/* Wait for any configured pre-graphics delay */
+#if IS_ENABLED(CONFIG_CHROMEOS)
+ if (developer_mode_enabled() || recovery_mode_enabled() ||
+ vboot_wants_oprom())
+ mdelay(CONFIG_PRE_GRAPHICS_DELAY);
+#else
mdelay(CONFIG_PRE_GRAPHICS_DELAY);
+#endif
/* Early init steps */
if (is_broadwell) {
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9473
-gerrit
commit ae9ba49e499c260e3991cfa0eefa8e19d7bbd82e
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Nov 11 08:31:26 2014 -0800
samus: Move board version to a separate file
This combines the board version reading and parsing to
a separate file that is compiled in both romstage (for
early serial output) and ramstage (for smbios tables).
It also adds a new board version that is wrapped back
to number zero as we are running out of available IDs.
BUG=chrome-os-partner:32895
BRANCH=samus
TEST=build and boot on samus EVT1 and EVT2 and check
for proper board versions reported in console and smbios.
Change-Id: I8c8f17708ced7167277a98529ff4597589f53095
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 3ab8bba1021a8dd41dd2210ba73efd2231eb596c
Original-Change-Id: I2aa03e7486a9581f94dc4e12f6f29eb0c5b3bdbb
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229041
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/samus/Makefile.inc | 3 +++
src/mainboard/google/samus/board_version.c | 37 ++++++++++++++++++++++++++++++
src/mainboard/google/samus/board_version.h | 30 ++++++++++++++++++++++++
src/mainboard/google/samus/ec.h | 4 ----
src/mainboard/google/samus/mainboard.c | 12 ++--------
src/mainboard/google/samus/romstage.c | 5 ++--
6 files changed, 75 insertions(+), 16 deletions(-)
diff --git a/src/mainboard/google/samus/Makefile.inc b/src/mainboard/google/samus/Makefile.inc
index 502204e..e8013a8 100644
--- a/src/mainboard/google/samus/Makefile.inc
+++ b/src/mainboard/google/samus/Makefile.inc
@@ -28,3 +28,6 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-y += pei_data.c
ramstage-y += pei_data.c
+
+romstage-y += board_version.c
+ramstage-y += board_version.c
diff --git a/src/mainboard/google/samus/board_version.c b/src/mainboard/google/samus/board_version.c
new file mode 100644
index 0000000..4575dd5
--- /dev/null
+++ b/src/mainboard/google/samus/board_version.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <ec/google/chromeec/ec.h>
+#include "board_version.h"
+
+const char *samus_board_version(void)
+{
+ switch (google_chromeec_get_board_version()) {
+ case SAMUS_EC_BOARD_VERSION_EVT1:
+ return "EVT1";
+ case SAMUS_EC_BOARD_VERSION_EVT2:
+ return "EVT2";
+ case SAMUS_EC_BOARD_VERSION_EVT3:
+ return "EVT3";
+ case SAMUS_EC_BOARD_VERSION_EVT4:
+ return "EVT4";
+ default:
+ return "Unknown";
+ }
+}
diff --git a/src/mainboard/google/samus/board_version.h b/src/mainboard/google/samus/board_version.h
new file mode 100644
index 0000000..8b3fea3
--- /dev/null
+++ b/src/mainboard/google/samus/board_version.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SAMUS_BOARD_VERSION_H
+#define SAMUS_BOARD_VERSION_H
+
+#define SAMUS_EC_BOARD_VERSION_EVT1 3
+#define SAMUS_EC_BOARD_VERSION_EVT2 4
+#define SAMUS_EC_BOARD_VERSION_EVT3 5
+#define SAMUS_EC_BOARD_VERSION_EVT4 0
+
+const char *samus_board_version(void);
+
+#endif
diff --git a/src/mainboard/google/samus/ec.h b/src/mainboard/google/samus/ec.h
index 295d040..1ba1677 100644
--- a/src/mainboard/google/samus/ec.h
+++ b/src/mainboard/google/samus/ec.h
@@ -22,10 +22,6 @@
#include <ec/google/chromeec/ec_commands.h>
-#define SAMUS_EC_BOARD_VERSION_EVT 3
-#define SAMUS_EC_BOARD_VERSION_EVT2 4
-#define SAMUS_EC_BOARD_VERSION_EVT3 5
-
#define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */
#define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */
diff --git a/src/mainboard/google/samus/mainboard.c b/src/mainboard/google/samus/mainboard.c
index 85e9dfb..53f31a5 100644
--- a/src/mainboard/google/samus/mainboard.c
+++ b/src/mainboard/google/samus/mainboard.c
@@ -32,7 +32,7 @@
#include <arch/io.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
-#include <ec/google/chromeec/ec.h>
+#include "board_version.h"
#include "ec.h"
void mainboard_suspend_resume(void)
@@ -41,15 +41,7 @@ void mainboard_suspend_resume(void)
const char *smbios_mainboard_version(void)
{
- switch (google_chromeec_get_board_version()) {
- case SAMUS_EC_BOARD_VERSION_EVT:
- return "EVT";
- case SAMUS_EC_BOARD_VERSION_EVT2:
- return "EVT2";
- case SAMUS_EC_BOARD_VERSION_EVT3:
- return "EVT3";
- }
- return "Unknown";
+ return samus_board_version();
}
static void mainboard_init(device_t dev)
diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c
index 55658f5..7c9aa6e 100644
--- a/src/mainboard/google/samus/romstage.c
+++ b/src/mainboard/google/samus/romstage.c
@@ -30,6 +30,8 @@
#include <soc/romstage.h>
#include <mainboard/google/samus/spd/spd.h>
#include <mainboard/google/samus/gpio.h>
+#include <ec/google/chromeec/ec.h>
+#include "board_version.h"
void mainboard_romstage_entry(struct romstage_params *rp)
{
@@ -40,8 +42,7 @@ void mainboard_romstage_entry(struct romstage_params *rp)
if (rp->power_state->prev_sleep_state != SLEEP_STATE_S3)
google_chromeec_kbbacklight(100);
- printk(BIOS_INFO, "MLB: board version %d\n",
- google_chromeec_get_board_version());
+ printk(BIOS_INFO, "MLB: board version %s\n", samus_board_version());
/* Ensure the EC and PD are in the right mode for recovery */
google_chromeec_early_pd_init();
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9472
-gerrit
commit 3bc9d52c4604a6741a23f60a347782168b64d98f
Author: Wenkai Du <wenkai.du(a)intel.com>
Date: Wed Nov 5 21:10:57 2014 -0800
broadwell: add ROM stage pre console init call back
Serial port on ITE 8772 SuperIO must be initialized before
console_init is called. So the pre console init callback
is added to let mainboard code do proper initialization.
Change-Id: Iaa3e4b9c6e7ce77a7b9a6b9ecedd8ea54f3141dc
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 71ee2fd470e19fa4854f895678445b05c17761c1
Original-Change-Id: I594e6e4a72f65744deca5cad666eb3b227adeb24
Original-Signed-off-by: Wenkai Du <wenkai.du(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/227933
Original-Reviewed-by: Kenji Chen <kenji.chen(a)intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-by: Rajmohan Mani <rajmohan.mani(a)intel.com>
Original-Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
---
src/soc/intel/broadwell/include/soc/romstage.h | 1 +
src/soc/intel/broadwell/romstage/romstage.c | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h
index 946d1d0..b636223 100644
--- a/src/soc/intel/broadwell/include/soc/romstage.h
+++ b/src/soc/intel/broadwell/include/soc/romstage.h
@@ -57,4 +57,5 @@ int smbus_read_byte(unsigned device, unsigned address);
int early_spi_read(u32 offset, u32 size, u8 *buffer);
int early_spi_read_wpsr(u8 *sr);
+void mainboard_pre_console_init(void);
#endif
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 31d4f88..11e14d7 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -61,6 +61,10 @@ void * asmlinkage romstage_main(unsigned long bist,
/* PCH Early Initialization */
pch_early_init();
+ /* Call into mainboard pre console init. Needed to enable serial port
+ on IT8772 */
+ mainboard_pre_console_init();
+
/* Start console drivers */
console_init();
@@ -149,4 +153,6 @@ int vboot_get_sw_write_protect(void)
/* Return unprotected status if status read fails. */
return (early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80));
}
+
+void __attribute__((weak)) mainboard_pre_console_init(void) {}
#endif