Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9499
-gerrit
commit 0158790a0e966082eea27bfd33c8e0ef871b8c00
Author: Ben Zhang <benzh(a)chromium.org>
Date: Fri Nov 21 11:17:53 2014 -0800
samus: Set MICBIAS1 to 2.970V
The default micbias1 voltage is 1.476V (1.8V * 0.82) which does
not match what's specified on the schematic. This patch sets
the voltage to 2.970V (3.3V * 0.90) according to the schematic.
BUG=chrome-os-partner:32953
BRANCH=samus
TEST=Set MICBIAS to 2.970V on Samus and verified with a scope
Change-Id: I1ced834a5afe2de3fccf4bcff8ec9c8e5718f60a
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 176f9272801a3de5ed6fc05ade06042e2a2c0a5c
Original-Change-Id: Icdbc1b5f65fe28591d54544372bdc2dacb50e9c1
Original-Signed-off-by: Ben Zhang <benzh(a)chromium.org>
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241178
---
src/mainboard/google/samus/acpi/mainboard.asl | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl
index 54a46d5..287f595 100644
--- a/src/mainboard/google/samus/acpi/mainboard.asl
+++ b/src/mainboard/google/samus/acpi/mainboard.asl
@@ -177,6 +177,7 @@ Scope (\_SB.PCI0.I2C0)
Name (_UID, 1)
Name (WAKE, 45) /* DSP_INT (use as codec wake) */
+ Name (MB1, 1) /* MICBIAS1 = 2.970V */
Name (DCLK, 0) /* RT5677_DMIC_CLK1 */
Name (PCLK, 1) /* RT5677_PDM_CLK_DIV2 (~3MHz) */
Name (IN1, 1) /* IN1 differential */
@@ -193,6 +194,7 @@ Scope (\_SB.PCI0.I2C0)
Name (_DSD, Package () {
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
+ Package () { "realtek,micbias1", 1 },
Package () { "realtek,in1-differential", 1 },
Package () { "realtek,in2-differential", 0 },
Package () { "realtek,lout1-differential", 1 },
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9496
-gerrit
commit ad2f9a31f5f665d1cbebba0b33bbc9b1e5f2722e
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Sun Jan 18 14:14:17 2015 -0800
samus: Adjust SATA Gen3 TX voltage amplitude
Reduce the SATA Gen3 TX voltage amplitude by 210mV based
on the provided test results to help with SATA validation.
BUG=chrome-os-partner:34121
BRANCH=samus
TEST=build and boot on samus and ensure SATA is still working,
firmware image will be provided for full validation.
Change-Id: I574d2f457b7b6831a339602a4165e959a0e2ee7d
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 9500ec152d8f9c90513811b1a92d1a8c155f514a
Original-Change-Id: I233fa1a9a7f2877a97ef6834304680f82b958e82
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241800
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
---
src/mainboard/google/samus/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb
index 0ca7405..3eaea40 100644
--- a/src/mainboard/google/samus/devicetree.cb
+++ b/src/mainboard/google/samus/devicetree.cb
@@ -43,6 +43,7 @@ chip soc/intel/broadwell
register "gpe0_en_4" = "0x00000000"
register "sata_port_map" = "0x1"
+ register "sata_port0_gen3_tx" = "0x72"
register "sio_acpi_mode" = "1"
# Set I2C0 to 1.8V
the following patch was just integrated into master:
commit 120aec0902663d2ed942c1542217791c46b8e406
Author: Julius Werner <jwerner(a)chromium.org>
Date: Wed Oct 22 14:12:50 2014 -0700
serial: Combine Tegra and Rockchip UARTs to generic 8250_mmio32
We have two drivers for a 100%-identical peripheral right now, mostly
because we couldn't come up with a good common name for it back when we
checked it in. That seems like a pretty silly reason in the long run.
Both Tegra and Rockchip SoCs contain UARTs that use the common 8250
register interface (at least for the very basic byte-per-byte transmit
and receive parts we care about), memory-mapped with a 32-bit register
stride. This patch combines them to a single 8250_mmio32 driver (which
also fixes a problem when booting Rockchip without serial enabled, since
that driver forgot to check for serial initialization when registering
its console drivers). The register accesses are done using readl/writel
(as Rockchip did before), since the registers are documented as 32-bit
length (with top 24 bits RAZ/WI), although the Tegra SoC doesn't enforce
APB accesses to have the full word length. Also fixed checkpatch stuff.
A day may come when we can also merge this driver into the (completely
different, with more complicated features and #ifdefs) 8250 driver for
x86 (which has MMIO support for 8-bit register stride only), both here
and in coreboot. But it is not this day. This day I just want to get rid
of a 99% identical file without expending too much effort.
BUG=None
TEST=Booted on Veyron_Pinky and Nyan_Blaze with and without serial
enabled, both worked fine (although Veyron has another kernel issue).
Change-Id: I85c004a75cc5aa7cb40098002d3e00a62c1c5f2d
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: e7959c19356d2922aa414866016540ad9ee2ffa8
Original-Change-Id: Ib84d00f52ff2c48398c75f77f6a245e658ffdeb9
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/225102
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9387
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9387 for details.
-gerrit
the following patch was just integrated into master:
commit 907fd12cf6c10b2a3d1edec09b23be5eeb4b9643
Author: Daisuke Nojiri <dnojiri(a)chromium.org>
Date: Fri Oct 24 09:38:31 2014 -0700
armv7-m: set stack pointer to _estack
this change sets the stack pointer to the value specified in
memlayout.ld before jumping to the bootblock.
BUG=none
BRANCH=ToT
TEST=Built cosmos and all other current boards.
Change-Id: Ic1b790f27bce431124ba70cc2d3d3607c537564b
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: d50fd02db8bf10147fd808f3030e6297b9ca0aad
Original-Change-Id: I4bb8cea7435d2a0e2c1ced050c3366d2e636cb8a
Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/225420
Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9384
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9384 for details.
-gerrit
the following patch was just integrated into master:
commit c5a4c124317ee9ec444e661420e572e78fe19d08
Author: Daisuke Nojiri <dnojiri(a)chromium.org>
Date: Thu Oct 23 11:51:18 2014 -0700
armv7-m: add bootblock entry point
this adds an entry point jumping to main for the bootblock.
BUG=None
BRANCH=ToT
TEST=Built coreboot for cosmos
Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Change-Id: I1c9ea6ba63a1058e09613d969fe00308260037be
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 662d0083f25008b55b9bc5fbce9e30e6b80c2c65
Original-Change-Id: I74f2f5e3b3961ab54a7913e6b3a3ab0e6fd813a3
Original-Reviewed-on: https://chromium-review.googlesource.com/225205
Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9382
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9382 for details.
-gerrit
the following patch was just integrated into master:
commit af3b2a1873f20cbffb2cf3b585d5020dc1e594fc
Author: Daisuke Nojiri <dnojiri(a)chromium.org>
Date: Thu Oct 23 12:39:11 2014 -0700
armv7-m: add empty cache routines
armv7-m does not have cache but adding empty cache functions allow us to
transparently use code handling entering and leaving stages.
BUG=none
BRANCH=ToT
TEST=Built coreboot for cosmos
Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Change-Id: I23415b273c90401cd81f2bc94b2d69958f134c6a
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 960453bf5d5fbf7dc75343b1cccaa62b6b8ec30c
Original-Change-Id: Ief0c8a949e7e14d68473e7a093a8642d6058ccc6
Original-Reviewed-on: https://chromium-review.googlesource.com/225206
Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9383
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9383 for details.
-gerrit
the following patch was just integrated into master:
commit 37083903ff94510bc8f656d3b596efcf5225b8c5
Author: Daisuke Nojiri <dnojiri(a)chromium.org>
Date: Tue Oct 21 11:22:54 2014 -0700
bg4cd: set bootblock and verstage architecture to armv7-m
this sets the proper architecture for bg4cd's bcm, which is armv7-m.
BUG=none
TEST=built cosmos
BRANCH=none
Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Change-Id: I6af25080c10a245a1fc884acb2a705f0b5d96309
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: fc04fd26f1f2634115fc9bcefd6eee5611c80659
Original-Change-Id: I3334c3ba27a3582ce0fe5b484a5a22c8441a4c11
Original-Reviewed-on: https://chromium-review.googlesource.com/224773
Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9381
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9381 for details.
-gerrit