Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9495
-gerrit
commit 64ac9da99d6eb5a4b4559691748b1ac8cb8a400c
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Sun Jan 18 14:06:42 2015 -0800
broadwell: Preserve VbNv around cmos_init
To ensure that boot flags (legacy, usb, signed-only) are
properly restored from CMOS and used in the first boot after
a battery removal or RTC reset then the VbNv region needs to
be preserved around the cmos_init call.
When using vboot firmware selection and VbNv is stored in CMOS
then that region of CMOS will have been re-initialized by the
time we call cmos_init and reset CMOS if the chipset flag was
set indicating a problem.
BUG=chrome-os-partner:35240
BRANCH=broadwell
TEST=manual testing on samus:
1) boot in dev mode, enable dev_boot_legacy and ensure it works
2) on EC console pulse PCH_RTCRST_L low for a second
3) ensure first boot after RTC reset will still boot legacy mode
4) remove battery for a time
5) ensure first boot after battery is re-inserted will still
boot legacy mode
Change-Id: Ica256bbdcba6d4616957ff38e63914dd15f645c6
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 881c7841c95dec392a66eef38a7112c1f385fdfa
Original-Change-Id: I4c33f183ba4b301d68ae31c41fc6663f3be857b0
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241529
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/broadwell/lpc.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 6ebc758..9a4c65c 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -49,6 +49,10 @@
#include <arch/acpigen.h>
#include <cpu/cpu.h>
+#if IS_ENABLED(CONFIG_CHROMEOS)
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
+
static void pch_enable_ioapic(struct device *dev)
{
u32 reg32;
@@ -174,6 +178,25 @@ static void pch_power_options(device_t dev)
enable_alt_smi(config->alt_gp_smi_en);
}
+#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)
+/*
+ * Preserve Vboot NV data when clearing CMOS as it will
+ * have been re-initialized already by Vboot firmware init.
+ */
+static void pch_cmos_init_preserve(int reset)
+{
+ uint8_t vbnv[CONFIG_VBNV_SIZE];
+
+ if (reset)
+ read_vbnv(vbnv);
+
+ cmos_init(reset);
+
+ if (reset)
+ save_vbnv(vbnv);
+}
+#endif
+
static void pch_rtc_init(struct device *dev)
{
u8 reg8;
@@ -187,7 +210,11 @@ static void pch_rtc_init(struct device *dev)
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
}
+#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)
+ pch_cmos_init_preserve(rtc_failed);
+#else
cmos_init(rtc_failed);
+#endif
}
static const struct reg_script pch_misc_init_script[] = {
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9492
-gerrit
commit 59b984094ed9a910dd216900b055810a29b1e6eb
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Jan 15 13:24:38 2015 -0800
samus: Add clear_recovery_mode_switch function
In order for recovery request to be cleared with software sync disabled
we need to implement this function in the mainboard.
BUG=chrome-os-partner:28234
BRANCH=samus
TEST=boot in recovery with software sync disabled, ensure that the next
boot will not boot in recovery again.
Change-Id: Ie9c845396dfc6ab65296b2f18a86e23590c833d6
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 430f85608cc3b59a68a86dba64ffe428bfc216a9
Original-Change-Id: Iac15b6a1b23cc971231339439bceb013f4a031bd
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241052
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
---
src/mainboard/google/samus/chromeos.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/mainboard/google/samus/chromeos.c b/src/mainboard/google/samus/chromeos.c
index fc7acff..fab06e8 100644
--- a/src/mainboard/google/samus/chromeos.c
+++ b/src/mainboard/google/samus/chromeos.c
@@ -92,6 +92,15 @@ int get_recovery_mode_switch(void)
#endif
}
+int clear_recovery_mode_switch(void)
+{
+ const uint32_t kb_rec_mask =
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY);
+
+ /* Unconditionally clear the EC recovery request. */
+ return google_chromeec_clear_events_b(kb_rec_mask);
+}
+
int get_write_protect_state(void)
{
return get_gpio(CROS_WP_GPIO);
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9490
-gerrit
commit 718ae861309aa13a140fe6897801c1d2df6d354a
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Jan 14 17:33:00 2015 -0800
broadwell: Turn off panel backlight in S5 SMI handler
In order for some panels to meet spec when the system is put
into S5 by way of power button during firmware (i.e. not by
the OS) then it needs to turn off the backlight and give it
time to turn off before going into S5.
If the OS properly sequences the panel down then the backlight
enable bit will not be set in this step and nothing will happen.
BUG=chrome-os-partner:33994
BRANCH=broadwell
TEST=build and boot on samus
Change-Id: Ic86f388218f889b1fe690cc1bfc5c3e233e95115
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: e3c9c131a87bae380e1fd3f96c9ad780441add56
Original-Change-Id: I43c5aee8e32768fc9e82790c9f7ceda0ed17ed13
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240852
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
---
src/soc/intel/broadwell/smihandler.c | 43 ++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index 5004a6a..63c9373 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -36,6 +36,7 @@
#include <soc/rcba.h>
#include <soc/smm.h>
#include <soc/xhci.h>
+#include <drivers/intel/gma/i915_reg.h>
static u8 smm_initialized = 0;
@@ -109,6 +110,45 @@ static void busmaster_disable_on_bus(int bus)
}
}
+/*
+ * Turn off the backlight if it is on, and wait for the specified
+ * backlight off delay. This will allow panel power timings to meet
+ * spec and prevent brief garbage on the screen when turned off
+ * during firmware with power button triggered SMI.
+ */
+static void backlight_off(void)
+{
+ void *reg_base;
+ uint32_t pp_ctrl;
+ uint32_t bl_off_delay;
+
+ reg_base = (void *)((uintptr_t)pci_read_config32(SA_DEV_IGD, PCI_BASE_ADDRESS_0) & ~0xf);
+
+ /* Check if backlight is enabled */
+ pp_ctrl = read32(reg_base + PCH_PP_CONTROL);
+ if (!(pp_ctrl & EDP_BLC_ENABLE))
+ return;
+
+ /* Enable writes to this register */
+ pp_ctrl &= ~PANEL_UNLOCK_MASK;
+ pp_ctrl |= PANEL_UNLOCK_REGS;
+
+ /* Turn off backlight */
+ pp_ctrl &= ~EDP_BLC_ENABLE;
+
+ write32(reg_base + PCH_PP_CONTROL, pp_ctrl);
+ read32(reg_base + PCH_PP_CONTROL);
+
+ /* Read backlight off delay in 100us units */
+ bl_off_delay = read32(reg_base + PCH_PP_OFF_DELAYS);
+ bl_off_delay &= PANEL_LIGHT_OFF_DELAY_MASK;
+ bl_off_delay *= 100;
+
+ /* Wait for backlight to turn off */
+ udelay(bl_off_delay);
+
+ printk(BIOS_INFO, "Backlight turned off\n");
+}
static void southbridge_smi_sleep(void)
{
@@ -170,6 +210,9 @@ static void southbridge_smi_sleep(void)
case SLP_TYP_S5:
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
+ /* Turn off backlight if needed */
+ backlight_off();
+
/* Disable all GPE */
disable_all_gpe();
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9491
-gerrit
commit 7a12c778afc4beabb4e7956a0d2f7018e54b48c3
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Jan 14 17:36:08 2015 -0800
samus: Set current backlight PWM value
With recent changes in the 3.14 kernel and the switch to not
using X the panel backlight is not geting turned on until
chrome is started which means the splash screen is not visible.
If we set the backlight PWM in coreboot then it will at least
turn on for the early boot process.
BUG=chrome-os-partner:31549
BRANCH=samus
TEST=boot on samus in normal mode and see the boot splash logo
Change-Id: I81e6b90617acb181b4de3365f8f56ec3b846b78b
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: f850fe3faff268a64f18e6bd176ec1126b921e3b
Original-Change-Id: I622bef8af9bb6b753fe228b33ecdc4aae76af131
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240853
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
---
src/mainboard/google/samus/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb
index 26b7b41..0ca7405 100644
--- a/src/mainboard/google/samus/devicetree.cb
+++ b/src/mainboard/google/samus/devicetree.cb
@@ -11,7 +11,7 @@ chip soc/intel/broadwell
# Set backlight PWM values for eDP
register "gpu_cpu_backlight" = "0x00000200"
- register "gpu_pch_backlight" = "0x04000000"
+ register "gpu_pch_backlight" = "0x04000200"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9489
-gerrit
commit 563848fb56b30e2ce255433b7ab72f562729a89a
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Jan 14 17:30:20 2015 -0800
broadwell: Skip steps when disabling PCIe port
When disabling PCIe ports skip steps if no card is detected.
This prevents the loop from timing out on each empty slot.
BUG=chrome-os-partner:31424
BRANCH=broadwell
TEST=build and boot on samus, check that this code is
no longer timing out when disabling PCIe ports
Change-Id: I84ee0e0e325784b3af06abe70420c07cf6e13ed2
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 4d759e2350dd00ceb7df196ac7008729dc1e4cef
Original-Change-Id: Idd88f0f1191a5465a0d8dcca07b5c3a5c5ca8855
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240851
Original-Reviewed-by: Wenkai Du <wenkai.du(a)intel.com>
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
---
src/soc/intel/broadwell/pcie.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index 4476fe4..e217149 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -321,12 +321,12 @@ static void root_port_commit_config(void)
do {
reg32 = pci_read_config32(dev, 0x328);
n++;
- if (((reg32 & 0xff000000) == 0x01000000) || (n > 500))
+ if (((reg32 & 0xff000000) == 0x01000000) || (n > 50))
break;
udelay(100);
} while (1);
- if (n > 500)
+ if (n > 50)
printk(BIOS_DEBUG, "%s: Timeout waiting for 328h\n",
dev_path(dev));
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9502
-gerrit
commit 41f1a0ae4909ee0c8ea17207f5b69f8ef84bf424
Author: Julius Werner <jwerner(a)chromium.org>
Date: Fri Feb 6 15:34:14 2015 -0800
broadwell: Correct XHCI offset for USB 3.0 ports
Looks like Intel has added two more USB 2.0 ports from LynxPoint to
Broadwell, which shifted the port offsets of the USB 3.0 ports behind
them. The USB 2.0 ports are now 0x480 to 0x520 and the 3.0 ones 0x530 to
0x560 (at least according to what my kernel seems to think). The offset
of the first USB 3.0 port is hardcoded and seems to have been copied
over without accounting for this, meaning when we try to operate on all
USB 3.0 ports we actually operate on the last two 2.0 and the first two
3.0 ports instead.
This patch should fix the bug for now. In the future, we might want to
consider dynamically detecting port locations through the Protocol
Capability structures at the end of the XHCI register set instead.
BRANCH=samus
BUG=chrome-os-partner:35320
TEST=TODO
Change-Id: Ifab6e484980fd4cd0daf80ceb292ddced2ab1aea
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 525f359c0b6b95b260add2b4617fd86119d69397
Original-Change-Id: Ic2becf2b043612270909ceef66e7d58efc8fcbe1
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/247351
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-by: Todd Broch <tbroch(a)chromium.org>
---
src/soc/intel/broadwell/include/soc/xhci.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/soc/intel/broadwell/include/soc/xhci.h
index 3f4fb4e..2b899a3 100644
--- a/src/soc/intel/broadwell/include/soc/xhci.h
+++ b/src/soc/intel/broadwell/include/soc/xhci.h
@@ -39,7 +39,7 @@
#define XHCI_USB3PDO 0xe8
/* XHCI Memory Registers */
-#define XHCI_USB3_PORTSC(port) (0x510 + (port * 0x10))
+#define XHCI_USB3_PORTSC(port) (0x530 + (port * 0x10))
#define XHCI_USB3_PORTSC_CHST (0x7f << 17)
#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */
#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9503
-gerrit
commit a1269e7824b63016b60b08d2a56de507422dcba6
Author: Julius Werner <jwerner(a)chromium.org>
Date: Thu Feb 5 12:55:45 2015 -0800
elog: Fix regression that caused elog to omit "System boot" event
CL:243671 moved the initialization of elog_initialized around, which is
now unfortunately so late that the ELOG_TYPE_BOOT event gets omitted
because the code believes the log to be broken at that time. Good thing
we now have a FAFT test for these things that I had of course been too
lazy to run. -.-
The real reason for moving that line was to put it after any point in
elog_init() that could still error out. The problem is that we might add
the "cleared" event before we try to shrink (which can fail and cause an
error)... but those two things cannot happen at the same time, so it
should be okay to flip them around and mark the elog as initialized in
between.
BRANCH=none
BUG=chrome-os-partner:35940
TEST=Ran firmware_EventLog on a Pinky, manually confirmed that I once
again get "System boot" events.
Change-Id: I12dcf4a8e47d302f6cd317194912c31db502bbaf
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 4a1c0b861017ca25229b1042c4b37dda33e869f9
Original-Change-Id: I4103779790e1a8a53ecabffd4316724035928ce6
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/246715
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/drivers/elog/elog.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c
index 8bc8a07..6d32878 100644
--- a/src/drivers/elog/elog.c
+++ b/src/drivers/elog/elog.c
@@ -606,15 +606,17 @@ int elog_init(void)
" shrink size %d\n", total_size,
CONFIG_ELOG_FULL_THRESHOLD, CONFIG_ELOG_SHRINK_SIZE);
- /* Log a clear event if necessary */
- if (event_count == 0)
- elog_add_event_word(ELOG_TYPE_LOG_CLEAR, total_size);
+ elog_initialized = ELOG_INITIALIZED;
/* Shrink the log if we are getting too full */
if (next_event_offset >= CONFIG_ELOG_FULL_THRESHOLD)
if (elog_shrink() < 0)
return -1;
+ /* Log a clear event if necessary */
+ if (event_count == 0)
+ elog_add_event_word(ELOG_TYPE_LOG_CLEAR, total_size);
+
#if !defined(__SMM__)
/* Log boot count event except in S3 resume */
#if CONFIG_ELOG_BOOT_COUNT == 1
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9500
-gerrit
commit cb85717ef65ed1783cc90d3fdcf01cd7e06c82a4
Author: Ben Zhang <benzh(a)chromium.org>
Date: Wed Dec 10 17:44:18 2014 -0800
samus: Use codec internal 1.8V as DACREF source
This is needed for audio playback after we disconnect PP1800_CODEC
from DACREF to avoid noise coupled on PP1800_CODEC, which makes
recording noisy.
For recording, DACREF comes from mic vref pump voltage.
For playback, DACREF comes from internal 1.8V.
BUG=chrome-os-partner:32953
BRANCH=samus
TEST=Set MICBIAS to 2.970V on Samus, playback/recording is clean
Change-Id: I65fb6dbfab54c7c4de6496fd4a0d666baead28ec
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 3e62a61f6cf6042f6d653a827698b55ac86e2d2b
Original-Change-Id: I27430691e469dd7f4056d99438ce080062b58b9a
Original-Signed-off-by: Ben Zhang <benzh(a)chromium.org>
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241179
---
src/mainboard/google/samus/acpi/mainboard.asl | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl
index 287f595..2140898 100644
--- a/src/mainboard/google/samus/acpi/mainboard.asl
+++ b/src/mainboard/google/samus/acpi/mainboard.asl
@@ -178,6 +178,7 @@ Scope (\_SB.PCI0.I2C0)
Name (WAKE, 45) /* DSP_INT (use as codec wake) */
Name (MB1, 1) /* MICBIAS1 = 2.970V */
+ Name (DACR, 1) /* Use codec internal 1.8V as DACREF source */
Name (DCLK, 0) /* RT5677_DMIC_CLK1 */
Name (PCLK, 1) /* RT5677_PDM_CLK_DIV2 (~3MHz) */
Name (IN1, 1) /* IN1 differential */
@@ -195,6 +196,7 @@ Scope (\_SB.PCI0.I2C0)
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "realtek,micbias1", 1 },
+ Package () { "realtek,internal-dacref-en", 1 },
Package () { "realtek,in1-differential", 1 },
Package () { "realtek,in2-differential", 0 },
Package () { "realtek,lout1-differential", 1 },