Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9410
-gerrit
commit bf1970ffb6524c7d6b381c99b8f0933f9c452fe6
Author: Julius Werner <jwerner(a)chromium.org>
Date: Thu Nov 6 17:32:58 2014 -0800
rk3288: Adjust CBFS header and ROM offsets
Our CBFS header offset on rk3288 was very low and overlapped with the
end of the bootblock on recent Pinky builds. This can create all kinds
of fun effects like BSS variables suddenly being initialized to
something else than zero, in an effect that jumps somewhere else for
every slightest code size change.
This patch moves the CBFS header offset up a bit and the CBFS ROM offset
down (because there's really no point in leaving such a large gap). This
resolves our immediate booting problems, and I'll also start on a patch
to add further checks somewhere that catch these overlaps in the future.
BRANCH=None
BUG=None
TEST=Created a Pinky image from the exact same commit version as the
official 6443.0.0 build, with a KERNELREVISION string of the exact same
length as the builder (which for some arcane reason is different than
running emerge locally, shifting the whole bootblock around with it).
Confirmed that I saw the same "Not enough room for another
sub-pagetable!" hang, and that this patch fixes it.
Change-Id: I9e59a282b3cd0af3b0d224d64c10b7c4d312ad02
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 1a142cd2c51c6f51a1597c21ad513feb151e0938
Original-Change-Id: I8be5b7b7e87021cc1b3a91d336e8d233546ee188
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228326
Original-Reviewed-by: Gediminas Ramanauskas <gedis(a)chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
---
src/soc/rockchip/rk3288/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig
index 70951a5..ada3d58 100644
--- a/src/soc/rockchip/rk3288/Kconfig
+++ b/src/soc/rockchip/rk3288/Kconfig
@@ -49,10 +49,10 @@ config BOOTBLOCK_ROM_OFFSET
config CBFS_HEADER_ROM_OFFSET
hex
- default 0x0008000
+ default 0x0010000
config CBFS_ROM_OFFSET
hex
- default 0x0018000
+ default 0x0010100
endif
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9411
-gerrit
commit 08a8271147a6af22da040fa0fd22d1f7b1edb7ce
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Thu Nov 6 15:09:27 2014 -0800
gpio: cosmetic changes to tristate_gpios.c
This patch makes a few cosmetic changes:
- Rename tristate_gpios.c to gpio.c since it will soon be used for
binary GPIOs as well.
- Rename gpio_get_tristates() to gpio_base3_value() - The binary
version will be called gpio_base2_value().
- Updates call sites.
- Change the variable name "id" to something more generic.
BUG=none
BRANCH=none
TEST=compiled for veyron_pinky and storm
Change-Id: Iab7e32f4e9d70853f782695cfe6842accff1df64
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: c47d0f33ea1a6e9515211b834009cf47a171953f
Original-Change-Id: I36d88c67cb118efd1730278691dc3e4ecb6055ee
Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228324
---
src/include/gpio.h | 4 +-
src/lib/Makefile.inc | 2 +-
src/lib/gpio.c | 82 +++++++++++++++++++++++++++++++
src/lib/tristate_gpios.c | 82 -------------------------------
src/mainboard/google/nyan_big/boardid.c | 2 +-
src/mainboard/google/nyan_blaze/boardid.c | 2 +-
src/mainboard/google/rush_ryu/boardid.c | 2 +-
src/mainboard/google/storm/boardid.c | 6 +--
8 files changed, 91 insertions(+), 91 deletions(-)
diff --git a/src/include/gpio.h b/src/include/gpio.h
index b2a341d..e54b156 100644
--- a/src/include/gpio.h
+++ b/src/include/gpio.h
@@ -37,12 +37,12 @@ void gpio_output(gpio_t gpio, int value);
/*
* Read the value presented by the set of GPIOs, when each pin is interpreted
* as a base-3 digit (LOW = 0, HIGH = 1, Z/floating = 2).
- * Example: X1 = Z, X2 = 1 -> gpio_get_tristates({GPIO(X1), GPIO(X2)}) = 5
+ * Example: X1 = Z, X2 = 1 -> gpio_base3_value({GPIO(X1), GPIO(X2)}) = 5
* BASE3() from <base3.h> can generate numbers to compare the result to.
*
* gpio[]: pin positions to read. gpio[0] is less significant than gpio[1].
* num_gpio: number of pins to read.
*/
-int gpio_get_tristates(gpio_t gpio[], int num_gpio);
+int gpio_base3_value(gpio_t gpio[], int num_gpio);
#endif /* __SRC_INCLUDE_GPIO_H__ */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 079c855..0959359 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -92,7 +92,7 @@ ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += edid.c
ramstage-y += memrange.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c
ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c
-ramstage-$(CONFIG_TERTIARY_BOARD_ID) += tristate_gpios.c
+ramstage-$(CONFIG_TERTIARY_BOARD_ID) += gpio.c
ramstage-$(CONFIG_GENERIC_UDELAY) += timer.c
romstage-y += cbmem_common.c dynamic_cbmem.c
diff --git a/src/lib/gpio.c b/src/lib/gpio.c
new file mode 100644
index 0000000..3a646e0
--- /dev/null
+++ b/src/lib/gpio.c
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <base3.h>
+#include <console/console.h>
+#include <delay.h>
+#include <gpio.h>
+
+int gpio_base3_value(gpio_t gpio[], int num_gpio)
+{
+ /*
+ * GPIOs which are tied to stronger external pull up or pull down
+ * will stay there regardless of the internal pull up or pull
+ * down setting.
+ *
+ * GPIOs which are floating will go to whatever level they're
+ * internally pulled to.
+ */
+
+ static const char tristate_char[] = {[0] = '0', [1] = '1', [Z] = 'Z'};
+ int temp;
+ int index;
+ int result = 0;
+ char value[num_gpio];
+
+ /* Enable internal pull up */
+ for (index = 0; index < num_gpio; ++index)
+ gpio_input_pullup(gpio[index]);
+
+ /* Wait until signals become stable */
+ udelay(10);
+
+ /* Get gpio values at internal pull up */
+ for (index = 0; index < num_gpio; ++index)
+ value[index] = gpio_get(gpio[index]);
+
+ /* Enable internal pull down */
+ for (index = 0; index < num_gpio; ++index)
+ gpio_input_pulldown(gpio[index]);
+
+ /* Wait until signals become stable */
+ udelay(10);
+
+ /*
+ * Get gpio values at internal pull down.
+ * Compare with gpio pull up value and then
+ * determine a gpio final value/state:
+ * 0: pull down
+ * 1: pull up
+ * 2: floating
+ */
+ printk(BIOS_DEBUG, "Reading tristate GPIOs: ");
+ for (index = num_gpio - 1; index >= 0; --index) {
+ temp = gpio_get(gpio[index]);
+ temp |= ((value[index] ^ temp) << 1);
+ printk(BIOS_DEBUG, "%c ", tristate_char[temp]);
+ result = (result * 3) + temp;
+ }
+ printk(BIOS_DEBUG, "= %d\n", result);
+
+ /* Disable pull up / pull down to conserve power */
+ for (index = 0; index < num_gpio; ++index)
+ gpio_input(gpio[index]);
+
+ return result;
+}
diff --git a/src/lib/tristate_gpios.c b/src/lib/tristate_gpios.c
deleted file mode 100644
index 0967a8f..0000000
--- a/src/lib/tristate_gpios.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <base3.h>
-#include <console/console.h>
-#include <delay.h>
-#include <gpio.h>
-
-int gpio_get_tristates(gpio_t gpio[], int num_gpio)
-{
- /*
- * GPIOs which are tied to stronger external pull up or pull down
- * will stay there regardless of the internal pull up or pull
- * down setting.
- *
- * GPIOs which are floating will go to whatever level they're
- * internally pulled to.
- */
-
- static const char tristate_char[] = {[0] = '0', [1] = '1', [Z] = 'Z'};
- int temp;
- int index;
- int id = 0;
- char value[num_gpio];
-
- /* Enable internal pull up */
- for (index = 0; index < num_gpio; ++index)
- gpio_input_pullup(gpio[index]);
-
- /* Wait until signals become stable */
- udelay(10);
-
- /* Get gpio values at internal pull up */
- for (index = 0; index < num_gpio; ++index)
- value[index] = gpio_get(gpio[index]);
-
- /* Enable internal pull down */
- for (index = 0; index < num_gpio; ++index)
- gpio_input_pulldown(gpio[index]);
-
- /* Wait until signals become stable */
- udelay(10);
-
- /*
- * Get gpio values at internal pull down.
- * Compare with gpio pull up value and then
- * determine a gpio final value/state:
- * 0: pull down
- * 1: pull up
- * 2: floating
- */
- printk(BIOS_DEBUG, "Reading tristate GPIOs: ");
- for (index = num_gpio - 1; index >= 0; --index) {
- temp = gpio_get(gpio[index]);
- temp |= ((value[index] ^ temp) << 1);
- printk(BIOS_DEBUG, "%c ", tristate_char[temp]);
- id = (id * 3) + temp;
- }
- printk(BIOS_DEBUG, "= %d\n", id);
-
- /* Disable pull up / pull down to conserve power */
- for (index = 0; index < num_gpio; ++index)
- gpio_input(gpio[index]);
-
- return id;
-}
diff --git a/src/mainboard/google/nyan_big/boardid.c b/src/mainboard/google/nyan_big/boardid.c
index b420f5a..1905c79 100644
--- a/src/mainboard/google/nyan_big/boardid.c
+++ b/src/mainboard/google/nyan_big/boardid.c
@@ -29,7 +29,7 @@ uint8_t board_id(void)
[1] = GPIO(T1), [0] = GPIO(Q3),}; /* Q3 is LSB */
if (id < 0) {
- id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio));
+ id = gpio_base3_value(gpio, ARRAY_SIZE(gpio));
printk(BIOS_SPEW, "Board TRISTATE ID: %d.\n", id);
}
diff --git a/src/mainboard/google/nyan_blaze/boardid.c b/src/mainboard/google/nyan_blaze/boardid.c
index b420f5a..1905c79 100644
--- a/src/mainboard/google/nyan_blaze/boardid.c
+++ b/src/mainboard/google/nyan_blaze/boardid.c
@@ -29,7 +29,7 @@ uint8_t board_id(void)
[1] = GPIO(T1), [0] = GPIO(Q3),}; /* Q3 is LSB */
if (id < 0) {
- id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio));
+ id = gpio_base3_value(gpio, ARRAY_SIZE(gpio));
printk(BIOS_SPEW, "Board TRISTATE ID: %d.\n", id);
}
diff --git a/src/mainboard/google/rush_ryu/boardid.c b/src/mainboard/google/rush_ryu/boardid.c
index 37f6292..9c4d184 100644
--- a/src/mainboard/google/rush_ryu/boardid.c
+++ b/src/mainboard/google/rush_ryu/boardid.c
@@ -30,7 +30,7 @@ uint8_t board_id(void)
if (id < 0) {
gpio_t gpio[] = {[1] = BD_ID1, [0] = BD_ID0}; /* ID0 is LSB */
- id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio));
+ id = gpio_base3_value(gpio, ARRAY_SIZE(gpio));
}
return id;
diff --git a/src/mainboard/google/storm/boardid.c b/src/mainboard/google/storm/boardid.c
index c32567e..c4f54a5 100644
--- a/src/mainboard/google/storm/boardid.c
+++ b/src/mainboard/google/storm/boardid.c
@@ -25,8 +25,8 @@
/*
* Storm boards dedicate to the board ID three GPIOs in tertiary mode: 29, 30
* and 68. On proto0 GPIO68 is used and tied low, so it reads as 'zero' by
- * gpio_get_tristates(), whereas the other two pins are not connected
- * and read as 'two'. This results in gpio_get_tristates() returning
+ * gpio_base3_value(), whereas the other two pins are not connected
+ * and read as 'two'. This results in gpio_base3_value() returning
* 8 on proto0.
*
* Three tertitiary signals could represent 27 different values. To make
@@ -45,7 +45,7 @@ static uint8_t get_board_id(void)
gpio_t hw_rev_gpios[] = {[2] = 68, [1] = 30, [0] = 29}; /* 29 is LSB */
int offset = 19;
- bid = gpio_get_tristates(hw_rev_gpios, ARRAY_SIZE(hw_rev_gpios));
+ bid = gpio_base3_value(hw_rev_gpios, ARRAY_SIZE(hw_rev_gpios));
bid = (bid + offset) % 27;
printk(BIOS_INFO, "Board ID %d\n", bid);
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9412
-gerrit
commit fdcadf678cc03edc16212686694f36710f2aba67
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Thu Nov 6 15:05:35 2014 -0800
gpio: add a function to read GPIO array as base-2 value
This adds gpio_base2_value() which reads an array of 2-state
GPIOs and returns a base-2 value, where gpio[0] represents the
least significant bit.
BUG=none
BRANCH=none
TEST=tested with follow-up patches for pinky
Change-Id: I0d6bfac369da0d68079a38de0988c7b59d269a97
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 27873b7a9ea237d13f0cbafd10033a8d0f821cbe
Original-Change-Id: Ia7ffc16eb60e93413c0812573b9cf0999b92828e
Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228323
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
src/include/gpio.h | 9 +++++++++
src/lib/gpio.c | 12 ++++++++++++
2 files changed, 21 insertions(+)
diff --git a/src/include/gpio.h b/src/include/gpio.h
index e54b156..7b64ebf 100644
--- a/src/include/gpio.h
+++ b/src/include/gpio.h
@@ -36,6 +36,15 @@ void gpio_output(gpio_t gpio, int value);
/*
* Read the value presented by the set of GPIOs, when each pin is interpreted
+ * as a base-2 digit (LOW = 0, HIGH = 1).
+ *
+ * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1].
+ * num_gpio: number of pins to read.
+ */
+int gpio_base2_value(gpio_t gpio[], int num_gpio);
+
+/*
+ * Read the value presented by the set of GPIOs, when each pin is interpreted
* as a base-3 digit (LOW = 0, HIGH = 1, Z/floating = 2).
* Example: X1 = Z, X2 = 1 -> gpio_base3_value({GPIO(X1), GPIO(X2)}) = 5
* BASE3() from <base3.h> can generate numbers to compare the result to.
diff --git a/src/lib/gpio.c b/src/lib/gpio.c
index 3a646e0..0875538 100644
--- a/src/lib/gpio.c
+++ b/src/lib/gpio.c
@@ -22,6 +22,18 @@
#include <delay.h>
#include <gpio.h>
+int gpio_base2_value(gpio_t gpio[], int num_gpio)
+{
+ int i, result = 0;
+
+ for (i = 0; i < num_gpio; i++) {
+ gpio_input(gpio[i]);
+ result |= gpio_get(gpio[i]) << i;
+ }
+
+ return result;
+}
+
int gpio_base3_value(gpio_t gpio[], int num_gpio)
{
/*
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9413
-gerrit
commit 497225c8c5e08ae3230c85d971dd19cd267bc63c
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Wed Nov 5 14:05:56 2014 -0800
gpio: decouple tristate gpio support from board ID
This deprecates TERTIARY_BOARD_ID. Instead, a board will set
BOARD_ID_SUPPORT (the ones affected already do) which will set
GENERIC_GPIO_SUPPORT and compile the generic GPIO library.
The user is expected to handle the details of how the ID is encoded.
BUG=none
BRANCH=none
TEST=Compiled for peppy, nyan*, storm, and pinky
Change-Id: Iaf1cac6e90b6c931100e9d1b6735684fac86b8a8
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 93db63f419f596160ce2459eb70b3218cc83c09e
Original-Change-Id: I687877e5bb89679d0133bed24e2480216c384a1c
Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228322
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
src/Kconfig | 17 +++++++++--------
src/lib/Makefile.inc | 2 +-
src/mainboard/google/nyan_big/Kconfig | 1 -
src/mainboard/google/nyan_blaze/Kconfig | 1 -
src/mainboard/google/rush_ryu/Kconfig | 1 -
src/mainboard/google/storm/Kconfig | 1 -
6 files changed, 10 insertions(+), 13 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index f94fad4..7c325c2 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -1114,22 +1114,23 @@ config DEBUG_COVERAGE
If enabled, the code coverage hooks in coreboot will output some
information about the coverage data that is dumped.
+config GENERIC_GPIO_LIB
+ bool "Build generic GPIO library"
+ default n
+ help
+ If enabled, compile the generic GPIO library. A "generic" GPIO
+ implies configurability usually found on SoCs, particularly the
+ ability to control internal pull resistors.
+
config BOARD_ID_SUPPORT
bool "Discover board ID and store it in coreboot table"
default n
+ select GENERIC_GPIO_LIB
help
If enabled, coreboot discovers the board id of the hardware it is
running on and reports it through the coreboot table to the rest of
the system.
-config TERTIARY_BOARD_ID
- bool "Interpret board ID GPIOs as tertiary inputs"
- default n
- depends on BOARD_ID_SUPPORT
- help
- Consider each GPIO as being in one of three states: pulled down (0),
- pulled up (1), or not connected (2)
-
endmenu
# These probably belong somewhere else, but they are needed somewhere.
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 0959359..54e0473 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -92,7 +92,7 @@ ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += edid.c
ramstage-y += memrange.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c
ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c
-ramstage-$(CONFIG_TERTIARY_BOARD_ID) += gpio.c
+ramstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
ramstage-$(CONFIG_GENERIC_UDELAY) += timer.c
romstage-y += cbmem_common.c dynamic_cbmem.c
diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig
index 7334472..22958a9 100644
--- a/src/mainboard/google/nyan_big/Kconfig
+++ b/src/mainboard/google/nyan_big/Kconfig
@@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SPI_FLASH
select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
select VIRTUAL_DEV_SWITCH
- select TERTIARY_BOARD_ID
config MAINBOARD_DIR
string
diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig
index 3495919..0902b4f 100644
--- a/src/mainboard/google/nyan_blaze/Kconfig
+++ b/src/mainboard/google/nyan_blaze/Kconfig
@@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_1024
select SPI_FLASH
select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
- select TERTIARY_BOARD_ID
select VIRTUAL_DEV_SWITCH
config MAINBOARD_DIR
diff --git a/src/mainboard/google/rush_ryu/Kconfig b/src/mainboard/google/rush_ryu/Kconfig
index a824f2e..da517da 100644
--- a/src/mainboard/google/rush_ryu/Kconfig
+++ b/src/mainboard/google/rush_ryu/Kconfig
@@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_BOOTBLOCK_INIT
select BOARD_ROMSIZE_KB_4096
select VIRTUAL_DEV_SWITCH
- select TERTIARY_BOARD_ID
select ARCH_SPINTABLE
config MAINBOARD_DIR
diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig
index 3e1e016..5e010fc 100644
--- a/src/mainboard/google/storm/Kconfig
+++ b/src/mainboard/google/storm/Kconfig
@@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_BOOTBLOCK_INIT
select SPI_FLASH
select SPI_FLASH_SPANSION
- select TERTIARY_BOARD_ID
config BOARD_VARIANT_AP148
bool "pick this to build an image for ap148"
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9414
-gerrit
commit 75c4856515636cb3906d56fb390b4e470a399766
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Thu Nov 6 15:22:10 2014 -0800
gpio: compile gpio.c at all stages
Since gpio.c is more generic now and will be used in various
stages (ie for board_id()), compile it for all stages.
BUG=none
BRANCH=none
TEST=compiled for peppy and veyron_pinky
Change-Id: Ib5c73f68db92791dd6b42369f681f9159b7e1c22
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: ef4e40ccf6510d63c4a54451bdfea8da695e387e
Original-Change-Id: I77ec56a77e75e602e8b9406524d36a8f69ce9128
Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228325
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
src/lib/Makefile.inc | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 54e0473..d4f0452 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -21,6 +21,7 @@ subdirs-y += loaders
bootblock-y += prog_ops.c
bootblock-y += cbfs.c cbfs_core.c
bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
+bootblock-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
bootblock-$(CONFIG_GENERIC_UDELAY) += timer.c
@@ -36,6 +37,7 @@ verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
verstage-y += tlcl.c
verstage-$(CONFIG_GENERIC_UDELAY) += timer.c
+verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
romstage-y += prog_ops.c
romstage-y += memchr.c
@@ -51,6 +53,7 @@ romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c lzmadecode.c
romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c
ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c
romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c
+romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
ifeq ($(CONFIG_EARLY_CBMEM_INIT),y)
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9299
-gerrit
commit d42780256995720609a383a6dea4c9a2fbf1919f
Author: Patrick Georgi <pgeorgi(a)google.com>
Date: Fri Apr 3 17:06:48 2015 -0700
git: add rebase helper script
This is a script we have been using to rewrite commit messages when
upstreaming coreboot patches from the Chromium OS tree into coreboot
upstream.
Change-Id: I5442279c099dafe55cc97ccf09ee2bc2df4eca5f
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
util/gitconfig/rebase.sh | 47 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/util/gitconfig/rebase.sh b/util/gitconfig/rebase.sh
new file mode 100755
index 0000000..4bc32a4
--- /dev/null
+++ b/util/gitconfig/rebase.sh
@@ -0,0 +1,47 @@
+#!/bin/sh
+
+# rebase.sh - rebase helper script
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+# Adapt to your remote branch:
+BRANCH="cros/chromeos-2013.04"
+
+# When pulling in patches from another tree from a gerrit repository,
+# do the following at the end of a larger cherry-pick series:
+# git remote add ...
+# git checkout -b upstreaming
+# git cherry-pick ...
+# git rebase -i --exec util/gitconfig/rebase.sh master
+# Alternatively, you can run util/gitconfig/rebase.sh after every
+# individual cherry-pick.
+
+commit_message() {
+ git log -n 1 | grep "^ " | cut -c5-
+}
+
+CHID=$( commit_message | grep -i "^Change-Id: I" )
+CID=$( git log -n1 --grep "^$CHID$" --pretty=%H $BRANCH )
+GUID="$(git config user.name) <$(git config user.email)>"
+
+# TBD: Don't add Original- to empty lines, and possibly make script more
+# solid for commits with an unexpected order of meta data lines.
+
+commit_message | tac | awk '/^$/ {
+ if (end==0)
+ print "Original-Commit-Id: '"$CID"'\nSigned-off-by: '"$GUID"'";
+ end=1
+ }; {
+ if (end==0)
+ print "Original-" $0;
+ else
+ print $0;
+ }' | tac | git commit --amend -F -
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9509
-gerrit
commit c9591ab36b63929c7c8c342046c346ff9af5f308
Author: Kane Chen <kane.chen(a)intel.com>
Date: Thu Feb 12 16:08:42 2015 +0800
baytrail: correct NC pin to GPO pin according to BYT platform design guide
According to BYT platform design guide chap 14.2.2, the NC GPIOs
need to be configured to GPO.
BRANCH=none
BUG=none
TEST=Test on rambi, boot to OS, and make sure NC pins config to GPO
Change-Id: Ida5ea89ee66e39b4fddea242dc918b314756d94f
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 998493566f5cf7abd9375583e12fe631b226e591
Original-Change-Id: Ieaf346d1c7bf3ecb47a71a6ee4afaa805235cc37
Original-Signed-off-by: Kane Chen <kane.chen(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/249060
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/baytrail/include/soc/gpio.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h
index 413ade2..f312cdc 100644
--- a/src/soc/intel/baytrail/include/soc/gpio.h
+++ b/src/soc/intel/baytrail/include/soc/gpio.h
@@ -322,7 +322,7 @@
#define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU
#define GPIO_INPUT_PU GPIO_INPUT_PU_20K
#define GPIO_INPUT_PD GPIO_INPUT_PD_20K
-#define GPIO_NC GPIO_INPUT_PU_20K
+#define GPIO_NC GPIO_OUT_HIGH
#define GPIO_DEFAULT GPIO_FUNC0
/* 16 DirectIRQs per supported bank */
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9508
-gerrit
commit 11058151626d99a8cf667bbef96a0f49a4197f2b
Author: Shawn Nematbakhsh <shawnn(a)chromium.org>
Date: Mon Feb 23 15:14:54 2015 -0800
samus: Log EC panics to eventlog
Log the new EC panic host event.
BUG=chrome-os-partner:36985
TEST=Manual on Samus. Trigger EC panic, verify that "Panic Reset in
previous boot" is seen in /var/log/eventlog.
BRANCH=Samus
Change-Id: If59c522bd06f308a7ee6c5ff69ea427fcea361c9
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: dae4eb50b3607c5141a77fce6709107283f5dc36
Original-Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Original-Change-Id: I89b358a81a962fd463101d84b6bcf3b0a12830c7
Original-Reviewed-on: https://chromium-review.googlesource.com/252391
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-by: Alec Berg <alecaberg(a)chromium.org>
---
src/ec/google/chromeec/ec_commands.h | 3 +++
src/mainboard/google/samus/ec.h | 3 ++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h
index bd94281..725a652 100644
--- a/src/ec/google/chromeec/ec_commands.h
+++ b/src/ec/google/chromeec/ec_commands.h
@@ -278,6 +278,9 @@ enum host_event_code {
/* Battery Status flags have changed */
EC_HOST_EVENT_BATTERY_STATUS = 23,
+ /* EC encountered a panic, triggering an reset */
+ EC_HOST_EVENT_PANIC = 24,
+
/*
* The high bit of the event mask is not used as a host event code. If
* it reads back as set, then the entire event mask should be
diff --git a/src/mainboard/google/samus/ec.h b/src/mainboard/google/samus/ec.h
index 1ba1677..9b932ac 100644
--- a/src/mainboard/google/samus/ec.h
+++ b/src/mainboard/google/samus/ec.h
@@ -57,7 +57,8 @@
/* Log EC wake events plus EC shutdown events */
#define MAINBOARD_EC_LOG_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
#ifndef __ACPI__
extern void mainboard_ec_init(void);
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9471
-gerrit
commit 6fcc5539765cd03cc559e0e9eaa7667c43db4ea7
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Oct 30 15:23:52 2014 -0700
samus: Declare TPM in devicetree.cb and include ACPI device
This adds the TPM device to the devicetree and configures an
active high edge triggered interrupt at IRQ10 and adds the ACPI
Device for the TPM into the DSDT.
It also cleans up the EC PNP ID to use the EISAID for an EC since
there are now two PNP devices declared, and removes the unused
ENABLE_TPM define at the top of the DSDT.
BUG=chrome-os-partner:33385
BRANCH=samus
TEST=build and boot on samus, ensure TPM is functional at IRQ10
CQ-DEPEND=CL:226661
Change-Id: I4b9b016014d136fbf9a37003003632821ae93a53
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 0420e27b05d0f1568efa9beb849e0e8ff5995c86
Original-Change-Id: I2660cb30ac535da0b255603a619b9c09681ca947
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/226663
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/samus/acpi/mainboard.asl | 8 ++++++++
src/mainboard/google/samus/acpi_tables.c | 3 ---
src/mainboard/google/samus/devicetree.cb | 13 ++++++++-----
src/mainboard/google/samus/dsdt.asl | 2 --
4 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl
index 2b6cea0..4ade8e2 100644
--- a/src/mainboard/google/samus/acpi/mainboard.asl
+++ b/src/mainboard/google/samus/acpi/mainboard.asl
@@ -58,6 +58,14 @@ Scope (\_SB)
}
/*
+ * LPC Trusted Platform Module
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+ #include <drivers/pc80/tpm/acpi/tpm.asl>
+}
+
+/*
* WLAN connected to Root Port 3, becomes Root Port 1 after coalesce
*/
Scope (\_SB.PCI0.RP01)
diff --git a/src/mainboard/google/samus/acpi_tables.c b/src/mainboard/google/samus/acpi_tables.c
index a605828..a8b5b36 100644
--- a/src/mainboard/google/samus/acpi_tables.c
+++ b/src/mainboard/google/samus/acpi_tables.c
@@ -43,9 +43,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
/* Disable USB ports in S5 */
gnvs->s5u0 = 0;
- /* TPM Present */
- gnvs->tpmp = 1;
-
gnvs->tmps = TEMPERATURE_SENSOR_ID;
gnvs->tcrt = CRITICAL_TEMPERATURE;
gnvs->tpsv = PASSIVE_TEMPERATURE;
diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb
index 93ae51b..26b7b41 100644
--- a/src/mainboard/google/samus/devicetree.cb
+++ b/src/mainboard/google/samus/devicetree.cb
@@ -90,13 +90,16 @@ chip soc/intel/broadwell
device pci 1d.0 off end # USB2 EHCI
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
+ chip drivers/pc80/tpm
+ # Rising edge interrupt
+ register "irq_polarity" = "2"
+ device pnp 0c31.0 on
+ irq 0x70 = 10
end
end
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
end # LPC bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 off end # SMBus
diff --git a/src/mainboard/google/samus/dsdt.asl b/src/mainboard/google/samus/dsdt.asl
index cfd2037..722e0c9 100644
--- a/src/mainboard/google/samus/dsdt.asl
+++ b/src/mainboard/google/samus/dsdt.asl
@@ -18,8 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define ENABLE_TPM
-
DefinitionBlock(
"dsdt.aml",
"DSDT",