Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9505
-gerrit
commit 31423bfb04e82bee648b6f1349f5bde87bf221b0
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Mon Feb 9 21:16:14 2015 -0800
Intel SOC Common: Reset
Move reset support into the Intel common branch. Prevent breaking of
existing platforms by using a Kconfig value to select use of the common
reset code.
BRANCH=none
BUG=None
TEST=Build and run on Glados
Change-Id: I5ba86ef585dde3ef4ecdcc198ab615b5c056d985
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 85d8a6d9628a66cc8d73176d460cd6c5bf6bd6b2
Original-Change-Id: I5048ccf3eb593d59301ad8e808c4e281b9a0aa98
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/248301
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy(a)intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/common/Kconfig | 4 +++
src/soc/intel/common/Makefile.inc | 2 ++
src/soc/intel/common/reset.c | 54 +++++++++++++++++++++++++++++++++++++++
3 files changed, 60 insertions(+)
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 8b02a4a..70f3e01 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -17,3 +17,7 @@ config MRC_SETTINGS_CACHE_SIZE
endif # CACHE_MRC_SETTINGS
endif # HAVE_MRC
+
+config COMMON_RESET
+ bool
+ default n
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index 0c39d80..1861ec3 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -2,3 +2,5 @@ ramstage-y += hda_verb.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
+ramstage-$(CONFIG_COMMON_RESET) += reset.c
+romstage-$(CONFIG_COMMON_RESET) += reset.c
diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c
new file mode 100644
index 0000000..2046c3b
--- /dev/null
+++ b/src/soc/intel/common/reset.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <reset.h>
+
+/* Reset control port */
+#define RST_CNT 0xcf9
+#define FULL_RST (1 << 3)
+#define RST_CPU (1 << 2)
+#define SYS_RST (1 << 1)
+
+void hard_reset(void)
+{
+ /* S0->S5->S0 trip. */
+ outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
+ while (1)
+ hlt();
+}
+
+void soft_reset(void)
+{
+ /* PMC_PLTRST# asserted. */
+ outb(RST_CPU | SYS_RST, RST_CNT);
+ while (1)
+ hlt();
+}
+
+void cpu_reset(void)
+{
+ /* Sends INIT# to CPU */
+ outb(RST_CPU, RST_CNT);
+ while (1)
+ hlt();
+}
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9504
-gerrit
commit a8742570748b31dbc381c09867ade729bcfc27cd
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Mon Feb 9 21:09:49 2015 -0800
x86: Support reset routines in bootblock
Expand the boot block include file to allow for a file containing reset
routines to be added. Prevent breaking existing platforms by using a
Kconfig value to specify the path to this file, and have the code
include this file only if the Kconfig value is set.
BRANCH=none
BUG=None
TEST=Build and run on Glados
Change-Id: I604f701057d7018f2ed9c3ba49a643c4bca13f00
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: c109481d9503916e19ed300c1a3f085e0d2b5c51
Original-Change-Id: I3214399f8156b5ea2ef709ce77e3915cea1523a3
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/248300
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy(a)intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy(a)intel.com>
---
src/arch/x86/Kconfig | 3 +++
src/arch/x86/include/bootblock_common.h | 4 ++++
2 files changed, 7 insertions(+)
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index f7da89a..29f0514 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -84,6 +84,9 @@ config BOOTBLOCK_MAINBOARD_INIT
config BOOTBLOCK_NORTHBRIDGE_INIT
string
+config BOOTBLOCK_RESETS
+ string
+
config HAVE_CMOS_DEFAULT
def_bool n
diff --git a/src/arch/x86/include/bootblock_common.h b/src/arch/x86/include/bootblock_common.h
index b4100b7..939ba08 100644
--- a/src/arch/x86/include/bootblock_common.h
+++ b/src/arch/x86/include/bootblock_common.h
@@ -2,6 +2,10 @@
#include <cpu/x86/lapic/boot_cpu.c>
#include <pc80/mc146818rtc.h>
+#ifdef CONFIG_BOOTBLOCK_RESETS
+#include CONFIG_BOOTBLOCK_RESETS
+#endif
+
#ifdef CONFIG_BOOTBLOCK_CPU_INIT
#include CONFIG_BOOTBLOCK_CPU_INIT
#endif
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9507
-gerrit
commit a28aa6933e1eade6d6595e0f4723b4f5add1b847
Author: Julius Werner <jwerner(a)chromium.org>
Date: Fri Feb 20 13:36:11 2015 -0800
cros_ec: Retry failed VBNV transactions
This patch adds a few retries to NVRAM read/write transactions with the
EC. Failing to read the NVRAM is not fatal to the boot, but it's still
pretty bad... especially since a single initial read failure will cause
vboot to blindly reinitialize the whole NVRAM with zeroes, destroying
important configuration bits like dev_boot_usb. The current EC
transaction timeout is one second, so the three retries added here can
potentially increase boot time by three seconds per transaction... but
this shouldn't happen in any normal case anyway, and if there are errors
a little extra wait is probably preferrable to nuking your NVRAM.
(Also, added a missing newline to an error message in the EC code.)
BRANCH=veyron
BUG=chrome-os-partner:36924
TEST=Booted a Jerry with the power button bug with a 2 second press,
noticed that the first two transactions failed but the third one
succeeded.
Change-Id: I5d1cf29ac1c555ea2336ebb0b0e0a3f7cbb9c3fd
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 894a8a0b4a9805e92544b5e3dfa90baf6d36649a
Original-Change-Id: I6267cdda2be2bad34541b687404c2434d3be345b
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/251694
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/ec/google/chromeec/crosec_proto.c | 2 +-
src/ec/google/chromeec/ec.c | 11 +++++++++--
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/src/ec/google/chromeec/crosec_proto.c b/src/ec/google/chromeec/crosec_proto.c
index 55a707d..1183e82 100644
--- a/src/ec/google/chromeec/crosec_proto.c
+++ b/src/ec/google/chromeec/crosec_proto.c
@@ -235,7 +235,7 @@ static int send_command_proto3(struct chromeec_command *cec_command,
rv = crosec_io(out_bytes, in_bytes, context);
if (rv != 0) {
- printk(BIOS_ERR, "%s: failed to complete I/O: Err = %#x.",
+ printk(BIOS_ERR, "%s: failed to complete I/O: Err = %#x.\n",
__func__, rv >= 0 ? rv : -rv);
return -EC_RES_ERROR;
}
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 83c22d3..bda88e4 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -232,11 +232,12 @@ int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len)
struct chromeec_command cec_cmd;
struct ec_params_vbnvcontext cmd_vbnvcontext;
struct ec_response_vbnvcontext rsp_vbnvcontext;
+ int retries = 3;
if (len != EC_VBNV_BLOCK_SIZE)
return -1;
-
+ retry:
cec_cmd.cmd_code = EC_CMD_VBNV_CONTEXT;
cec_cmd.cmd_version = EC_VER_VBNV_CONTEXT;
cec_cmd.cmd_data_in = &cmd_vbnvcontext;
@@ -251,7 +252,13 @@ int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len)
if (!is_read)
memcpy(&cmd_vbnvcontext.block, data, EC_VBNV_BLOCK_SIZE);
- google_chromeec_command(&cec_cmd);
+ if (google_chromeec_command(&cec_cmd)) {
+ printk(BIOS_ERR, "ERROR: failed to %s vbnv_ec context: %d\n",
+ is_read ? "read" : "write", (int)cec_cmd.cmd_code);
+ mdelay(10); /* just in case */
+ if (--retries)
+ goto retry;
+ }
if (is_read)
memcpy(data, &rsp_vbnvcontext.block, EC_VBNV_BLOCK_SIZE);
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9476
-gerrit
commit fb44c2f0d958708b6e494e0fa72e0c1e945cca05
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Sun Nov 23 17:07:50 2014 -0800
tpm: Remove error message for unknown resource type
This is being triggered because the base address is added, but
there is nothing that needs done with it in set_resources step
and the ERROR message is tripping suspend resume test scripts.
BUG=chrome-os-partner:33385
BRANCH=samus,auron
TEST=boot on samus and check for ERROR strings,
successfully run suspend_stress_test without failures
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/231603
(cherry picked from commit bb789492965d92e309a913dc7b9f09f7036c5480)
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Change-Id: I565c8af954f1c5a406d2c65f01c274e9259e43ec
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 9062734d884f814dc880589ee615b4d7e1fdc61a
Original-Change-Id: I2b5f44795f1ee445d509b29bd56f498aea7b7fe3
Original-Reviewed-on: https://chromium-review.googlesource.com/231604
Original-Commit-Queue: Duncan Laurie <dlaurie(a)chromium.org>
Original-Tested-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/drivers/pc80/tpm/tpm.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/drivers/pc80/tpm/tpm.c b/src/drivers/pc80/tpm/tpm.c
index f1c5d97..68758aa 100644
--- a/src/drivers/pc80/tpm/tpm.c
+++ b/src/drivers/pc80/tpm/tpm.c
@@ -749,9 +749,6 @@ static void lpc_tpm_set_resources(struct device *dev)
tis_setup_interrupt((int)res->base,
config->irq_polarity);
} else {
- printk(BIOS_ERR,
- "ERROR: %s %02lx unknown resource type\n",
- dev_path(dev), res->index);
continue;
}