Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9474
-gerrit
commit ede858bec29c14f8c9b362b5d5eac18d05ed4b68
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Nov 10 13:00:27 2014 -0800
broadwell: Only do pre-graphics delay when running option rom
This changes the broadwell graphics init path to only do the delay
before initializing graphics when running chromeos if we are also
going to execute the option rom.
BUG=chrome-os-partner:33671
BRANCH=samus
TEST=build and boot on samus
Change-Id: Idb7d39b22f7f6dc3be6dfbd2fa3cc2e33d78a397
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: f7ed93504a74760f16acb8fb3c6c57ac514b7260
Original-Change-Id: I350f85738efe3d17152de4f025adbfd52ae15b95
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228882
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/broadwell/igd.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index 41a6961..4257ff3 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -33,6 +33,7 @@
#include <soc/ramstage.h>
#include <soc/systemagent.h>
#include <soc/intel/broadwell/chip.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#define GT_RETRY 1000
#define GT_CDCLK_337 0
@@ -487,7 +488,13 @@ static void igd_init(struct device *dev)
return;
/* Wait for any configured pre-graphics delay */
+#if IS_ENABLED(CONFIG_CHROMEOS)
+ if (developer_mode_enabled() || recovery_mode_enabled() ||
+ vboot_wants_oprom())
+ mdelay(CONFIG_PRE_GRAPHICS_DELAY);
+#else
mdelay(CONFIG_PRE_GRAPHICS_DELAY);
+#endif
/* Early init steps */
if (is_broadwell) {
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9473
-gerrit
commit d6bc1e402fef0c6353082b83d32a7fc669aebe77
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Nov 11 08:31:26 2014 -0800
samus: Move board version to a separate file
This combines the board version reading and parsing to
a separate file that is compiled in both romstage (for
early serial output) and ramstage (for smbios tables).
It also adds a new board version that is wrapped back
to number zero as we are running out of available IDs.
BUG=chrome-os-partner:32895
BRANCH=samus
TEST=build and boot on samus EVT1 and EVT2 and check
for proper board versions reported in console and smbios.
Change-Id: I8c8f17708ced7167277a98529ff4597589f53095
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 3ab8bba1021a8dd41dd2210ba73efd2231eb596c
Original-Change-Id: I2aa03e7486a9581f94dc4e12f6f29eb0c5b3bdbb
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229041
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/samus/Makefile.inc | 3 +++
src/mainboard/google/samus/board_version.c | 37 ++++++++++++++++++++++++++++++
src/mainboard/google/samus/board_version.h | 30 ++++++++++++++++++++++++
src/mainboard/google/samus/ec.h | 4 ----
src/mainboard/google/samus/mainboard.c | 12 ++--------
src/mainboard/google/samus/romstage.c | 5 ++--
6 files changed, 75 insertions(+), 16 deletions(-)
diff --git a/src/mainboard/google/samus/Makefile.inc b/src/mainboard/google/samus/Makefile.inc
index 502204e..e8013a8 100644
--- a/src/mainboard/google/samus/Makefile.inc
+++ b/src/mainboard/google/samus/Makefile.inc
@@ -28,3 +28,6 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-y += pei_data.c
ramstage-y += pei_data.c
+
+romstage-y += board_version.c
+ramstage-y += board_version.c
diff --git a/src/mainboard/google/samus/board_version.c b/src/mainboard/google/samus/board_version.c
new file mode 100644
index 0000000..4575dd5
--- /dev/null
+++ b/src/mainboard/google/samus/board_version.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <ec/google/chromeec/ec.h>
+#include "board_version.h"
+
+const char *samus_board_version(void)
+{
+ switch (google_chromeec_get_board_version()) {
+ case SAMUS_EC_BOARD_VERSION_EVT1:
+ return "EVT1";
+ case SAMUS_EC_BOARD_VERSION_EVT2:
+ return "EVT2";
+ case SAMUS_EC_BOARD_VERSION_EVT3:
+ return "EVT3";
+ case SAMUS_EC_BOARD_VERSION_EVT4:
+ return "EVT4";
+ default:
+ return "Unknown";
+ }
+}
diff --git a/src/mainboard/google/samus/board_version.h b/src/mainboard/google/samus/board_version.h
new file mode 100644
index 0000000..8b3fea3
--- /dev/null
+++ b/src/mainboard/google/samus/board_version.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SAMUS_BOARD_VERSION_H
+#define SAMUS_BOARD_VERSION_H
+
+#define SAMUS_EC_BOARD_VERSION_EVT1 3
+#define SAMUS_EC_BOARD_VERSION_EVT2 4
+#define SAMUS_EC_BOARD_VERSION_EVT3 5
+#define SAMUS_EC_BOARD_VERSION_EVT4 0
+
+const char *samus_board_version(void);
+
+#endif
diff --git a/src/mainboard/google/samus/ec.h b/src/mainboard/google/samus/ec.h
index 295d040..1ba1677 100644
--- a/src/mainboard/google/samus/ec.h
+++ b/src/mainboard/google/samus/ec.h
@@ -22,10 +22,6 @@
#include <ec/google/chromeec/ec_commands.h>
-#define SAMUS_EC_BOARD_VERSION_EVT 3
-#define SAMUS_EC_BOARD_VERSION_EVT2 4
-#define SAMUS_EC_BOARD_VERSION_EVT3 5
-
#define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */
#define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */
diff --git a/src/mainboard/google/samus/mainboard.c b/src/mainboard/google/samus/mainboard.c
index 85e9dfb..53f31a5 100644
--- a/src/mainboard/google/samus/mainboard.c
+++ b/src/mainboard/google/samus/mainboard.c
@@ -32,7 +32,7 @@
#include <arch/io.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
-#include <ec/google/chromeec/ec.h>
+#include "board_version.h"
#include "ec.h"
void mainboard_suspend_resume(void)
@@ -41,15 +41,7 @@ void mainboard_suspend_resume(void)
const char *smbios_mainboard_version(void)
{
- switch (google_chromeec_get_board_version()) {
- case SAMUS_EC_BOARD_VERSION_EVT:
- return "EVT";
- case SAMUS_EC_BOARD_VERSION_EVT2:
- return "EVT2";
- case SAMUS_EC_BOARD_VERSION_EVT3:
- return "EVT3";
- }
- return "Unknown";
+ return samus_board_version();
}
static void mainboard_init(device_t dev)
diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c
index 55658f5..7c9aa6e 100644
--- a/src/mainboard/google/samus/romstage.c
+++ b/src/mainboard/google/samus/romstage.c
@@ -30,6 +30,8 @@
#include <soc/romstage.h>
#include <mainboard/google/samus/spd/spd.h>
#include <mainboard/google/samus/gpio.h>
+#include <ec/google/chromeec/ec.h>
+#include "board_version.h"
void mainboard_romstage_entry(struct romstage_params *rp)
{
@@ -40,8 +42,7 @@ void mainboard_romstage_entry(struct romstage_params *rp)
if (rp->power_state->prev_sleep_state != SLEEP_STATE_S3)
google_chromeec_kbbacklight(100);
- printk(BIOS_INFO, "MLB: board version %d\n",
- google_chromeec_get_board_version());
+ printk(BIOS_INFO, "MLB: board version %s\n", samus_board_version());
/* Ensure the EC and PD are in the right mode for recovery */
google_chromeec_early_pd_init();
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9481
-gerrit
commit 773724444eb4a036a368310b939ce27502b254e4
Author: Julius Werner <jwerner(a)chromium.org>
Date: Fri Dec 19 14:38:51 2014 -0800
TPM: Reduce buffer size to fix stack overflow
The TPM driver by default allocates a 4K transfer buffer on the stack,
which leads to lots of fun on boards with 2K or 3K stack sizes. On
RK3288 this ends up writing over random memory sections which dependent
on the memlayout of the day might contain timestamp data (no big deal)
or page tables (-> bad time).
This patch fixes the problem by reducing the buffer size to slightly
above 1K, which still seems to work as far as I can tell. There was
already some really odd code that #undef'ed this value and redefined it
with the lower number in one .c file (unfortunately not the one with the
buffer declaration), with no explanation whatsoever... I'm removing that
and just assume the smaller value will be fine for everything.
BRANCH=veyron
BUG=None
TEST=Booted Pinky and Falco.
Change-Id: I440a5662b41cbd8b7becab3113262e1140b7f763
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 3d3288041b6629b7623b9d58816e782e72836b81
Original-Change-Id: Idf80f44cbfb9617c56b64a5c88ebedf7fcb4ec71
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/236976
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
---
src/drivers/i2c/tpm/tpm.c | 6 ------
src/drivers/i2c/tpm/tpm.h | 4 ++--
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c
index bc36e35..3af82db 100644
--- a/src/drivers/i2c/tpm/tpm.c
+++ b/src/drivers/i2c/tpm/tpm.c
@@ -45,12 +45,6 @@
#include <device/i2c.h>
#include "tpm.h"
-/* max. buffer size supported by our TPM */
-#ifdef TPM_BUFSIZE
-#undef TPM_BUFSIZE
-#endif
-#define TPM_BUFSIZE 1260
-
/* Address of the TPM on the I2C bus */
#define TPM_I2C_ADDR 0x20
diff --git a/src/drivers/i2c/tpm/tpm.h b/src/drivers/i2c/tpm/tpm.h
index 6d195a1..de88a66 100644
--- a/src/drivers/i2c/tpm/tpm.h
+++ b/src/drivers/i2c/tpm/tpm.h
@@ -42,8 +42,8 @@ enum tpm_timeout {
TPM_TIMEOUT = 1, /* msecs */
};
-/* Size of external transmit buffer (used in tpm_transmit)*/
-#define TPM_BUFSIZE 4096
+/* Size of external transmit buffer (used for stack buffer in tpm_sendrecv) */
+#define TPM_BUFSIZE 1260
/* Index of fields in TPM command buffer */
#define TPM_CMD_SIZE_BYTE 2
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9480
-gerrit
commit 231d2ca6c611dc9df030e4448bde8155ecb56b27
Author: Kevin L Lee <kevin.l.lee(a)intel.com>
Date: Fri Dec 12 14:02:43 2014 +0800
baytrail:fix the coding error on PCIe L1 exit lantency
The original code use L1EXIT_MASK to shift the bit for
PCIe L1 exist lantency, the code should be use
L1EXIT_SHIFT for bit shift.
BUG=chrome-os-partner:34037
BRANCH=None
TEST=build and boot on candy, verify B0:D28:F0 + 4Ch [17:15]
set to 010b. Correspond WIFI device performance got improvement.
Signed-off-by: Kevin L Lee <kevin.l.lee(a)intel.com>
Change-Id: I3ac5b6319b726aa16cdb9678face89022d979517
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 381827e3d92c9e786cd8ebe412586968662fb4be
Original-Change-Id: I8171f80720830cfa76f26778ae31c7590a723b92
Original-Reviewed-on: https://chromium-review.googlesource.com/234673
Original-Reviewed-by: Kenji Chen <kenji.chen(a)intel.com>
Original-Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Original-Tested-by: Kenji Chen <kenji.chen(a)intel.com>
Original-Commit-Queue: Kenji Chen <kenji.chen(a)intel.com>
---
src/soc/intel/baytrail/pcie.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c
index 1870158..e44ebc6 100644
--- a/src/soc/intel/baytrail/pcie.c
+++ b/src/soc/intel/baytrail/pcie.c
@@ -95,7 +95,7 @@ static void byt_pcie_init(device_t dev)
/* Exit latency configuration based on
* PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/
REG_PCI_RMW32(LCAP, ~L1EXIT_MASK,
- 2 << (L1EXIT_MASK + pll_en_off)),
+ 2 << (L1EXIT_SHIFT + pll_en_off)),
REG_SCRIPT_NEXT(init_static_after_exit_latency),
/* Disable hot plug, set power to 10W, set slot number. */
REG_PCI_RMW32(SLCAP, ~(HPC | HPS),