the following patch was just integrated into master:
commit 2d8688711f40b48a9b5e77387eb64a4fb8257aa4
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Wed Apr 8 11:36:45 2015 +0200
abuild: also consider verstage architecture
We have another stage which we need to test for. Not a problem
right now, because it always matches either bootblock or romstage,
but future proof the test.
Change-Id: Id0a16d9bc1270516f2c00f9f8fd049420c9ba354
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9380
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9380 for details.
-gerrit
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9467
-gerrit
commit defcb0b150df918327632d45595bfeb8742d1cd8
Author: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com>
Date: Wed Oct 29 17:26:05 2014 -0700
broadwell: Increase I2C SDA hold timing to 300ns
I2C bus SDA hold time can be marginal with 60ns value, especially
when there is level shifter on the bus. So program it to 300ns
based on Fast-mode specification, which is between 0 to 900ns.
Apply the same timing for Standard-mode as well.
Refer to original bug on BayTrail chrome-os-partner:28092, this
is to carry forward the fix to Broadwell.
BRANCH=chromeos-2013.04
BUG=chrome-os-partner:33378
TEST=suspend resume test, watch for I2C errors
Change-Id: I93200b141602163903f5c9f52b94013bcf3382a5
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 72b82a1d5d836594e7d0f95972cc0dc91ae7ff8c
Original-Change-Id: I995d6868a44f2578a6d0b18dd5e8548f3c3cd494
Original-Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/226386
Original-Reviewed-by: Wenkai Du <wenkai.du(a)intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/broadwell/acpi/serialio.asl | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/acpi/serialio.asl
index 6b42d54..7ffc671 100644
--- a/src/soc/intel/broadwell/acpi/serialio.asl
+++ b/src/soc/intel/broadwell/acpi/serialio.asl
@@ -205,8 +205,8 @@ Device (I2C0)
Name (_UID, 1)
Name (_ADR, 0x00150001)
- Name (SSCN, Package () { 432, 507, 9 })
- Name (FMCN, Package () { 72, 160, 9 })
+ Name (SSCN, Package () { 432, 507, 30 })
+ Name (FMCN, Package () { 72, 160, 30 })
// BAR0 is assigned during PCI enumeration and saved into NVS
Name (RBUF, ResourceTemplate ()
@@ -276,8 +276,8 @@ Device (I2C1)
Name (_UID, 1)
Name (_ADR, 0x00150002)
- Name (SSCN, Package () { 432, 507, 9 })
- Name (FMCN, Package () { 72, 160, 9 })
+ Name (SSCN, Package () { 432, 507, 30 })
+ Name (FMCN, Package () { 72, 160, 30 })
// BAR0 is assigned during PCI enumeration and saved into NVS
Name (RBUF, ResourceTemplate ()
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9509
-gerrit
commit 4e72d4eb03de9fb4289e5be2352a1843d75a2bcc
Author: Kane Chen <kane.chen(a)intel.com>
Date: Thu Feb 12 16:08:42 2015 +0800
baytrail: correct NC pin to GPO pin according to BYT platform design guide
According to BYT platform design guide chap 14.2.2, the NC GPIOs
need to be configured to GPO.
BRANCH=none
BUG=none
TEST=Test on rambi, boot to OS, and make sure NC pins config to GPO
Change-Id: Ida5ea89ee66e39b4fddea242dc918b314756d94f
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 998493566f5cf7abd9375583e12fe631b226e591
Original-Change-Id: Ieaf346d1c7bf3ecb47a71a6ee4afaa805235cc37
Original-Signed-off-by: Kane Chen <kane.chen(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/249060
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/baytrail/include/soc/gpio.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h
index 413ade2..f312cdc 100644
--- a/src/soc/intel/baytrail/include/soc/gpio.h
+++ b/src/soc/intel/baytrail/include/soc/gpio.h
@@ -322,7 +322,7 @@
#define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU
#define GPIO_INPUT_PU GPIO_INPUT_PU_20K
#define GPIO_INPUT_PD GPIO_INPUT_PD_20K
-#define GPIO_NC GPIO_INPUT_PU_20K
+#define GPIO_NC GPIO_OUT_HIGH
#define GPIO_DEFAULT GPIO_FUNC0
/* 16 DirectIRQs per supported bank */
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9508
-gerrit
commit 8bce88f01405b201203ae357e7718fda6ad5ada9
Author: Shawn Nematbakhsh <shawnn(a)chromium.org>
Date: Mon Feb 23 15:14:54 2015 -0800
samus: Log EC panics to eventlog
Log the new EC panic host event.
BUG=chrome-os-partner:36985
TEST=Manual on Samus. Trigger EC panic, verify that "Panic Reset in
previous boot" is seen in /var/log/eventlog.
BRANCH=Samus
Change-Id: If59c522bd06f308a7ee6c5ff69ea427fcea361c9
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: dae4eb50b3607c5141a77fce6709107283f5dc36
Original-Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Original-Change-Id: I89b358a81a962fd463101d84b6bcf3b0a12830c7
Original-Reviewed-on: https://chromium-review.googlesource.com/252391
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-by: Alec Berg <alecaberg(a)chromium.org>
---
src/ec/google/chromeec/ec_commands.h | 3 +++
src/mainboard/google/samus/ec.h | 3 ++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h
index bd94281..725a652 100644
--- a/src/ec/google/chromeec/ec_commands.h
+++ b/src/ec/google/chromeec/ec_commands.h
@@ -278,6 +278,9 @@ enum host_event_code {
/* Battery Status flags have changed */
EC_HOST_EVENT_BATTERY_STATUS = 23,
+ /* EC encountered a panic, triggering an reset */
+ EC_HOST_EVENT_PANIC = 24,
+
/*
* The high bit of the event mask is not used as a host event code. If
* it reads back as set, then the entire event mask should be
diff --git a/src/mainboard/google/samus/ec.h b/src/mainboard/google/samus/ec.h
index 1ba1677..9b932ac 100644
--- a/src/mainboard/google/samus/ec.h
+++ b/src/mainboard/google/samus/ec.h
@@ -57,7 +57,8 @@
/* Log EC wake events plus EC shutdown events */
#define MAINBOARD_EC_LOG_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
#ifndef __ACPI__
extern void mainboard_ec_init(void);
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9464
-gerrit
commit ce71ab338ccb1bdf534dc6aed9dad864b6ded93d
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Oct 9 16:13:24 2014 -0700
broadwell: Work around VBIOS framebuffer issue
The first 64 bytes of the framebuffer contain garbage after running
the option rom and after calling the VBE mode set with the flag to
clear the framebuffer.
Work around this issue by clearing the first 64 bytes in the framebuffer
in the broadwell graphics setup code after it executes the VBIOS.
BUG=chrome-os-partner:32771
BRANCH=samus,auron
TEST=build and boot on samus in dev mode, check for graphical corruption
Change-Id: I0381e32a5ea17e13c4ed598835999c12136418cf
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: f29c1b0b7c100cf290f82de671042823032f71c9
Original-Change-Id: I072bc913f7daea16e4861a7549e1b4ec85cde4cd
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/222676
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/broadwell/igd.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index d8b51a3..41a6961 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -523,6 +523,15 @@ static void igd_init(struct device *dev)
reg_script_run_on_dev(dev, haswell_late_init_script);
}
+ if (gfx_get_init_done()) {
+ /*
+ * Work around VBIOS issue that is not clearing first 64
+ * bytes of the framebuffer during VBE mode set.
+ */
+ struct resource *fb = find_resource(dev, PCI_BASE_ADDRESS_2);
+ memset((void *)((u32)fb->base), 0, 64);
+ }
+
if (!gfx_get_init_done() && acpi_slp_type != 3) {
/*
* Enable DDI-A if the Option ROM did not execute:
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9471
-gerrit
commit b60493eec64b597dd1e01f29eccf618e0f4e5564
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Oct 30 15:23:52 2014 -0700
samus: Declare TPM in devicetree.cb and include ACPI device
This adds the TPM device to the devicetree and configures an
active high edge triggered interrupt at IRQ10 and adds the ACPI
Device for the TPM into the DSDT.
It also cleans up the EC PNP ID to use the EISAID for an EC since
there are now two PNP devices declared, and removes the unused
ENABLE_TPM define at the top of the DSDT.
BUG=chrome-os-partner:33385
BRANCH=samus
TEST=build and boot on samus, ensure TPM is functional at IRQ10
CQ-DEPEND=CL:226661
Change-Id: I4b9b016014d136fbf9a37003003632821ae93a53
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 0420e27b05d0f1568efa9beb849e0e8ff5995c86
Original-Change-Id: I2660cb30ac535da0b255603a619b9c09681ca947
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/226663
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/samus/acpi/mainboard.asl | 8 ++++++++
src/mainboard/google/samus/acpi_tables.c | 3 ---
src/mainboard/google/samus/devicetree.cb | 13 ++++++++-----
src/mainboard/google/samus/dsdt.asl | 2 --
4 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl
index 2b6cea0..4ade8e2 100644
--- a/src/mainboard/google/samus/acpi/mainboard.asl
+++ b/src/mainboard/google/samus/acpi/mainboard.asl
@@ -58,6 +58,14 @@ Scope (\_SB)
}
/*
+ * LPC Trusted Platform Module
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+ #include <drivers/pc80/tpm/acpi/tpm.asl>
+}
+
+/*
* WLAN connected to Root Port 3, becomes Root Port 1 after coalesce
*/
Scope (\_SB.PCI0.RP01)
diff --git a/src/mainboard/google/samus/acpi_tables.c b/src/mainboard/google/samus/acpi_tables.c
index a605828..a8b5b36 100644
--- a/src/mainboard/google/samus/acpi_tables.c
+++ b/src/mainboard/google/samus/acpi_tables.c
@@ -43,9 +43,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
/* Disable USB ports in S5 */
gnvs->s5u0 = 0;
- /* TPM Present */
- gnvs->tpmp = 1;
-
gnvs->tmps = TEMPERATURE_SENSOR_ID;
gnvs->tcrt = CRITICAL_TEMPERATURE;
gnvs->tpsv = PASSIVE_TEMPERATURE;
diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb
index 93ae51b..26b7b41 100644
--- a/src/mainboard/google/samus/devicetree.cb
+++ b/src/mainboard/google/samus/devicetree.cb
@@ -90,13 +90,16 @@ chip soc/intel/broadwell
device pci 1d.0 off end # USB2 EHCI
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
+ chip drivers/pc80/tpm
+ # Rising edge interrupt
+ register "irq_polarity" = "2"
+ device pnp 0c31.0 on
+ irq 0x70 = 10
end
end
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
end # LPC bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 off end # SMBus
diff --git a/src/mainboard/google/samus/dsdt.asl b/src/mainboard/google/samus/dsdt.asl
index cfd2037..722e0c9 100644
--- a/src/mainboard/google/samus/dsdt.asl
+++ b/src/mainboard/google/samus/dsdt.asl
@@ -18,8 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define ENABLE_TPM
-
DefinitionBlock(
"dsdt.aml",
"DSDT",
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9505
-gerrit
commit 0e460a2d0b21dc8f7446abdb3433b654a6fd965c
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Mon Feb 9 21:16:14 2015 -0800
Intel SOC Common: Reset
Move reset support into the Intel common branch. Prevent breaking of
existing platforms by using a Kconfig value to select use of the common
reset code.
BRANCH=none
BUG=None
TEST=Build and run on Glados
Change-Id: I5ba86ef585dde3ef4ecdcc198ab615b5c056d985
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 85d8a6d9628a66cc8d73176d460cd6c5bf6bd6b2
Original-Change-Id: I5048ccf3eb593d59301ad8e808c4e281b9a0aa98
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/248301
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy(a)intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/common/Kconfig | 4 +++
src/soc/intel/common/Makefile.inc | 2 ++
src/soc/intel/common/reset.c | 54 +++++++++++++++++++++++++++++++++++++++
3 files changed, 60 insertions(+)
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 8b02a4a..70f3e01 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -17,3 +17,7 @@ config MRC_SETTINGS_CACHE_SIZE
endif # CACHE_MRC_SETTINGS
endif # HAVE_MRC
+
+config COMMON_RESET
+ bool
+ default n
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index 0c39d80..1861ec3 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -2,3 +2,5 @@ ramstage-y += hda_verb.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
+ramstage-$(CONFIG_COMMON_RESET) += reset.c
+romstage-$(CONFIG_COMMON_RESET) += reset.c
diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c
new file mode 100644
index 0000000..2046c3b
--- /dev/null
+++ b/src/soc/intel/common/reset.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <reset.h>
+
+/* Reset control port */
+#define RST_CNT 0xcf9
+#define FULL_RST (1 << 3)
+#define RST_CPU (1 << 2)
+#define SYS_RST (1 << 1)
+
+void hard_reset(void)
+{
+ /* S0->S5->S0 trip. */
+ outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
+ while (1)
+ hlt();
+}
+
+void soft_reset(void)
+{
+ /* PMC_PLTRST# asserted. */
+ outb(RST_CPU | SYS_RST, RST_CNT);
+ while (1)
+ hlt();
+}
+
+void cpu_reset(void)
+{
+ /* Sends INIT# to CPU */
+ outb(RST_CPU, RST_CNT);
+ while (1)
+ hlt();
+}