Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9489
-gerrit
commit 7bbe70c94c46df55d60432fab42d27f486156b1e
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Jan 14 17:30:20 2015 -0800
broadwell: Skip steps when disabling PCIe port
When disabling PCIe ports skip steps if no card is detected.
This prevents the loop from timing out on each empty slot.
BUG=chrome-os-partner:31424
BRANCH=broadwell
TEST=build and boot on samus, check that this code is
no longer timing out when disabling PCIe ports
Change-Id: I84ee0e0e325784b3af06abe70420c07cf6e13ed2
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 4d759e2350dd00ceb7df196ac7008729dc1e4cef
Original-Change-Id: Idd88f0f1191a5465a0d8dcca07b5c3a5c5ca8855
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240851
Original-Reviewed-by: Wenkai Du <wenkai.du(a)intel.com>
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
---
src/soc/intel/broadwell/pcie.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index 4476fe4..e217149 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -321,12 +321,12 @@ static void root_port_commit_config(void)
do {
reg32 = pci_read_config32(dev, 0x328);
n++;
- if (((reg32 & 0xff000000) == 0x01000000) || (n > 500))
+ if (((reg32 & 0xff000000) == 0x01000000) || (n > 50))
break;
udelay(100);
} while (1);
- if (n > 500)
+ if (n > 50)
printk(BIOS_DEBUG, "%s: Timeout waiting for 328h\n",
dev_path(dev));
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9481
-gerrit
commit bfb732de7efb26219063cde5a4e36a2e5e9aafb2
Author: Julius Werner <jwerner(a)chromium.org>
Date: Fri Dec 19 14:38:51 2014 -0800
TPM: Reduce buffer size to fix stack overflow
The TPM driver by default allocates a 4K transfer buffer on the stack,
which leads to lots of fun on boards with 2K or 3K stack sizes. On
RK3288 this ends up writing over random memory sections which dependent
on the memlayout of the day might contain timestamp data (no big deal)
or page tables (-> bad time).
This patch fixes the problem by reducing the buffer size to slightly
above 1K, which still seems to work as far as I can tell. There was
already some really odd code that #undef'ed this value and redefined it
with the lower number in one .c file (unfortunately not the one with the
buffer declaration), with no explanation whatsoever... I'm removing that
and just assume the smaller value will be fine for everything.
BRANCH=veyron
BUG=None
TEST=Booted Pinky and Falco.
Change-Id: I440a5662b41cbd8b7becab3113262e1140b7f763
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 3d3288041b6629b7623b9d58816e782e72836b81
Original-Change-Id: Idf80f44cbfb9617c56b64a5c88ebedf7fcb4ec71
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/236976
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
---
src/drivers/i2c/tpm/tpm.c | 6 ------
src/drivers/i2c/tpm/tpm.h | 4 ++--
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c
index bc36e35..3af82db 100644
--- a/src/drivers/i2c/tpm/tpm.c
+++ b/src/drivers/i2c/tpm/tpm.c
@@ -45,12 +45,6 @@
#include <device/i2c.h>
#include "tpm.h"
-/* max. buffer size supported by our TPM */
-#ifdef TPM_BUFSIZE
-#undef TPM_BUFSIZE
-#endif
-#define TPM_BUFSIZE 1260
-
/* Address of the TPM on the I2C bus */
#define TPM_I2C_ADDR 0x20
diff --git a/src/drivers/i2c/tpm/tpm.h b/src/drivers/i2c/tpm/tpm.h
index 6d195a1..de88a66 100644
--- a/src/drivers/i2c/tpm/tpm.h
+++ b/src/drivers/i2c/tpm/tpm.h
@@ -42,8 +42,8 @@ enum tpm_timeout {
TPM_TIMEOUT = 1, /* msecs */
};
-/* Size of external transmit buffer (used in tpm_transmit)*/
-#define TPM_BUFSIZE 4096
+/* Size of external transmit buffer (used for stack buffer in tpm_sendrecv) */
+#define TPM_BUFSIZE 1260
/* Index of fields in TPM command buffer */
#define TPM_CMD_SIZE_BYTE 2
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9480
-gerrit
commit dc19877701ca8e575a32cee6e5f593a017a99ad2
Author: Kevin L Lee <kevin.l.lee(a)intel.com>
Date: Fri Dec 12 14:02:43 2014 +0800
baytrail:fix the coding error on PCIe L1 exit lantency
The original code use L1EXIT_MASK to shift the bit for
PCIe L1 exist lantency, the code should be use
L1EXIT_SHIFT for bit shift.
BUG=chrome-os-partner:34037
BRANCH=None
TEST=build and boot on candy, verify B0:D28:F0 + 4Ch [17:15]
set to 010b. Correspond WIFI device performance got improvement.
Signed-off-by: Kevin L Lee <kevin.l.lee(a)intel.com>
Change-Id: I3ac5b6319b726aa16cdb9678face89022d979517
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 381827e3d92c9e786cd8ebe412586968662fb4be
Original-Change-Id: I8171f80720830cfa76f26778ae31c7590a723b92
Original-Reviewed-on: https://chromium-review.googlesource.com/234673
Original-Reviewed-by: Kenji Chen <kenji.chen(a)intel.com>
Original-Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Original-Tested-by: Kenji Chen <kenji.chen(a)intel.com>
Original-Commit-Queue: Kenji Chen <kenji.chen(a)intel.com>
---
src/soc/intel/baytrail/pcie.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c
index 1870158..e44ebc6 100644
--- a/src/soc/intel/baytrail/pcie.c
+++ b/src/soc/intel/baytrail/pcie.c
@@ -95,7 +95,7 @@ static void byt_pcie_init(device_t dev)
/* Exit latency configuration based on
* PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/
REG_PCI_RMW32(LCAP, ~L1EXIT_MASK,
- 2 << (L1EXIT_MASK + pll_en_off)),
+ 2 << (L1EXIT_SHIFT + pll_en_off)),
REG_SCRIPT_NEXT(init_static_after_exit_latency),
/* Disable hot plug, set power to 10W, set slot number. */
REG_PCI_RMW32(SLCAP, ~(HPC | HPS),