Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9499
-gerrit
commit ca1840ea902f9b3e99303490a99802d42f4515c3
Author: Ben Zhang <benzh(a)chromium.org>
Date: Fri Nov 21 11:17:53 2014 -0800
samus: Set MICBIAS1 to 2.970V
The default micbias1 voltage is 1.476V (1.8V * 0.82) which does
not match what's specified on the schematic. This patch sets
the voltage to 2.970V (3.3V * 0.90) according to the schematic.
BUG=chrome-os-partner:32953
BRANCH=samus
TEST=Set MICBIAS to 2.970V on Samus and verified with a scope
Change-Id: I1ced834a5afe2de3fccf4bcff8ec9c8e5718f60a
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 176f9272801a3de5ed6fc05ade06042e2a2c0a5c
Original-Change-Id: Icdbc1b5f65fe28591d54544372bdc2dacb50e9c1
Original-Signed-off-by: Ben Zhang <benzh(a)chromium.org>
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241178
---
src/mainboard/google/samus/acpi/mainboard.asl | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl
index 54a46d5..287f595 100644
--- a/src/mainboard/google/samus/acpi/mainboard.asl
+++ b/src/mainboard/google/samus/acpi/mainboard.asl
@@ -177,6 +177,7 @@ Scope (\_SB.PCI0.I2C0)
Name (_UID, 1)
Name (WAKE, 45) /* DSP_INT (use as codec wake) */
+ Name (MB1, 1) /* MICBIAS1 = 2.970V */
Name (DCLK, 0) /* RT5677_DMIC_CLK1 */
Name (PCLK, 1) /* RT5677_PDM_CLK_DIV2 (~3MHz) */
Name (IN1, 1) /* IN1 differential */
@@ -193,6 +194,7 @@ Scope (\_SB.PCI0.I2C0)
Name (_DSD, Package () {
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
+ Package () { "realtek,micbias1", 1 },
Package () { "realtek,in1-differential", 1 },
Package () { "realtek,in2-differential", 0 },
Package () { "realtek,lout1-differential", 1 },
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9496
-gerrit
commit 8c772fd3821c8f259c79c76088cc33ce83465cbf
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Sun Jan 18 14:14:17 2015 -0800
samus: Adjust SATA Gen3 TX voltage amplitude
Reduce the SATA Gen3 TX voltage amplitude by 210mV based
on the provided test results to help with SATA validation.
BUG=chrome-os-partner:34121
BRANCH=samus
TEST=build and boot on samus and ensure SATA is still working,
firmware image will be provided for full validation.
Change-Id: I574d2f457b7b6831a339602a4165e959a0e2ee7d
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 9500ec152d8f9c90513811b1a92d1a8c155f514a
Original-Change-Id: I233fa1a9a7f2877a97ef6834304680f82b958e82
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241800
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
---
src/mainboard/google/samus/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb
index 0ca7405..3eaea40 100644
--- a/src/mainboard/google/samus/devicetree.cb
+++ b/src/mainboard/google/samus/devicetree.cb
@@ -43,6 +43,7 @@ chip soc/intel/broadwell
register "gpe0_en_4" = "0x00000000"
register "sata_port_map" = "0x1"
+ register "sata_port0_gen3_tx" = "0x72"
register "sio_acpi_mode" = "1"
# Set I2C0 to 1.8V
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9495
-gerrit
commit 83dccf2e9343283f7df9077534988a207a9275f8
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Sun Jan 18 14:06:42 2015 -0800
broadwell: Preserve VbNv around cmos_init
To ensure that boot flags (legacy, usb, signed-only) are
properly restored from CMOS and used in the first boot after
a battery removal or RTC reset then the VbNv region needs to
be preserved around the cmos_init call.
When using vboot firmware selection and VbNv is stored in CMOS
then that region of CMOS will have been re-initialized by the
time we call cmos_init and reset CMOS if the chipset flag was
set indicating a problem.
BUG=chrome-os-partner:35240
BRANCH=broadwell
TEST=manual testing on samus:
1) boot in dev mode, enable dev_boot_legacy and ensure it works
2) on EC console pulse PCH_RTCRST_L low for a second
3) ensure first boot after RTC reset will still boot legacy mode
4) remove battery for a time
5) ensure first boot after battery is re-inserted will still
boot legacy mode
Change-Id: Ica256bbdcba6d4616957ff38e63914dd15f645c6
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 881c7841c95dec392a66eef38a7112c1f385fdfa
Original-Change-Id: I4c33f183ba4b301d68ae31c41fc6663f3be857b0
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241529
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/broadwell/lpc.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 6ebc758..9a4c65c 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -49,6 +49,10 @@
#include <arch/acpigen.h>
#include <cpu/cpu.h>
+#if IS_ENABLED(CONFIG_CHROMEOS)
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
+
static void pch_enable_ioapic(struct device *dev)
{
u32 reg32;
@@ -174,6 +178,25 @@ static void pch_power_options(device_t dev)
enable_alt_smi(config->alt_gp_smi_en);
}
+#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)
+/*
+ * Preserve Vboot NV data when clearing CMOS as it will
+ * have been re-initialized already by Vboot firmware init.
+ */
+static void pch_cmos_init_preserve(int reset)
+{
+ uint8_t vbnv[CONFIG_VBNV_SIZE];
+
+ if (reset)
+ read_vbnv(vbnv);
+
+ cmos_init(reset);
+
+ if (reset)
+ save_vbnv(vbnv);
+}
+#endif
+
static void pch_rtc_init(struct device *dev)
{
u8 reg8;
@@ -187,7 +210,11 @@ static void pch_rtc_init(struct device *dev)
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
}
+#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)
+ pch_cmos_init_preserve(rtc_failed);
+#else
cmos_init(rtc_failed);
+#endif
}
static const struct reg_script pch_misc_init_script[] = {
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9494
-gerrit
commit 7164ccd56ddebf9acadcb5a0fd9f9875b792b03e
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Jan 15 15:49:07 2015 -0800
soc/intel/common: Add function to protect MRC cache
Add support for applying write protection to the MRC cache
region in SPI flash.
This is only enabled if there is write protect GPIO that is
set, and the flash status register reports that the flash
chip is currently write protected.
Then it will call out to a SOC specific function that will
enable write protection on the RW_MRC_CACHE region of flash.
The implementation is not quite as clean as I would like because
there is not a common flash protect interface across SOCs so
instead it relies on a new Kconfig variable to be set that will
indicate a SOC implements the function to protect a region of
SPI flash.
BUG=chrome-os-partner:28234
BRANCH=broadwell
TEST=build and boot on samus
1) with either WPSW=0 or SRP0=0 the PRR is not applied
2) with both WPSW=1 and SRP0=1 the PRR is applied
Change-Id: If5907b7ddf3f966c546ae32dc99aa815beb27587
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: a3e0e71dfd7339aab171a26b67aec465a3f332d6
Original-Change-Id: I94e54e4723b1dcdacbb6a05f047d0c0ebc7d8711
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241170
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
---
src/soc/intel/common/Kconfig | 4 ++++
src/soc/intel/common/mrc_cache.c | 21 +++++++++++++++++++
src/soc/intel/common/nvm.c | 44 ++++++++++++++++++++++++++++++++++++++++
src/soc/intel/common/nvm.h | 6 ++++++
4 files changed, 75 insertions(+)
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 8b02a4a..aadd64d 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -14,6 +14,10 @@ config MRC_SETTINGS_CACHE_SIZE
hex
default 0x10000
+config MRC_SETTINGS_PROTECT
+ bool "Enable protection on MRC settings"
+ default n
+
endif # CACHE_MRC_SETTINGS
endif # HAVE_MRC
diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c
index 5860201..f854046 100644
--- a/src/soc/intel/common/mrc_cache.c
+++ b/src/soc/intel/common/mrc_cache.c
@@ -247,6 +247,25 @@ mrc_cache_next_slot(const struct mrc_data_region *region,
return next_slot;
}
+/* Protect RW_MRC_CACHE region with a Protected Range Register */
+static int protect_mrc_cache(const struct mrc_data_region *region)
+{
+#if IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT)
+ if (nvm_is_write_protected() <= 0) {
+ printk(BIOS_INFO, "NOT enabling PRR for RW_MRC_CACHE region\n");
+ return 1;
+ }
+
+ if (nvm_protect(region->base, region->size) < 0) {
+ printk(BIOS_ERR, "ERROR setting PRR for RW_MRC_CACHE region\n");
+ return -1;
+ }
+
+ printk(BIOS_INFO, "Enabled Protected Range on RW_MRC_CACHE region\n");
+#endif
+ return 0;
+}
+
static void update_mrc_cache(void *unused)
{
const struct mrc_saved_data *current_boot;
@@ -279,6 +298,7 @@ static void update_mrc_cache(void *unused)
!memcmp(¤t_saved->data[0], ¤t_boot->data[0],
current_saved->size)) {
printk(BIOS_DEBUG, "MRC cache up to date.\n");
+ protect_mrc_cache(®ion);
return;
}
}
@@ -301,6 +321,7 @@ static void update_mrc_cache(void *unused)
printk(BIOS_DEBUG, "Failure writing MRC cache to %p.\n",
next_slot);
}
+ protect_mrc_cache(®ion);
}
BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);
diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c
index 791422f..8ff4fd6 100644
--- a/src/soc/intel/common/nvm.c
+++ b/src/soc/intel/common/nvm.c
@@ -23,6 +23,10 @@
#include <string.h>
#include <spi-generic.h>
#include <spi_flash.h>
+#include <soc/spi.h>
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
#include "nvm.h"
/* This module assumes the flash is memory mapped just below 4GiB in the
@@ -80,3 +84,43 @@ int nvm_write(void *start, const void *data, size_t size)
return -1;
return flash->write(flash, to_flash_offset(start), size, data);
}
+
+/* Read flash status register to determine if write protect is active */
+int nvm_is_write_protected(void)
+{
+ u8 sr1;
+ u8 wp_gpio = 0;
+ u8 wp_spi;
+
+ if (nvm_init() < 0)
+ return -1;
+
+#if IS_ENABLED(CONFIG_CHROMEOS)
+ /* Read Write Protect GPIO if available */
+ wp_gpio = get_write_protect_state();
+#endif
+
+ /* Read Status Register 1 */
+ if (spi_flash_status(flash, &sr1) < 0) {
+ printk(BIOS_ERR, "Failed to read SPI status register 1\n");
+ return -1;
+ }
+ wp_spi = !!(sr1 & 0x80);
+
+ printk(BIOS_DEBUG, "SPI flash protection: WPSW=%d SRP0=%d\n",
+ wp_gpio, wp_spi);
+
+ return wp_gpio && wp_spi;
+}
+
+/* Apply protection to a range of flash */
+int nvm_protect(void *start, size_t size)
+{
+#if IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT)
+ if (nvm_init() < 0)
+ return -1;
+ return spi_flash_protect(to_flash_offset(start), size);
+#else
+ return -1;
+#endif
+}
diff --git a/src/soc/intel/common/nvm.h b/src/soc/intel/common/nvm.h
index d332d83..2e6b364 100644
--- a/src/soc/intel/common/nvm.h
+++ b/src/soc/intel/common/nvm.h
@@ -31,4 +31,10 @@ int nvm_erase(void *start, size_t size);
/* Write data to NVM. Returns 0 on success < 0 on error. */
int nvm_write(void *start, const void *data, size_t size);
+/* Determine if flash device is write protected */
+int nvm_is_write_protected(void);
+
+/* Apply protection to a range of flash */
+int nvm_protect(void *start, size_t size);
+
#endif /* _COMMON_NVM_H_ */
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9492
-gerrit
commit 4143dbeccb20730154b1fef43e6fc9ef4bd91612
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Jan 15 13:24:38 2015 -0800
samus: Add clear_recovery_mode_switch function
In order for recovery request to be cleared with software sync disabled
we need to implement this function in the mainboard.
BUG=chrome-os-partner:28234
BRANCH=samus
TEST=boot in recovery with software sync disabled, ensure that the next
boot will not boot in recovery again.
Change-Id: Ie9c845396dfc6ab65296b2f18a86e23590c833d6
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 430f85608cc3b59a68a86dba64ffe428bfc216a9
Original-Change-Id: Iac15b6a1b23cc971231339439bceb013f4a031bd
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241052
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
---
src/mainboard/google/samus/chromeos.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/mainboard/google/samus/chromeos.c b/src/mainboard/google/samus/chromeos.c
index fc7acff..fab06e8 100644
--- a/src/mainboard/google/samus/chromeos.c
+++ b/src/mainboard/google/samus/chromeos.c
@@ -92,6 +92,15 @@ int get_recovery_mode_switch(void)
#endif
}
+int clear_recovery_mode_switch(void)
+{
+ const uint32_t kb_rec_mask =
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY);
+
+ /* Unconditionally clear the EC recovery request. */
+ return google_chromeec_clear_events_b(kb_rec_mask);
+}
+
int get_write_protect_state(void)
{
return get_gpio(CROS_WP_GPIO);
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9491
-gerrit
commit af8e17b7faf7a3eee1b19715643c876c60bdca34
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Jan 14 17:36:08 2015 -0800
samus: Set current backlight PWM value
With recent changes in the 3.14 kernel and the switch to not
using X the panel backlight is not geting turned on until
chrome is started which means the splash screen is not visible.
If we set the backlight PWM in coreboot then it will at least
turn on for the early boot process.
BUG=chrome-os-partner:31549
BRANCH=samus
TEST=boot on samus in normal mode and see the boot splash logo
Change-Id: I81e6b90617acb181b4de3365f8f56ec3b846b78b
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: f850fe3faff268a64f18e6bd176ec1126b921e3b
Original-Change-Id: I622bef8af9bb6b753fe228b33ecdc4aae76af131
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240853
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
---
src/mainboard/google/samus/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb
index 26b7b41..0ca7405 100644
--- a/src/mainboard/google/samus/devicetree.cb
+++ b/src/mainboard/google/samus/devicetree.cb
@@ -11,7 +11,7 @@ chip soc/intel/broadwell
# Set backlight PWM values for eDP
register "gpu_cpu_backlight" = "0x00000200"
- register "gpu_pch_backlight" = "0x04000000"
+ register "gpu_pch_backlight" = "0x04000200"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9490
-gerrit
commit c80abbffcbb73610eddb9f3b58e18657719a73e4
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Jan 14 17:33:00 2015 -0800
broadwell: Turn off panel backlight in S5 SMI handler
In order for some panels to meet spec when the system is put
into S5 by way of power button during firmware (i.e. not by
the OS) then it needs to turn off the backlight and give it
time to turn off before going into S5.
If the OS properly sequences the panel down then the backlight
enable bit will not be set in this step and nothing will happen.
BUG=chrome-os-partner:33994
BRANCH=broadwell
TEST=build and boot on samus
Change-Id: Ic86f388218f889b1fe690cc1bfc5c3e233e95115
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: e3c9c131a87bae380e1fd3f96c9ad780441add56
Original-Change-Id: I43c5aee8e32768fc9e82790c9f7ceda0ed17ed13
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240852
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
---
src/soc/intel/broadwell/smihandler.c | 43 ++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index 5004a6a..0374d15 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -36,6 +36,7 @@
#include <soc/rcba.h>
#include <soc/smm.h>
#include <soc/xhci.h>
+#include <device/i915_reg.h>
static u8 smm_initialized = 0;
@@ -109,6 +110,45 @@ static void busmaster_disable_on_bus(int bus)
}
}
+/*
+ * Turn off the backlight if it is on, and wait for the specified
+ * backlight off delay. This will allow panel power timings to meet
+ * spec and prevent brief garbage on the screen when turned off
+ * during firmware with power button triggered SMI.
+ */
+static void backlight_off(void)
+{
+ uint32_t reg_base;
+ uint32_t pp_ctrl;
+ uint32_t bl_off_delay;
+
+ reg_base = pci_read_config32(SA_DEV_IGD, PCI_BASE_ADDRESS_0) & ~0xf;
+
+ /* Check if backlight is enabled */
+ pp_ctrl = read32(reg_base + PCH_PP_CONTROL);
+ if (!(pp_ctrl & EDP_BLC_ENABLE))
+ return;
+
+ /* Enable writes to this register */
+ pp_ctrl &= ~PANEL_UNLOCK_MASK;
+ pp_ctrl |= PANEL_UNLOCK_REGS;
+
+ /* Turn off backlight */
+ pp_ctrl &= ~EDP_BLC_ENABLE;
+
+ write32(reg_base + PCH_PP_CONTROL, pp_ctrl);
+ read32(reg_base + PCH_PP_CONTROL);
+
+ /* Read backlight off delay in 100us units */
+ bl_off_delay = read32(reg_base + PCH_PP_OFF_DELAYS);
+ bl_off_delay &= PANEL_LIGHT_OFF_DELAY_MASK;
+ bl_off_delay *= 100;
+
+ /* Wait for backlight to turn off */
+ udelay(bl_off_delay);
+
+ printk(BIOS_INFO, "Backlight turned off\n");
+}
static void southbridge_smi_sleep(void)
{
@@ -170,6 +210,9 @@ static void southbridge_smi_sleep(void)
case SLP_TYP_S5:
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
+ /* Turn off backlight if needed */
+ backlight_off();
+
/* Disable all GPE */
disable_all_gpe();