coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 043c2fb northbridge/amd/amdht: Allow mainboards to set HT frequency limit
by Timothy Pearson 04 Mar '15

04 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8464 -gerrit commit 043c2fbf580e9394adbec0924243a5d097f73578 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Feb 16 14:57:06 2015 -0600 northbridge/amd/amdht: Allow mainboards to set HT frequency limit This is useful when the PCB layout of a mainboard does not allow stable operation at the increased HyperTransport speeds of newer processors. Change-Id: Idc93a1294608178ddf38ca72d40e6bad7deb9004 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/amdfam10.h | 7 +++++++ src/northbridge/amd/amdht/h3finit.c | 29 ++++++++++++++++++++++++++--- src/northbridge/amd/amdht/h3finit.h | 3 +++ src/northbridge/amd/amdht/ht_wrapper.c | 3 ++- 4 files changed, 38 insertions(+), 4 deletions(-) diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index ab4b42e..af9e24e 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -1033,6 +1034,10 @@ struct nodes_info_t { u32 up_planes; // down planes will be [up_planes, planes) } __attribute__((packed)); +struct ht_link_config { + uint8_t ht_speed_limit; // Speed in MHz; 0 for autodetect (default) +}; + /* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and ramstage stage. and ramstage may be running at 64bit later.*/ #if !CONFIG_AMDMCT @@ -1053,6 +1058,8 @@ struct sys_info { u8 host_link_freq[NODE_NUMS*8]; // record freq for every link from cpu, 0x0f means don't need to touch it u16 host_link_freq_cap[NODE_NUMS*8]; //cap + struct ht_link_config ht_link_cfg; + u32 segbit; u32 sbdn; u32 sblk; diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 4059182..10973aa 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -75,6 +75,30 @@ static const uint16_t ht_speed_limit[16] = 0x00FF, 0x007F, 0x003F, 0x001F, 0x000F, 0x0007, 0x0003, 0x0001}; +static const uint16_t ht_speed_mhz_to_hw(uint16_t mhz) +{ + switch(mhz) { + case 200: return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_200]; + case 300: return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_300]; + case 400: return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_400]; + case 500: return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_500]; + case 600: return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_600]; + case 800: return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_800]; + case 1000: return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_1000]; + case 1200: return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_1200]; + case 1400: return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_1400]; + case 1600: return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_1600]; + case 1800: return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_1800]; + case 2000: return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_2000]; + case 2200: return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_2200]; + case 2400: return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_2400]; + case 2600: return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_2600]; + case 0: return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_AUTO]; + default: printk(BIOS_WARNING, "WARNING: Invalid HT link limit frequency %d specified, ignoring...\n", mhz); + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_AUTO]; + } +} + /*---------------------------------------------------------------------------- * TYPEDEFS AND STRUCTURES * @@ -1359,10 +1383,9 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat) for (i = 0; i < pDat->TotalLinks*2; i += 2) { - /* FIXME - * Mainboards need to be able to set cbPCBFreqLimit - */ cbPCBFreqLimit = 0xFFFF; // Maximum allowed by autoconfiguration + if (pDat->HtBlock->ht_link_configuration) + cbPCBFreqLimit = ht_speed_mhz_to_hw(pDat->HtBlock->ht_link_configuration->ht_speed_limit); cbPCBFreqLimit = min(cbPCBFreqLimit, cbPCBFreqLimit_NVRAM); #if CONFIG_EXPERT && CONFIG_LIMIT_HT_DOWN_WIDTH_8 diff --git a/src/northbridge/amd/amdht/h3finit.h b/src/northbridge/amd/amdht/h3finit.h index 136a5cf..a56c246 100644 --- a/src/northbridge/amd/amdht/h3finit.h +++ b/src/northbridge/amd/amdht/h3finit.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -462,6 +463,8 @@ typedef struct { const u8 *pEventData0 ); + const struct ht_link_config *ht_link_configuration; + } AMD_HTBLOCK; /* diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 3bf81c6..a38caa4 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -139,7 +139,8 @@ static void amd_ht_init(struct sys_info *sysinfo) NULL, // BOOL (*AMD_CB_CustomizeBuffers)(); NULL, // void (*AMD_CB_OverrideDevicePort)(); NULL, // void (*AMD_CB_OverrideCpuPort)(); - AMD_CB_EventNotify // void (*AMD_CB_EventNotify) (); + AMD_CB_EventNotify, // void (*AMD_CB_EventNotify) (); + &sysinfo->ht_link_cfg // struct ht_link_config* }; printk(BIOS_DEBUG, "Enter amd_ht_init()\n");

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Patch merged into coreboot/master: 8ddc1f3 rush: enable 128MiB MTS carveout below top of DRAM
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit 8ddc1f328ad2c6071c5c3dc126ec04f4e2e4a927 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jun 30 16:42:13 2014 -0500 rush: enable 128MiB MTS carveout below top of DRAM The recommended settings for the size of the MTS region is 128MiB. Therefore, provide this region 128MiB below the top of DRAM for each configuration. BUG=chrome-os-partner:29922 BRANCH=None TEST=Built and noted MTS carveout region at expected location. Original-Change-Id: Iac17f210dfef8e8a36617c7b3dceba8c2134ee9b Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/206291 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit f1758c74330afe9dd7eaa8ff1fef5e4d18ed14ad) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I369a3897e31f3126d031d3582f52f9892350f658 Reviewed-on: http://review.coreboot.org/8579 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8579 for details. -gerrit

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Patch merged into coreboot/master: 0e69639 t132: Replace fallback with CONFIG_CBFS_PREFIX
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit 0e69639909ff4e1d824781b7404461b07ea29942 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Mar 3 15:17:15 2015 -0700 t132: Replace fallback with CONFIG_CBFS_PREFIX Use the Kconfig value to load the name of the stage instead of the hard-coded fallback stage. (cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I1ac707efe38e29f109dbbe206de74fbfe7cb7b0b Reviewed-on: http://review.coreboot.org/8576 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8576 for details. -gerrit

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Patch set updated for coreboot: c374ab4 t132: Replace fallback with CONFIG_CBFS_PREFIX
by Marc Jones 04 Mar '15

04 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8576 -gerrit commit c374ab4028f79efbfa488cba9d42ec406f97ab4b Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Mar 3 15:17:15 2015 -0700 t132: Replace fallback with CONFIG_CBFS_PREFIX Use the Kconfig value to load the name of the stage instead of the hard-coded fallback stage. (cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I1ac707efe38e29f109dbbe206de74fbfe7cb7b0b --- src/soc/nvidia/tegra132/bootblock.c | 3 ++- src/soc/nvidia/tegra132/romstage.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c index 62e5228..ad78f51 100644 --- a/src/soc/nvidia/tegra132/bootblock.c +++ b/src/soc/nvidia/tegra132/bootblock.c @@ -68,7 +68,8 @@ void main(void) printk(BIOS_INFO, "T132 bootblock: Mainboard bootblock init done\n"); - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, + CONFIG_CBFS_PREFIX "/romstage"); if (entry) { printk(BIOS_INFO, "T132 bootblock: jumping to romstage\n"); diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index a4a0636..20429a5 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -40,6 +40,7 @@ void main(void) while (1); - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, + CONFIG_CBFS_PREFIX "/ramstage"); stage_exit(entry); }

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Patch merged into coreboot/master: 1ac4e59 t132: Add shared romstage
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit 1ac4e591bfcfd135ab46843fcbee0342e21a8689 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jun 27 16:43:59 2014 -0500 t132: Add shared romstage There's no reason to duplicate code in the mainboards. Therefore, drive the flow of romstage boot in the SoC. This allows for easier scaling with multiple devices. BUG=None BRANCH=None TEST=Built and booted to same place as before. Original-Change-Id: I0d4df84034b19353daad0da1f722b820596c4f55 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205992 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ie74f0eb1c983aff92d3cbafb7fe7d9d7cb65ae19 Reviewed-on: http://review.coreboot.org/8575 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8575 for details. -gerrit

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Patch merged into coreboot/master: 650d11c coreboot rush: Add dram init code
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit 650d11ce94dea9ecc3fee3c2eb4dcb423af3f503 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Jun 26 14:24:42 2014 -0700 coreboot rush: Add dram init code Add support for initializing dram within romstage. This is an essential before we move to the armv8 core. BUG=None BRANCH=None TEST=Compiles succesfully for rush. Tried writing to and reading value from the base of sdram and it worked fine. Also tested with primitive_memtest CL: https://chromium-review.googlesource.com/#/c/186309/5 Original-Change-Id: I67ec04c766e249c9727b0cf2ba216522c862c2f5 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205823 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 33c468b16e7ccd8cf9266d6a9ca30c02da104821) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I4baface2c109ca74f85f43a25508677c46c64159 Reviewed-on: http://review.coreboot.org/8574 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8574 for details. -gerrit

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Patch merged into coreboot/master: d42b3fc coreboot rush: Add support for basic romstage
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit d42b3fc6a9adda4a20cd331b27117d95c70887a4 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Jun 26 00:11:29 2014 -0700 coreboot rush: Add support for basic romstage Add basic romstage support for rush. Since, dram init needs to be done before we can jump to armv8 core, romstage will run on armv4 core as well. Thus, correcting the compiler selection options. BUG=None BRANCH=None TEST=Compiles successfully for rush. Prints romstage banner and initial printk Original-Change-Id: Ie3cd290e56a712b07c1503dab199e4e34cec04d2 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205763 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit d20b4e66209e902f54a07a17d5ce741f0a0b3a7b) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ic6b7ef4a2ea01c95d0c7f040bbd079219cf5750a Reviewed-on: http://review.coreboot.org/8573 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/8573 for details. -gerrit

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Patch merged into coreboot/master: b68cb9e coreboot t132: Enable loading of romstage from CBFS media
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit b68cb9e8ae63d734f5cea42d54eef11d726a5964 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jun 25 15:19:13 2014 -0700 coreboot t132: Enable loading of romstage from CBFS media Add proper Kconfig options and initialize cbfs media to enable loading of romstage BUG=None BRANCH=None TEST=Compiles successfully for rush and cbfs_load_stage returns entry pointer for romstage Original-Change-Id: If62edcdc0496d89d30003ffd7b827b77835910fd Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205762 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit c89c05bc86fd6c1e49fbed5e0730659b64bffc6c) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I68c10171424c85605b5065a19634d3c5dd639b78 Reviewed-on: http://review.coreboot.org/8572 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8572 for details. -gerrit

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Patch merged into coreboot/master: f0d150e coreboot t132: Remove init pllx for now
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit f0d150e0bad67a6ffd6fb175ed1591f944df106e Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jun 25 11:37:04 2014 -0700 coreboot t132: Remove init pllx for now We suspect that the code was stuck on init pllx (PLLX - acts as a clock source for the CPU cluster). So, remove the init call for pllx. This needs to be added later when required. Also, add a few more printks to display the progress. BUG=None BRANCH=None TEST=Compiles successfully for rush. Print messages seen on serial console. Original-Change-Id: I70e908a9ce1f3598d68bda68c0401a78834597d1 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205680 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit d557d99edb855fbf7b32231c6746c676041bf62a) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Iaf56f2d587708c6e9fb01d4ced2edb5931075a81 Reviewed-on: http://review.coreboot.org/8571 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8571 for details. -gerrit

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Patch merged into coreboot/master: 84bbab9 coreboot t132, rush: Add mainboard specific bootblock_init
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit 84bbab9226163cca6ec58e4d5875fea1e53ec3b4 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jun 24 17:38:03 2014 -0700 coreboot t132,rush: Add mainboard specific bootblock_init Pull in mainboard specific bootblock_init function from nyan into rush. Additionally, pull in all files required for proper compilation of rush after adding the bootblock_init function BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I69c736275f66eca3ad92f97d166e91d4c2301364 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205583 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit e7aac547026717d7380f71593010e3ea34ecea51) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ie26f91f8caaa06af3b195246febcdc70b9fe9795 Reviewed-on: http://review.coreboot.org/8570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8570 for details. -gerrit

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coreboot-gerrit March 2015