coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: dfe7ea2 rush: PMIC: initial AS3722 PMIC writes for Rush
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit dfe7ea2b4eb86afcb59819fc9a72a41ceede8215 Author: Tom Warren <twarren(a)nvidia.com> Date: Tue Jul 1 17:08:27 2014 -0700 rush: PMIC: initial AS3722 PMIC writes for Rush Still waiting on VDD_CPU value, etc. from board guys, but this is a start. BUG=None BRANCH=None TEST=Built and flashed rush, saw 'PMIC init done' string OK. Original-Change-Id: I6f8b16c4ebf1e9c159f8175d59262119ef0e498f Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206412 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 96a9ff8f632c2b9bf3f81f5b8fc4f3b6784a02bc) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I9d3d7ff55f2d6ca88ebdcc8ad1d7de135f5136d2 Reviewed-on: http://review.coreboot.org/8582 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8582 for details. -gerrit

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Patch merged into coreboot/master: d2907c1 t132: kick off core complex after loading MTS microcode
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit d2907c1e0267eddd1a04e4d6d9670ef95c43e0b9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jul 1 13:51:21 2014 -0500 t132: kick off core complex after loading MTS microcode Once the MTS microcode is loaded the core complex can be directed to decode the MTS and start running. The cores, however, won't start executing until instructed to do so. BUG=chrome-os-partner:29222 BRANCH=None TEST=Built, booted, ran. Noted it took about 920ms for the core complex to decode and handshake back. Original-Change-Id: I0a9ed53e596eb65801461b2769d133710a92a48a Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/206075 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> (cherry picked from commit 6edb6e21a69d84ba5b23137e9e390954159e7887) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I179e561bb3a34b206620eecde6781a1c05a3744e Reviewed-on: http://review.coreboot.org/8581 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/8581 for details. -gerrit

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Patch merged into coreboot/master: 196ee2b coreboot memrange: Two changes for zero size or empty memrange
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit 196ee2b029349588d1cac4f01c4e1b92f9dd8447 Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Jul 18 10:25:54 2014 -0700 coreboot memrange: Two changes for zero size or empty memrange 1) Add check for zero size in memrange. 2) Add public memrange_init_empty function to allow initializing only the memrange structure without filling in device resources BUG=None BRANCH=None TEST=Compiles and runs succesfully for rush MMU memranges. Original-Change-Id: I8e4d864cbc9a770cd208f8a9f83f509dc7ace894 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208957 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 5c42301c2a51a1a2a29ef58012f210d03bd37f94) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I8d63abb15efda74270ef6fa3c0df55c05659595d Reviewed-on: http://review.coreboot.org/8597 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8597 for details. -gerrit

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Patch set updated for coreboot: 085ea67 coreboot memrange: Two changes for zero size or empty memrange
by Marc Jones 04 Mar '15

04 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8597 -gerrit commit 085ea67409697f3387bb6a6d04c92a3a3229cce8 Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Jul 18 10:25:54 2014 -0700 coreboot memrange: Two changes for zero size or empty memrange 1) Add check for zero size in memrange. 2) Add public memrange_init_empty function to allow initializing only the memrange structure without filling in device resources BUG=None BRANCH=None TEST=Compiles and runs succesfully for rush MMU memranges. Original-Change-Id: I8e4d864cbc9a770cd208f8a9f83f509dc7ace894 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208957 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 5c42301c2a51a1a2a29ef58012f210d03bd37f94) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I8d63abb15efda74270ef6fa3c0df55c05659595d --- src/include/memrange.h | 3 +++ src/lib/memrange.c | 10 +++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/include/memrange.h b/src/include/memrange.h index ba85bef..048c287 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -75,6 +75,9 @@ static inline void range_entry_update_tag(struct range_entry *r, #define memranges_each_entry(r, ranges) \ for (r = (ranges)->entries; r != NULL; r = r->next) +/* Initialize memranges structure */ +void memranges_init_empty(struct memranges *ranges); + /* Initialize and fill a memranges structure according to the * mask and match type for all memory resources. Tag each entry with the * specified type. */ diff --git a/src/lib/memrange.c b/src/lib/memrange.c index a85bc01..d2ffa26 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -228,6 +228,9 @@ static void do_action(struct memranges *ranges, resource_t end; resource_t begin; + if (size == 0) + return; + /* The addresses are aligned to 4096 bytes: the begin address is * aligned down while the end address is aligned up to be conservative * about the full range covered. */ @@ -290,11 +293,16 @@ void memranges_add_resources(struct memranges *ranges, memranges_add_resources_filter(ranges, mask, match, tag, NULL); } +void memranges_init_empty(struct memranges *ranges) +{ + ranges->entries = NULL; +} + void memranges_init(struct memranges *ranges, unsigned long mask, unsigned long match, unsigned long tag) { - ranges->entries = NULL; + memranges_init_empty(ranges); memranges_add_resources(ranges, mask, match, tag); }

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Patch merged into coreboot/master: 2dd161f cbfstool: Clean up code
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit 2dd161f556eb0bfb4f092d35397fd04c98d1a3fb Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Mar 4 00:55:03 2015 +0100 cbfstool: Clean up code cbfstool has diverged between coreboot upstream and the chromium tree. Bring in some of the chromium changes, in particular the useful remainders of cbf37fe (https://chromium-review.googlesource.com/176710) - fix coding style - mark unused variables explicitly unused - remove some dead code Change-Id: I354aaede8ce425ebe99d4c60c232feea62bf8a11 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/8577 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/8577 for details. -gerrit

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Patch set updated for coreboot: cd9f93b cbfstool: Clean up code
by Stefan Reinauer 04 Mar '15

04 Mar '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8577 -gerrit commit cd9f93b4ffa9d7767263b363be292a031eb4690c Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Mar 4 00:55:03 2015 +0100 cbfstool: Clean up code cbfstool has diverged between coreboot upstream and the chromium tree. Bring in some of the chromium changes, in particular the useful remainders of cbf37fe (https://chromium-review.googlesource.com/176710) - fix coding style - mark unused variables explicitly unused - remove some dead code Change-Id: I354aaede8ce425ebe99d4c60c232feea62bf8a11 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/cbfstool/Makefile | 3 +-- util/cbfstool/cbfs.h | 1 - util/cbfstool/cbfs_image.c | 26 +++----------------------- util/cbfstool/cbfstool.c | 10 +++++++--- util/cbfstool/common.c | 12 ++++++++---- util/cbfstool/common.h | 16 +++++++++------- util/cbfstool/lzma/lzma.c | 8 ++++---- 7 files changed, 32 insertions(+), 44 deletions(-) diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile index 4f282f9..05a96ee 100644 --- a/util/cbfstool/Makefile +++ b/util/cbfstool/Makefile @@ -4,8 +4,7 @@ HOSTCC ?= $(CC) CFLAGS ?= -g CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -CFLAGS += -Wstrict-aliasing -Werror -CFLAGS += -Wshadow +CFLAGS += -Wstrict-aliasing -Wshadow -Werror CBFSTOOL_BINARY:=$(obj)/cbfstool diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index f7cd39a..e5011d6 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -125,7 +125,6 @@ struct cbfs_payload { #define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) ) /* cbfs_image.c */ uint32_t get_cbfs_entry_type(const char *name, uint32_t default_value); -const char *get_cbfs_entry_type_name(uint32_t type); uint32_t get_cbfs_compression(const char *name, uint32_t unknown); /* common.c */ diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 6775b06..6b0ed59 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -69,16 +69,6 @@ static uint32_t align_up(uint32_t value, uint32_t align) return value; } -static uint32_t lookup_type_by_name(const struct typedesc_t *desc, const char *name, - uint32_t default_value) -{ - int i; - for (i = 0; desc[i].name; i++) - if (strcmp(desc[i].name, name) == 0) - return desc[i].type; - return default_value; -} - static const char *lookup_name_by_type(const struct typedesc_t *desc, uint32_t type, const char *default_value) { @@ -89,21 +79,11 @@ static const char *lookup_name_by_type(const struct typedesc_t *desc, uint32_t t return default_value; } -uint32_t get_cbfs_entry_type(const char *name, uint32_t default_value) -{ - return lookup_type_by_name(types_cbfs_entry, name, default_value); -} - -const char *get_cbfs_entry_type_name(uint32_t type) +static const char *get_cbfs_entry_type_name(uint32_t type) { return lookup_name_by_type(types_cbfs_entry, type, "(unknown)"); } -uint32_t get_cbfs_compression(const char *name, uint32_t unknown) -{ - return lookup_type_by_name(types_cbfs_compression, name, unknown); -} - /* CBFS image */ static int cbfs_calculate_file_header_size(const char *name) @@ -186,7 +166,7 @@ void cbfs_get_header(struct cbfs_header *header, const void *src) } int cbfs_image_create(struct cbfs_image *image, - uint32_t myarch, + uint32_t architecture, size_t size, uint32_t align, struct buffer *bootblock, @@ -253,7 +233,7 @@ int cbfs_image_create(struct cbfs_image *image, image->header->bootblocksize = bootblock->size; image->header->align = align; image->header->offset = entries_offset; - image->header->architecture = myarch; + image->header->architecture = architecture; header_loc = (image->buffer.data + header_offset); cbfs_put_header(header_loc, image->header); diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 41df157..80331e7 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -118,7 +118,8 @@ static int cbfs_add_component(const char *cbfs_name, const char *name, uint32_t type, uint32_t offset, - convert_buffer_t convert) { + convert_buffer_t convert) +{ struct cbfs_image image; struct buffer buffer; @@ -194,7 +195,9 @@ static int cbfstool_convert_mkstage(struct buffer *buffer, uint32_t *offset) return 0; } -static int cbfstool_convert_mkpayload(struct buffer *buffer, uint32_t *offset) { +static int cbfstool_convert_mkpayload(struct buffer *buffer, + unused uint32_t *offset) +{ struct buffer output; int ret; /* per default, try and see if payload is an ELF binary */ @@ -222,7 +225,8 @@ static int cbfstool_convert_mkpayload(struct buffer *buffer, uint32_t *offset) { } static int cbfstool_convert_mkflatpayload(struct buffer *buffer, - uint32_t *offset) { + unused uint32_t *offset) +{ struct buffer output; if (parse_flat_binary_to_payload(buffer, &output, param.loadaddress, diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index bd9cdc0..6ac39ef 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -53,7 +53,8 @@ static off_t get_file_size(FILE *f) } /* Buffer and file I/O */ -int buffer_create(struct buffer *buffer, size_t size, const char *name) { +int buffer_create(struct buffer *buffer, size_t size, const char *name) +{ buffer->name = strdup(name); buffer->size = size; buffer->data = (char *)malloc(buffer->size); @@ -64,7 +65,8 @@ int buffer_create(struct buffer *buffer, size_t size, const char *name) { return (buffer->data == NULL); } -int buffer_from_file(struct buffer *buffer, const char *filename) { +int buffer_from_file(struct buffer *buffer, const char *filename) +{ FILE *fp = fopen(filename, "rb"); if (!fp) { perror(filename); @@ -88,7 +90,8 @@ int buffer_from_file(struct buffer *buffer, const char *filename) { return 0; } -int buffer_write_file(struct buffer *buffer, const char *filename) { +int buffer_write_file(struct buffer *buffer, const char *filename) +{ FILE *fp = fopen(filename, "wb"); if (!fp) { perror(filename); @@ -104,7 +107,8 @@ int buffer_write_file(struct buffer *buffer, const char *filename) { return 0; } -void buffer_delete(struct buffer *buffer) { +void buffer_delete(struct buffer *buffer) +{ assert(buffer); if (buffer->name) { free(buffer->name); diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index 41659a2..02a1076 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -31,7 +31,7 @@ #endif #define ntohll(x) (is_big_endian() ? (x) : swab64(x)) #define htonll(x) (is_big_endian() ? (x) : swab64(x)) -extern int is_big_endian(void); +int is_big_endian(void); /* Message output */ extern int verbose; @@ -41,6 +41,12 @@ extern int verbose; #define INFO(x...) { if (verbose > 0) fprintf(stderr, "INFO: " x); } #define DEBUG(x...) { if (verbose > 1) fprintf(stderr, "DEBUG: " x); } +/* Helpers */ +#define ARRAY_SIZE(a) (int)(sizeof(a) / sizeof((a)[0])) +#define ALIGN(val, by) (((val) + (by)-1)&~((by)-1)) + +#define unused __attribute__((unused)) + /* Buffer and file I/O */ struct buffer { char *name; @@ -72,8 +78,7 @@ static inline void buffer_init(struct buffer *b, char *name, void *data, b->size = size; } -/* - * Splice a buffer into another buffer. If size is zero the entire buffer +/* Splice a buffer into another buffer. If size is zero the entire buffer * is spliced while if size is non-zero the buffer is spliced starting at * offset for size bytes. Note that it's up to caller to bounds check. */ @@ -115,8 +120,6 @@ void buffer_delete(struct buffer *buffer); const char *arch_to_string(uint32_t a); uint32_t string_to_arch(const char *arch_string); -#define ALIGN(val, by) (((val) + (by)-1)&~((by)-1)) - typedef int (*comp_func_ptr) (char *, int, char *, int *); typedef enum { CBFS_COMPRESS_NONE = 0, CBFS_COMPRESS_LZMA = 1 } comp_algo; @@ -144,10 +147,10 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, void print_supported_filetypes(void); -#define ARRAY_SIZE(a) (int)(sizeof(a) / sizeof((a)[0])) /* lzma/lzma.c */ int do_lzma_compress(char *in, int in_len, char *out, int *out_len); int do_lzma_uncompress(char *dst, int dst_len, char *src, int src_len); + /* xdr.c */ struct xdr { uint8_t (*get8)(struct buffer *input); @@ -160,7 +163,6 @@ struct xdr { void (*put64)(struct buffer *input, uint64_t val); }; -/* xdr.c */ extern struct xdr xdr_le, xdr_be; size_t bgets(struct buffer *input, void *output, size_t len); size_t bputs(struct buffer *b, const void *data, size_t len); diff --git a/util/cbfstool/lzma/lzma.c b/util/cbfstool/lzma/lzma.c index abd1bfd..0944b1f 100644 --- a/util/cbfstool/lzma/lzma.c +++ b/util/cbfstool/lzma/lzma.c @@ -31,12 +31,12 @@ static void put_64(void *p, uint64_t value) /* Memory Allocation API */ -static void *SzAlloc(void *unused, size_t size) +static void *SzAlloc(unused void *u, size_t size) { return malloc(size); } -static void SzFree(void *unused, void *address) +static void SzFree(unused void *u, void *address) { free(address); } @@ -53,7 +53,7 @@ struct vector_t { static struct vector_t instream, outstream; -static SRes Read(void *unused, void *buf, size_t *size) +static SRes Read(unused void *u, void *buf, size_t *size) { if ((instream.size - instream.pos) < *size) *size = instream.size - instream.pos; @@ -62,7 +62,7 @@ static SRes Read(void *unused, void *buf, size_t *size) return SZ_OK; } -static size_t Write(void *unused, const void *buf, size_t size) +static size_t Write(unused void *u, const void *buf, size_t size) { if(outstream.size - outstream.pos < size) size = outstream.size - outstream.pos;

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Patch merged into coreboot/master: 3aca2cd t132: load MTS microcode
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit 3aca2cdced54ff525022366bc6dee949b0152d83 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jun 30 16:37:13 2014 -0500 t132: load MTS microcode The armv8 cores need to have microcode loaded before they can be taken out of reset. Locate and load the MTS microcode at the fixed address of 0x82000000. The ccplex, once enabled, will decode and transfer the microcode to the carveout region. BUG=chrome-os-partner:29922 BRANCH=None TEST=Built and ran. Confirmed dump of MTS region after loading code. Original-Change-Id: Ie5ab72e5363cbdb251d169356f718020d375fce6 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/206290 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 6726d8862c08b155b9218aa5e2e39428a105089e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I425c2e2fd1eaec49d81bef1ff4bf4f36da9296df Reviewed-on: http://review.coreboot.org/8580 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8580 for details. -gerrit

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Patch merged into coreboot/master: 73307e0 Add stage information to coreboot banner
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit 73307e0917c9084f1dc264ac2a61a094fddf1167 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Mar 4 01:11:18 2015 +0100 Add stage information to coreboot banner As a convenience, print the actual stage name when entering a stage. Also unify the banner between bootblock / romstage and ramstage. No reason for two different occurences. Instead of this: coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 booting... you will see this: coreboot-4.0 Tue May 13 14:13:37 PDT 2014 bootblock starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 romstage starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 ramstage starting... Roughly based on: https://chromium-review.googlesource.com/199671 Change-Id: Id5894535e0551d113c80e4ff0514287391be1bef Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: http://review.coreboot.org/8578 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/8578 for details. -gerrit

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Patch set updated for coreboot: e0a6715 northbridge/amd/amdht: Allow mainboards to set HT frequency limit
by Timothy Pearson 04 Mar '15

04 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8464 -gerrit commit e0a67150bcb24ccc019f1fc80f11eeb8e6c54aec Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Feb 16 14:57:06 2015 -0600 northbridge/amd/amdht: Allow mainboards to set HT frequency limit This is useful when the PCB layout of a mainboard does not allow stable operation at the increased HyperTransport speeds of newer processors. Change-Id: Idc93a1294608178ddf38ca72d40e6bad7deb9004 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/amdfam10.h | 7 +++++ src/northbridge/amd/amdht/h3finit.c | 52 +++++++++++++++++++++++++++++++-- src/northbridge/amd/amdht/h3finit.h | 3 ++ src/northbridge/amd/amdht/ht_wrapper.c | 3 +- 4 files changed, 61 insertions(+), 4 deletions(-) diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index ab4b42e..af9e24e 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -1033,6 +1034,10 @@ struct nodes_info_t { u32 up_planes; // down planes will be [up_planes, planes) } __attribute__((packed)); +struct ht_link_config { + uint8_t ht_speed_limit; // Speed in MHz; 0 for autodetect (default) +}; + /* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and ramstage stage. and ramstage may be running at 64bit later.*/ #if !CONFIG_AMDMCT @@ -1053,6 +1058,8 @@ struct sys_info { u8 host_link_freq[NODE_NUMS*8]; // record freq for every link from cpu, 0x0f means don't need to touch it u16 host_link_freq_cap[NODE_NUMS*8]; //cap + struct ht_link_config ht_link_cfg; + u32 segbit; u32 sbdn; u32 sblk; diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 4059182..eab99c7 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -75,6 +75,53 @@ static const uint16_t ht_speed_limit[16] = 0x00FF, 0x007F, 0x003F, 0x001F, 0x000F, 0x0007, 0x0003, 0x0001}; +/* WARNING + * The coding style made this hard to read; + * if you need to modify it make absolutely sure + * the case MHz lines up with the appropriate + * return value! + */ +static const uint16_t ht_speed_mhz_to_hw(uint16_t mhz) +{ + switch(mhz) { + case 200: + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_200]; + case 300: + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_300]; + case 400: + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_400]; + case 500: + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_500]; + case 600: + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_600]; + case 800: + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_800]; + case 1000: + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_1000]; + case 1200: + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_1200]; + case 1400: + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_1400]; + case 1600: + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_1600]; + case 1800: + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_1800]; + case 2000: + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_2000]; + case 2200: + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_2200]; + case 2400: + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_2400]; + case 2600: + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_2600]; + case 0: + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_AUTO]; + default: + printk(BIOS_WARNING, "WARNING: Invalid HT link limit frequency %d specified, ignoring...\n", mhz); + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_AUTO]; + } +} + /*---------------------------------------------------------------------------- * TYPEDEFS AND STRUCTURES * @@ -1359,10 +1406,9 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat) for (i = 0; i < pDat->TotalLinks*2; i += 2) { - /* FIXME - * Mainboards need to be able to set cbPCBFreqLimit - */ cbPCBFreqLimit = 0xFFFF; // Maximum allowed by autoconfiguration + if (pDat->HtBlock->ht_link_configuration) + cbPCBFreqLimit = ht_speed_mhz_to_hw(pDat->HtBlock->ht_link_configuration->ht_speed_limit); cbPCBFreqLimit = min(cbPCBFreqLimit, cbPCBFreqLimit_NVRAM); #if CONFIG_EXPERT && CONFIG_LIMIT_HT_DOWN_WIDTH_8 diff --git a/src/northbridge/amd/amdht/h3finit.h b/src/northbridge/amd/amdht/h3finit.h index 136a5cf..a56c246 100644 --- a/src/northbridge/amd/amdht/h3finit.h +++ b/src/northbridge/amd/amdht/h3finit.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -462,6 +463,8 @@ typedef struct { const u8 *pEventData0 ); + const struct ht_link_config *ht_link_configuration; + } AMD_HTBLOCK; /* diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 3bf81c6..a38caa4 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -139,7 +139,8 @@ static void amd_ht_init(struct sys_info *sysinfo) NULL, // BOOL (*AMD_CB_CustomizeBuffers)(); NULL, // void (*AMD_CB_OverrideDevicePort)(); NULL, // void (*AMD_CB_OverrideCpuPort)(); - AMD_CB_EventNotify // void (*AMD_CB_EventNotify) (); + AMD_CB_EventNotify, // void (*AMD_CB_EventNotify) (); + &sysinfo->ht_link_cfg // struct ht_link_config* }; printk(BIOS_DEBUG, "Enter amd_ht_init()\n");

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Patch set updated for coreboot: 7ae4c3f Add stage information to coreboot banner
by Stefan Reinauer 04 Mar '15

04 Mar '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8578 -gerrit commit 7ae4c3f43871bad2edf2150a28c19f68d60a83cb Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Mar 4 01:11:18 2015 +0100 Add stage information to coreboot banner As a convenience, print the actual stage name when entering a stage. Also unify the banner between bootblock / romstage and ramstage. No reason for two different occurences. Instead of this: coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 booting... you will see this: coreboot-4.0 Tue May 13 14:13:37 PDT 2014 bootblock starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 romstage starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 ramstage starting... Roughly based on: https://chromium-review.googlesource.com/199671 Change-Id: Id5894535e0551d113c80e4ff0514287391be1bef Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/arch/x86/lib/romcc_console.c | 2 +- src/console/init.c | 12 +++++++++--- src/lib/hardwaremain.c | 5 ----- 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index a6424dd..1f28097 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -73,7 +73,7 @@ void console_init(void) COREBOOT_EXTRA_VERSION " " COREBOOT_BUILD - " starting...\n"; + " romstage starting...\n"; console_hw_init(); diff --git a/src/console/init.c b/src/console/init.c index 3dbf014..e638216 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -47,8 +47,14 @@ void console_init(void) console_hw_init(); -#if defined(__PRE_RAM__) - printk(BIOS_INFO, "\n\ncoreboot-%s%s %s starting...\n", - coreboot_version, coreboot_extra_version, coreboot_build); + printk(BIOS_INFO, "\n\ncoreboot-%s%s %s %s starting...\n", + coreboot_version, coreboot_extra_version, coreboot_build, +#if defined(__BOOT_BLOCK__) + "bootblock" +#elif defined(__PRE_RAM__) + "romstage" +#else + "ramstage" #endif + ); } diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index d43ff46..32162eb 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -460,11 +460,6 @@ void main(void) post_code(POST_CONSOLE_READY); - printk(BIOS_NOTICE, "coreboot-%s%s %s booting...\n", - coreboot_version, coreboot_extra_version, coreboot_build); - - post_code(POST_CONSOLE_BOOT_MSG); - /* Handoff sleep type from romstage. */ #if CONFIG_HAVE_ACPI_RESUME acpi_is_wakeup();

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coreboot-gerrit March 2015