coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 859a044 Only update submodules if the source is in a git repo
by Martin Roth 04 Mar '15

04 Mar '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8427 -gerrit commit 859a044c262d3d1c222cbf125664235ad8cc08c8 Author: Martin Roth <gaumless(a)gmail.com> Date: Thu Feb 12 19:34:11 2015 -0700 Only update submodules if the source is in a git repo This change just adds a check to verify that the build is happening inside a git repo and that git is a valid command before trying to update the submodules. Change-Id: Idfa27645c3dbfd684f90002ecb01626d71eacc8f Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- Makefile.inc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index a60df87..b8ab4be 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -19,7 +19,7 @@ ####################################################################### # misleadingly named, this is the coreboot version -export KERNELVERSION := $(shell if [ -d "$(top)/.git" -a -f "`which git`" ]; \ +export KERNELVERSION := $(shell if [ -d "$(top)/.git" -a -f "$(command -v git)" ]; \ then git describe --dirty --always || git describe; \ else echo 4.0$(KERNELREVISION); fi) @@ -139,12 +139,14 @@ ifeq ($(CONFIG_COVERAGE),y) ramstage-c-ccopts+=-fprofile-arcs -ftest-coverage endif -# try to fetch non-optional submodules -forgetthis:=$(shell git submodule update --init) +# try to fetch non-optional submodules if the source is under git +forgetthis:=$(shell if [ -d "$(top)/.git" -a -f "$(command -v git)" ]; \ + then git submodule update --init; fi) ifeq ($(CONFIG_USE_BLOBS),y) # this is necessary because 3rdparty is update=none, and so is ignored # unless explicitly requested and enabled through --checkout -forgetthis:=$(shell git submodule update --init --checkout 3rdparty) +forgetthis:=$(shell if [ -d "$(top)/.git" -a -f "$(command -v git)" ]; \ + then git submodule update --init --checkout 3rdparty; fi) endif bootblock-c-ccopts:=-D__BOOT_BLOCK__ -D__PRE_RAM__

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Patch set updated for coreboot: dde0cd2 google/butterfly: Drop MRC.bin in favor of native raminit
by Alexandru Gagniuc 04 Mar '15

04 Mar '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8477 -gerrit commit dde0cd274236717e17e27f02c728e1e063baa28c Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Feb 15 14:09:21 2015 -0600 google/butterfly: Drop MRC.bin in favor of native raminit I thought this wasn't going to work, and observing the timC detection failure of early tests, I was getting somewhat discouraged; however, this works. I've tried it with all possible permutations of the following memory modules: * 2 GiB single-rank DDR3-1600 * 4 GiB single-rank DDR3-1600 * 4 GiB dual-rank DDR3-1600 I did notice a limited number of memtest errors during one of the runs, but they were in an address range that is otherwise marked as reserved. I wrote that off as "maybe something was doing MMIO there just when memtest was poking the address range". I was not able to reproduce that error. Change-Id: Ibd52e1d52fc8d900591d6a488f9a5b4d1e5e4fd3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/google/butterfly/Kconfig | 2 +- src/mainboard/google/butterfly/Makefile.inc | 1 + src/mainboard/google/butterfly/devicetree.cb | 2 + src/mainboard/google/butterfly/gpio.c | 300 ++++++++++++++++++++++++++ src/mainboard/google/butterfly/gpio.h | 304 --------------------------- src/mainboard/google/butterfly/romstage.c | 159 +++----------- 6 files changed, 328 insertions(+), 440 deletions(-) diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index df7460a..811a9fe 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE select SOUTHBRIDGE_INTEL_C216 select EC_QUANTA_ENE_KB3940Q select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index f735e9c..456528e 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -21,5 +21,6 @@ ramstage-y += ec.c romstage-y += chromeos.c ramstage-y += chromeos.c +romstage-y += gpio.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index ed0d8d1..90925b9 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -12,6 +12,8 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms + register "max_mem_clock_mhz" = "666" # DDR3-1333 + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end diff --git a/src/mainboard/google/butterfly/gpio.c b/src/mainboard/google/butterfly/gpio.c new file mode 100644 index 0000000..5d997c7 --- /dev/null +++ b/src/mainboard/google/butterfly/gpio.c @@ -0,0 +1,300 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "southbridge/intel/bd82x6x/gpio.h" + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NONE, /* Unused */ + .gpio1 = GPIO_MODE_NONE, /* Unused */ + .gpio2 = GPIO_MODE_NONE, /* Unused */ + .gpio3 = GPIO_MODE_NONE, /* Unused */ + .gpio4 = GPIO_MODE_NATIVE, /* Native - TPSINT# for TP SMBus IRQ */ + .gpio5 = GPIO_MODE_NONE, /* Unused */ + .gpio6 = GPIO_MODE_GPIO, /* Input - BOARD_ID4 */ + .gpio7 = GPIO_MODE_GPIO, /* Input - BOARD_ID5 */ + .gpio8 = GPIO_MODE_GPIO, /* Output - BT on/off */ + .gpio9 = GPIO_MODE_NONE, /* Unused */ + .gpio10 = GPIO_MODE_NONE, /* Unused */ + .gpio11 = GPIO_MODE_GPIO, /* Input - TP WAKEUP Event */ + .gpio12 = GPIO_MODE_NONE, /* Unused */ + .gpio13 = GPIO_MODE_GPIO, /* Input - SCI from EC */ + .gpio14 = GPIO_MODE_GPIO, /* Output - AOAC WLAN power control */ + .gpio15 = GPIO_MODE_GPIO, /* Unused - Do not control WLAN*/ + .gpio16 = GPIO_MODE_NONE, /* Unused */ + .gpio17 = GPIO_MODE_GPIO, /* Input - DGPU_PWROK */ + .gpio18 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ1# LAN clock pin*/ + .gpio19 = GPIO_MODE_GPIO, /* Input - Boot BIOS Selection 0 */ + .gpio20 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ2# SDCard clock pin */ + .gpio21 = GPIO_MODE_GPIO, /* Input - EC_ENTERING_RW for Google OS */ + .gpio22 = GPIO_MODE_GPIO, /* Input - BIOS RECOVERY */ + .gpio23 = GPIO_MODE_NONE, /* Unused */ + .gpio24 = GPIO_MODE_GPIO, /* Output - DGPU_HOLD_RST# */ + .gpio25 = GPIO_MODE_NONE, /* Unused */ + .gpio26 = GPIO_MODE_NONE, /* Unused */ + .gpio27 = GPIO_MODE_NONE, /* Unused */ + .gpio28 = GPIO_MODE_NONE, /* Unused */ + .gpio29 = GPIO_MODE_NONE, /* Unused */ + .gpio30 = GPIO_MODE_NATIVE, /* Native - SUSWARN_EC# */ + .gpio31 = GPIO_MODE_NONE, /* Unused */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, /* Unused */ + .gpio1 = GPIO_DIR_INPUT, /* Unused */ + .gpio2 = GPIO_DIR_INPUT, /* Unused */ + .gpio3 = GPIO_DIR_INPUT, /* Unused */ + .gpio4 = GPIO_DIR_INPUT, /* Native */ + .gpio5 = GPIO_DIR_INPUT, /* Unused */ + .gpio6 = GPIO_DIR_INPUT, /* Input */ + .gpio7 = GPIO_DIR_INPUT, /* Input */ + .gpio8 = GPIO_DIR_INPUT, /* Output HIGH - set in mainboard.c */ + .gpio9 = GPIO_DIR_INPUT, /* Unused */ + .gpio10 = GPIO_DIR_INPUT, /* Unused */ + .gpio11 = GPIO_DIR_INPUT, /* Input */ + .gpio12 = GPIO_DIR_INPUT, /* Unused */ + .gpio13 = GPIO_DIR_INPUT, /* Input */ + .gpio14 = GPIO_DIR_OUTPUT, /* Output HIGH */ + .gpio15 = GPIO_DIR_INPUT, /* Unused */ + .gpio16 = GPIO_DIR_INPUT, /* Unused */ + .gpio17 = GPIO_DIR_INPUT, /* Input */ + .gpio18 = GPIO_DIR_INPUT, /* Native */ + .gpio19 = GPIO_DIR_INPUT, /* Input */ + .gpio20 = GPIO_DIR_INPUT, /* Native */ + .gpio21 = GPIO_DIR_INPUT, /* Input */ + .gpio22 = GPIO_DIR_INPUT, /* Input */ + .gpio23 = GPIO_DIR_INPUT, /* Unused */ + .gpio24 = GPIO_DIR_OUTPUT, /* Output HIGH */ + .gpio25 = GPIO_DIR_INPUT, /* Unused */ + .gpio26 = GPIO_DIR_INPUT, /* Unused */ + .gpio27 = GPIO_DIR_INPUT, /* Unused */ + .gpio28 = GPIO_DIR_INPUT, /* Unused */ + .gpio29 = GPIO_DIR_INPUT, /* Unused */ + .gpio30 = GPIO_DIR_INPUT, /* Native */ + .gpio31 = GPIO_DIR_INPUT, /* Unused */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, /* Unused */ + .gpio1 = GPIO_LEVEL_LOW, /* Unused */ + .gpio2 = GPIO_LEVEL_LOW, /* Unused */ + .gpio3 = GPIO_LEVEL_LOW, /* Unused */ + .gpio4 = GPIO_LEVEL_LOW, /* Native */ + .gpio5 = GPIO_LEVEL_LOW, /* Unused */ + .gpio6 = GPIO_LEVEL_LOW, /* Input */ + .gpio7 = GPIO_LEVEL_LOW, /* Input */ + .gpio8 = GPIO_LEVEL_HIGH, /* Output HIGH - set in mainboard.c */ + .gpio9 = GPIO_LEVEL_LOW, /* Unused */ + .gpio10 = GPIO_LEVEL_LOW, /* Unused */ + .gpio11 = GPIO_LEVEL_LOW, /* Input */ + .gpio12 = GPIO_LEVEL_LOW, /* Unused */ + .gpio13 = GPIO_LEVEL_LOW, /* Input */ + .gpio14 = GPIO_LEVEL_HIGH, /* Output HIGH */ + .gpio15 = GPIO_LEVEL_HIGH, /* Unused */ + .gpio16 = GPIO_LEVEL_LOW, /* Unused */ + .gpio17 = GPIO_LEVEL_LOW, /* Input */ + .gpio18 = GPIO_LEVEL_LOW, /* Native */ + .gpio19 = GPIO_LEVEL_LOW, /* Input */ + .gpio20 = GPIO_LEVEL_LOW, /* Native */ + .gpio21 = GPIO_LEVEL_LOW, /* Input */ + .gpio22 = GPIO_LEVEL_LOW, /* Input */ + .gpio23 = GPIO_LEVEL_LOW, /* Unused */ + .gpio24 = GPIO_LEVEL_HIGH, /* Output HIGH */ + .gpio25 = GPIO_LEVEL_LOW, /* Unused */ + .gpio26 = GPIO_LEVEL_LOW, /* Unused */ + .gpio27 = GPIO_LEVEL_LOW, /* Unused */ + .gpio28 = GPIO_LEVEL_LOW, /* Unused */ + .gpio29 = GPIO_LEVEL_LOW, /* Unused */ + .gpio30 = GPIO_LEVEL_LOW, /* Native */ + .gpio31 = GPIO_LEVEL_LOW, /* Unused */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio11 = GPIO_INVERT, /* invert touchpad wakeup pin */ + .gpio13 = GPIO_INVERT, /* invert EC SCI pin */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, /* Native - Connect to EC Clock Run */ + .gpio33 = GPIO_MODE_GPIO, /* Input - (Google protect BIOS ROM) */ + .gpio34 = GPIO_MODE_NONE, /* Unused */ + .gpio35 = GPIO_MODE_NONE, /* Unused */ + .gpio36 = GPIO_MODE_GPIO, /* Output - DGPU_PWR_EN */ + .gpio37 = GPIO_MODE_GPIO, /* Input - FDI TERM / VOLTAGE OVERRIDE */ + .gpio38 = GPIO_MODE_GPIO, /* Input - MFG_MODE test */ + .gpio39 = GPIO_MODE_GPIO, /* Input - DGPU_PRSNT */ + .gpio40 = GPIO_MODE_NONE, /* Unused */ + .gpio41 = GPIO_MODE_NONE, /* Unused */ + .gpio42 = GPIO_MODE_NONE, /* Unused */ + .gpio43 = GPIO_MODE_NONE, /* Unused */ + .gpio44 = GPIO_MODE_GPIO, /* Input - BOARD_ID0 */ + .gpio45 = GPIO_MODE_GPIO, /* Input - BOARD_ID1 */ + .gpio46 = GPIO_MODE_GPIO, /* Input - BOARD_ID2 */ + .gpio47 = GPIO_MODE_NATIVE, /* Native - PEGA_GPU clock request */ + .gpio48 = GPIO_MODE_NONE, /* Unused */ + .gpio49 = GPIO_MODE_NONE, /* Unused */ + .gpio50 = GPIO_MODE_NONE, /* Unused */ + .gpio51 = GPIO_MODE_GPIO, /* Input - Boot BIOS Selection 1 */ + .gpio52 = GPIO_MODE_GPIO, /* Input - Google recovery, Pull up +3V */ + .gpio53 = GPIO_MODE_GPIO, /* Output - G Sensor LED */ + .gpio54 = GPIO_MODE_GPIO, /* Input - Google Development */ + .gpio55 = GPIO_MODE_GPIO, /* Input - Top-Block Swap Override */ + .gpio56 = GPIO_MODE_NONE, /* Unused */ + .gpio57 = GPIO_MODE_GPIO, /* Input - SV_DET */ + .gpio58 = GPIO_MODE_NONE, /* Unused */ + .gpio59 = GPIO_MODE_NONE, /* Unused */ + .gpio60 = GPIO_MODE_NONE, /* GPO - DRAMRST_CNTRL_PCH */ + .gpio61 = GPIO_MODE_NONE, /* Unused */ + .gpio62 = GPIO_MODE_NATIVE, /* Native - Connect to EC 32.768KHz */ + .gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5 */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, /* Native */ + .gpio33 = GPIO_DIR_INPUT, /* Input */ + .gpio34 = GPIO_DIR_INPUT, /* Unused */ + .gpio35 = GPIO_DIR_INPUT, /* Unused */ + .gpio36 = GPIO_DIR_OUTPUT, /* Output HIGH */ + .gpio37 = GPIO_DIR_INPUT, /* Input */ + .gpio38 = GPIO_DIR_INPUT, /* Input */ + .gpio39 = GPIO_DIR_INPUT, /* Input */ + .gpio40 = GPIO_DIR_INPUT, /* Unused */ + .gpio41 = GPIO_DIR_INPUT, /* Unused */ + .gpio42 = GPIO_DIR_INPUT, /* Unused */ + .gpio43 = GPIO_DIR_INPUT, /* Unused */ + .gpio44 = GPIO_DIR_INPUT, /* Input */ + .gpio45 = GPIO_DIR_INPUT, /* Input */ + .gpio46 = GPIO_DIR_INPUT, /* Input */ + .gpio47 = GPIO_DIR_INPUT, /* Native */ + .gpio48 = GPIO_DIR_INPUT, /* Unused */ + .gpio49 = GPIO_DIR_INPUT, /* Unused */ + .gpio50 = GPIO_DIR_INPUT, /* Unused */ + .gpio51 = GPIO_DIR_INPUT, /* Input */ + .gpio52 = GPIO_DIR_INPUT, /* Input */ + .gpio53 = GPIO_DIR_OUTPUT, /* Input */ + .gpio54 = GPIO_DIR_INPUT, /* Input */ + .gpio55 = GPIO_DIR_INPUT, /* Input */ + .gpio56 = GPIO_DIR_INPUT, /* Unused */ + .gpio57 = GPIO_DIR_INPUT, /* Input */ + .gpio58 = GPIO_DIR_INPUT, /* Unused */ + .gpio59 = GPIO_DIR_INPUT, /* Unused */ + .gpio60 = GPIO_DIR_OUTPUT, /* Output HIGH */ + .gpio61 = GPIO_DIR_INPUT, /* Unused */ + .gpio62 = GPIO_DIR_INPUT, /* Native */ + .gpio63 = GPIO_DIR_INPUT, /* Native */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, /* Native */ + .gpio33 = GPIO_LEVEL_LOW, /* Input */ + .gpio34 = GPIO_LEVEL_LOW, /* Unused */ + .gpio35 = GPIO_LEVEL_LOW, /* Unused */ + .gpio36 = GPIO_LEVEL_HIGH, /* Output HIGH */ + .gpio37 = GPIO_LEVEL_LOW, /* Input */ + .gpio38 = GPIO_LEVEL_LOW, /* Input */ + .gpio39 = GPIO_LEVEL_LOW, /* Input */ + .gpio40 = GPIO_LEVEL_LOW, /* Unused */ + .gpio41 = GPIO_LEVEL_LOW, /* Unused */ + .gpio42 = GPIO_LEVEL_LOW, /* Unused */ + .gpio43 = GPIO_LEVEL_LOW, /* Unused */ + .gpio44 = GPIO_LEVEL_LOW, /* Input */ + .gpio45 = GPIO_LEVEL_LOW, /* Input */ + .gpio46 = GPIO_LEVEL_LOW, /* Input */ + .gpio47 = GPIO_LEVEL_LOW, /* Native */ + .gpio48 = GPIO_LEVEL_LOW, /* Unused */ + .gpio49 = GPIO_LEVEL_LOW, /* Unused */ + .gpio50 = GPIO_LEVEL_LOW, /* Unused */ + .gpio51 = GPIO_LEVEL_LOW, /* Input */ + .gpio52 = GPIO_LEVEL_LOW, /* Input */ + .gpio53 = GPIO_LEVEL_HIGH, /* Input */ + .gpio54 = GPIO_LEVEL_LOW, /* Input */ + .gpio55 = GPIO_LEVEL_LOW, /* Input */ + .gpio56 = GPIO_LEVEL_LOW, /* Unused */ + .gpio57 = GPIO_LEVEL_LOW, /* Input */ + .gpio58 = GPIO_LEVEL_LOW, /* Unused */ + .gpio59 = GPIO_LEVEL_LOW, /* Unused */ + .gpio60 = GPIO_LEVEL_HIGH, /* Output HIGH */ + .gpio61 = GPIO_LEVEL_LOW, /* Unused */ + .gpio62 = GPIO_LEVEL_LOW, /* Native */ + .gpio63 = GPIO_LEVEL_LOW, /* Native */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NONE, /* Unused */ + .gpio65 = GPIO_MODE_NONE, /* Unused */ + .gpio66 = GPIO_MODE_NONE, /* Unused */ + .gpio67 = GPIO_MODE_NONE, /* Unused */ + .gpio68 = GPIO_MODE_GPIO, /* Input - DGPU_PWR_EN */ + .gpio69 = GPIO_MODE_NONE, /* Unused */ + .gpio70 = GPIO_MODE_NONE, /* Unused */ + .gpio71 = GPIO_MODE_NONE, /* Unused */ + .gpio72 = GPIO_MODE_NONE, /* Unused */ + .gpio73 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ0# WLAN clock request */ + .gpio74 = GPIO_MODE_NONE, /* Unused */ + .gpio75 = GPIO_MODE_GPIO, /* Input - SMB_ME1_DAT */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, /* Unused */ + .gpio65 = GPIO_DIR_INPUT, /* Unused */ + .gpio66 = GPIO_DIR_INPUT, /* Unused */ + .gpio67 = GPIO_DIR_INPUT, /* Unused */ + .gpio68 = GPIO_DIR_INPUT, /* Input */ + .gpio69 = GPIO_DIR_INPUT, /* Unused */ + .gpio70 = GPIO_DIR_INPUT, /* Unused */ + .gpio71 = GPIO_DIR_INPUT, /* Unused */ + .gpio72 = GPIO_DIR_INPUT, /* Unused */ + .gpio73 = GPIO_DIR_INPUT, /* Native */ + .gpio74 = GPIO_DIR_INPUT, /* Unused */ + .gpio75 = GPIO_DIR_INPUT, /* Input */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, /* Unused */ + .gpio65 = GPIO_LEVEL_LOW, /* Unused */ + .gpio66 = GPIO_LEVEL_LOW, /* Unused */ + .gpio67 = GPIO_LEVEL_LOW, /* Unused */ + .gpio68 = GPIO_LEVEL_LOW, /* Input */ + .gpio69 = GPIO_LEVEL_LOW, /* Unused */ + .gpio70 = GPIO_LEVEL_LOW, /* Unused */ + .gpio71 = GPIO_LEVEL_LOW, /* Unused */ + .gpio72 = GPIO_LEVEL_LOW, /* Unused */ + .gpio73 = GPIO_LEVEL_LOW, /* Native */ + .gpio74 = GPIO_LEVEL_LOW, /* Unused */ + .gpio75 = GPIO_LEVEL_LOW, /* Input */ +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; diff --git a/src/mainboard/google/butterfly/gpio.h b/src/mainboard/google/butterfly/gpio.h deleted file mode 100644 index b592e6a..0000000 --- a/src/mainboard/google/butterfly/gpio.h +++ /dev/null @@ -1,304 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef BUTTERFLY_GPIO_H -#define BUTTERFLY_GPIO_H - -#include "southbridge/intel/bd82x6x/gpio.h" - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_NONE, /* Unused */ - .gpio1 = GPIO_MODE_NONE, /* Unused */ - .gpio2 = GPIO_MODE_NONE, /* Unused */ - .gpio3 = GPIO_MODE_NONE, /* Unused */ - .gpio4 = GPIO_MODE_NATIVE, /* Native - TPSINT# for TP SMBus IRQ */ - .gpio5 = GPIO_MODE_NONE, /* Unused */ - .gpio6 = GPIO_MODE_GPIO, /* Input - BOARD_ID4 */ - .gpio7 = GPIO_MODE_GPIO, /* Input - BOARD_ID5 */ - .gpio8 = GPIO_MODE_GPIO, /* Output - BT on/off */ - .gpio9 = GPIO_MODE_NONE, /* Unused */ - .gpio10 = GPIO_MODE_NONE, /* Unused */ - .gpio11 = GPIO_MODE_GPIO, /* Input - TP WAKEUP Event */ - .gpio12 = GPIO_MODE_NONE, /* Unused */ - .gpio13 = GPIO_MODE_GPIO, /* Input - SCI from EC */ - .gpio14 = GPIO_MODE_GPIO, /* Output - AOAC WLAN power control */ - .gpio15 = GPIO_MODE_GPIO, /* Unused - Do not control WLAN*/ - .gpio16 = GPIO_MODE_NONE, /* Unused */ - .gpio17 = GPIO_MODE_GPIO, /* Input - DGPU_PWROK */ - .gpio18 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ1# LAN clock pin*/ - .gpio19 = GPIO_MODE_GPIO, /* Input - Boot BIOS Selection 0 */ - .gpio20 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ2# SDCard clock pin */ - .gpio21 = GPIO_MODE_GPIO, /* Input - EC_ENTERING_RW for Google OS */ - .gpio22 = GPIO_MODE_GPIO, /* Input - BIOS RECOVERY */ - .gpio23 = GPIO_MODE_NONE, /* Unused */ - .gpio24 = GPIO_MODE_GPIO, /* Output - DGPU_HOLD_RST# */ - .gpio25 = GPIO_MODE_NONE, /* Unused */ - .gpio26 = GPIO_MODE_NONE, /* Unused */ - .gpio27 = GPIO_MODE_NONE, /* Unused */ - .gpio28 = GPIO_MODE_NONE, /* Unused */ - .gpio29 = GPIO_MODE_NONE, /* Unused */ - .gpio30 = GPIO_MODE_NATIVE, /* Native - SUSWARN_EC# */ - .gpio31 = GPIO_MODE_NONE, /* Unused */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, /* Unused */ - .gpio1 = GPIO_DIR_INPUT, /* Unused */ - .gpio2 = GPIO_DIR_INPUT, /* Unused */ - .gpio3 = GPIO_DIR_INPUT, /* Unused */ - .gpio4 = GPIO_DIR_INPUT, /* Native */ - .gpio5 = GPIO_DIR_INPUT, /* Unused */ - .gpio6 = GPIO_DIR_INPUT, /* Input */ - .gpio7 = GPIO_DIR_INPUT, /* Input */ - .gpio8 = GPIO_DIR_INPUT, /* Output HIGH - set in mainboard.c */ - .gpio9 = GPIO_DIR_INPUT, /* Unused */ - .gpio10 = GPIO_DIR_INPUT, /* Unused */ - .gpio11 = GPIO_DIR_INPUT, /* Input */ - .gpio12 = GPIO_DIR_INPUT, /* Unused */ - .gpio13 = GPIO_DIR_INPUT, /* Input */ - .gpio14 = GPIO_DIR_OUTPUT, /* Output HIGH */ - .gpio15 = GPIO_DIR_INPUT, /* Unused */ - .gpio16 = GPIO_DIR_INPUT, /* Unused */ - .gpio17 = GPIO_DIR_INPUT, /* Input */ - .gpio18 = GPIO_DIR_INPUT, /* Native */ - .gpio19 = GPIO_DIR_INPUT, /* Input */ - .gpio20 = GPIO_DIR_INPUT, /* Native */ - .gpio21 = GPIO_DIR_INPUT, /* Input */ - .gpio22 = GPIO_DIR_INPUT, /* Input */ - .gpio23 = GPIO_DIR_INPUT, /* Unused */ - .gpio24 = GPIO_DIR_OUTPUT, /* Output HIGH */ - .gpio25 = GPIO_DIR_INPUT, /* Unused */ - .gpio26 = GPIO_DIR_INPUT, /* Unused */ - .gpio27 = GPIO_DIR_INPUT, /* Unused */ - .gpio28 = GPIO_DIR_INPUT, /* Unused */ - .gpio29 = GPIO_DIR_INPUT, /* Unused */ - .gpio30 = GPIO_DIR_INPUT, /* Native */ - .gpio31 = GPIO_DIR_INPUT, /* Unused */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_LOW, /* Unused */ - .gpio1 = GPIO_LEVEL_LOW, /* Unused */ - .gpio2 = GPIO_LEVEL_LOW, /* Unused */ - .gpio3 = GPIO_LEVEL_LOW, /* Unused */ - .gpio4 = GPIO_LEVEL_LOW, /* Native */ - .gpio5 = GPIO_LEVEL_LOW, /* Unused */ - .gpio6 = GPIO_LEVEL_LOW, /* Input */ - .gpio7 = GPIO_LEVEL_LOW, /* Input */ - .gpio8 = GPIO_LEVEL_HIGH, /* Output HIGH - set in mainboard.c */ - .gpio9 = GPIO_LEVEL_LOW, /* Unused */ - .gpio10 = GPIO_LEVEL_LOW, /* Unused */ - .gpio11 = GPIO_LEVEL_LOW, /* Input */ - .gpio12 = GPIO_LEVEL_LOW, /* Unused */ - .gpio13 = GPIO_LEVEL_LOW, /* Input */ - .gpio14 = GPIO_LEVEL_HIGH, /* Output HIGH */ - .gpio15 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio16 = GPIO_LEVEL_LOW, /* Unused */ - .gpio17 = GPIO_LEVEL_LOW, /* Input */ - .gpio18 = GPIO_LEVEL_LOW, /* Native */ - .gpio19 = GPIO_LEVEL_LOW, /* Input */ - .gpio20 = GPIO_LEVEL_LOW, /* Native */ - .gpio21 = GPIO_LEVEL_LOW, /* Input */ - .gpio22 = GPIO_LEVEL_LOW, /* Input */ - .gpio23 = GPIO_LEVEL_LOW, /* Unused */ - .gpio24 = GPIO_LEVEL_HIGH, /* Output HIGH */ - .gpio25 = GPIO_LEVEL_LOW, /* Unused */ - .gpio26 = GPIO_LEVEL_LOW, /* Unused */ - .gpio27 = GPIO_LEVEL_LOW, /* Unused */ - .gpio28 = GPIO_LEVEL_LOW, /* Unused */ - .gpio29 = GPIO_LEVEL_LOW, /* Unused */ - .gpio30 = GPIO_LEVEL_LOW, /* Native */ - .gpio31 = GPIO_LEVEL_LOW, /* Unused */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio11 = GPIO_INVERT, /* invert touchpad wakeup pin */ - .gpio13 = GPIO_INVERT, /* invert EC SCI pin */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, /* Native - Connect to EC Clock Run */ - .gpio33 = GPIO_MODE_GPIO, /* Input - (Google protect BIOS ROM) */ - .gpio34 = GPIO_MODE_NONE, /* Unused */ - .gpio35 = GPIO_MODE_NONE, /* Unused */ - .gpio36 = GPIO_MODE_GPIO, /* Output - DGPU_PWR_EN */ - .gpio37 = GPIO_MODE_GPIO, /* Input - FDI TERM / VOLTAGE OVERRIDE */ - .gpio38 = GPIO_MODE_GPIO, /* Input - MFG_MODE test */ - .gpio39 = GPIO_MODE_GPIO, /* Input - DGPU_PRSNT */ - .gpio40 = GPIO_MODE_NONE, /* Unused */ - .gpio41 = GPIO_MODE_NONE, /* Unused */ - .gpio42 = GPIO_MODE_NONE, /* Unused */ - .gpio43 = GPIO_MODE_NONE, /* Unused */ - .gpio44 = GPIO_MODE_GPIO, /* Input - BOARD_ID0 */ - .gpio45 = GPIO_MODE_GPIO, /* Input - BOARD_ID1 */ - .gpio46 = GPIO_MODE_GPIO, /* Input - BOARD_ID2 */ - .gpio47 = GPIO_MODE_NATIVE, /* Native - PEGA_GPU clock request */ - .gpio48 = GPIO_MODE_NONE, /* Unused */ - .gpio49 = GPIO_MODE_NONE, /* Unused */ - .gpio50 = GPIO_MODE_NONE, /* Unused */ - .gpio51 = GPIO_MODE_GPIO, /* Input - Boot BIOS Selection 1 */ - .gpio52 = GPIO_MODE_GPIO, /* Input - Google recovery, Pull up +3V */ - .gpio53 = GPIO_MODE_GPIO, /* Output - G Sensor LED */ - .gpio54 = GPIO_MODE_GPIO, /* Input - Google Development */ - .gpio55 = GPIO_MODE_GPIO, /* Input - Top-Block Swap Override */ - .gpio56 = GPIO_MODE_NONE, /* Unused */ - .gpio57 = GPIO_MODE_GPIO, /* Input - SV_DET */ - .gpio58 = GPIO_MODE_NONE, /* Unused */ - .gpio59 = GPIO_MODE_NONE, /* Unused */ - .gpio60 = GPIO_MODE_NONE, /* GPO - DRAMRST_CNTRL_PCH */ - .gpio61 = GPIO_MODE_NONE, /* Unused */ - .gpio62 = GPIO_MODE_NATIVE, /* Native - Connect to EC 32.768KHz */ - .gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5 */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_INPUT, /* Native */ - .gpio33 = GPIO_DIR_INPUT, /* Input */ - .gpio34 = GPIO_DIR_INPUT, /* Unused */ - .gpio35 = GPIO_DIR_INPUT, /* Unused */ - .gpio36 = GPIO_DIR_OUTPUT, /* Output HIGH */ - .gpio37 = GPIO_DIR_INPUT, /* Input */ - .gpio38 = GPIO_DIR_INPUT, /* Input */ - .gpio39 = GPIO_DIR_INPUT, /* Input */ - .gpio40 = GPIO_DIR_INPUT, /* Unused */ - .gpio41 = GPIO_DIR_INPUT, /* Unused */ - .gpio42 = GPIO_DIR_INPUT, /* Unused */ - .gpio43 = GPIO_DIR_INPUT, /* Unused */ - .gpio44 = GPIO_DIR_INPUT, /* Input */ - .gpio45 = GPIO_DIR_INPUT, /* Input */ - .gpio46 = GPIO_DIR_INPUT, /* Input */ - .gpio47 = GPIO_DIR_INPUT, /* Native */ - .gpio48 = GPIO_DIR_INPUT, /* Unused */ - .gpio49 = GPIO_DIR_INPUT, /* Unused */ - .gpio50 = GPIO_DIR_INPUT, /* Unused */ - .gpio51 = GPIO_DIR_INPUT, /* Input */ - .gpio52 = GPIO_DIR_INPUT, /* Input */ - .gpio53 = GPIO_DIR_OUTPUT, /* Input */ - .gpio54 = GPIO_DIR_INPUT, /* Input */ - .gpio55 = GPIO_DIR_INPUT, /* Input */ - .gpio56 = GPIO_DIR_INPUT, /* Unused */ - .gpio57 = GPIO_DIR_INPUT, /* Input */ - .gpio58 = GPIO_DIR_INPUT, /* Unused */ - .gpio59 = GPIO_DIR_INPUT, /* Unused */ - .gpio60 = GPIO_DIR_OUTPUT, /* Output HIGH */ - .gpio61 = GPIO_DIR_INPUT, /* Unused */ - .gpio62 = GPIO_DIR_INPUT, /* Native */ - .gpio63 = GPIO_DIR_INPUT, /* Native */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_LOW, /* Native */ - .gpio33 = GPIO_LEVEL_LOW, /* Input */ - .gpio34 = GPIO_LEVEL_LOW, /* Unused */ - .gpio35 = GPIO_LEVEL_LOW, /* Unused */ - .gpio36 = GPIO_LEVEL_HIGH, /* Output HIGH */ - .gpio37 = GPIO_LEVEL_LOW, /* Input */ - .gpio38 = GPIO_LEVEL_LOW, /* Input */ - .gpio39 = GPIO_LEVEL_LOW, /* Input */ - .gpio40 = GPIO_LEVEL_LOW, /* Unused */ - .gpio41 = GPIO_LEVEL_LOW, /* Unused */ - .gpio42 = GPIO_LEVEL_LOW, /* Unused */ - .gpio43 = GPIO_LEVEL_LOW, /* Unused */ - .gpio44 = GPIO_LEVEL_LOW, /* Input */ - .gpio45 = GPIO_LEVEL_LOW, /* Input */ - .gpio46 = GPIO_LEVEL_LOW, /* Input */ - .gpio47 = GPIO_LEVEL_LOW, /* Native */ - .gpio48 = GPIO_LEVEL_LOW, /* Unused */ - .gpio49 = GPIO_LEVEL_LOW, /* Unused */ - .gpio50 = GPIO_LEVEL_LOW, /* Unused */ - .gpio51 = GPIO_LEVEL_LOW, /* Input */ - .gpio52 = GPIO_LEVEL_LOW, /* Input */ - .gpio53 = GPIO_LEVEL_HIGH, /* Input */ - .gpio54 = GPIO_LEVEL_LOW, /* Input */ - .gpio55 = GPIO_LEVEL_LOW, /* Input */ - .gpio56 = GPIO_LEVEL_LOW, /* Unused */ - .gpio57 = GPIO_LEVEL_LOW, /* Input */ - .gpio58 = GPIO_LEVEL_LOW, /* Unused */ - .gpio59 = GPIO_LEVEL_LOW, /* Unused */ - .gpio60 = GPIO_LEVEL_HIGH, /* Output HIGH */ - .gpio61 = GPIO_LEVEL_LOW, /* Unused */ - .gpio62 = GPIO_LEVEL_LOW, /* Native */ - .gpio63 = GPIO_LEVEL_LOW, /* Native */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_NONE, /* Unused */ - .gpio65 = GPIO_MODE_NONE, /* Unused */ - .gpio66 = GPIO_MODE_NONE, /* Unused */ - .gpio67 = GPIO_MODE_NONE, /* Unused */ - .gpio68 = GPIO_MODE_GPIO, /* Input - DGPU_PWR_EN */ - .gpio69 = GPIO_MODE_NONE, /* Unused */ - .gpio70 = GPIO_MODE_NONE, /* Unused */ - .gpio71 = GPIO_MODE_NONE, /* Unused */ - .gpio72 = GPIO_MODE_NONE, /* Unused */ - .gpio73 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ0# WLAN clock request */ - .gpio74 = GPIO_MODE_NONE, /* Unused */ - .gpio75 = GPIO_MODE_GPIO, /* Input - SMB_ME1_DAT */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_INPUT, /* Unused */ - .gpio65 = GPIO_DIR_INPUT, /* Unused */ - .gpio66 = GPIO_DIR_INPUT, /* Unused */ - .gpio67 = GPIO_DIR_INPUT, /* Unused */ - .gpio68 = GPIO_DIR_INPUT, /* Input */ - .gpio69 = GPIO_DIR_INPUT, /* Unused */ - .gpio70 = GPIO_DIR_INPUT, /* Unused */ - .gpio71 = GPIO_DIR_INPUT, /* Unused */ - .gpio72 = GPIO_DIR_INPUT, /* Unused */ - .gpio73 = GPIO_DIR_INPUT, /* Native */ - .gpio74 = GPIO_DIR_INPUT, /* Unused */ - .gpio75 = GPIO_DIR_INPUT, /* Input */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { - .gpio64 = GPIO_LEVEL_LOW, /* Unused */ - .gpio65 = GPIO_LEVEL_LOW, /* Unused */ - .gpio66 = GPIO_LEVEL_LOW, /* Unused */ - .gpio67 = GPIO_LEVEL_LOW, /* Unused */ - .gpio68 = GPIO_LEVEL_LOW, /* Input */ - .gpio69 = GPIO_LEVEL_LOW, /* Unused */ - .gpio70 = GPIO_LEVEL_LOW, /* Unused */ - .gpio71 = GPIO_LEVEL_LOW, /* Unused */ - .gpio72 = GPIO_LEVEL_LOW, /* Unused */ - .gpio73 = GPIO_LEVEL_LOW, /* Native */ - .gpio74 = GPIO_LEVEL_LOW, /* Unused */ - .gpio75 = GPIO_LEVEL_LOW, /* Input */ -}; - -const struct pch_gpio_map butterfly_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .invert = &pch_gpio_set1_invert, - - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; -#endif diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index b117295..7f9ab60 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -32,20 +32,18 @@ #include <cbmem.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> -#include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <halt.h> -#include "gpio.h" #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> #endif #include <cbfs.h> -static void pch_enable_lpc(void) +void pch_enable_lpc(void) { /* EC Decode Range Port60/64 and Port62/66 */ /* Enable EC and PS/2 Keyboard/Mouse*/ @@ -59,7 +57,7 @@ static void pch_enable_lpc(void) } -static void rcba_config(void) +void rcba_config(void) { u32 reg32; @@ -73,134 +71,25 @@ static void rcba_config(void) RCBA32(FD) = reg32; } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) -{ - int boot_mode = 0; - int cbmem_was_initted; - - struct pei_data pei_data = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .ddr3lv_support = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* enabled usb oc pin length */ - { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ - { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ - { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ - { 0, 0, 0x0000 }, /* P3: Empty */ - { 0, 0, 0x0000 }, /* P4: Empty */ - { 0, 0, 0x0000 }, /* P5: Empty */ - { 0, 0, 0x0000 }, /* P6: Empty */ - { 0, 0, 0x0000 }, /* P7: Empty */ - { 0, 4, 0x0000 }, /* P8: Empty */ - { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ - { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ - { 0, 4, 0x0000 }, /* P11: Empty */ - { 0, 4, 0x0000 }, /* P12: Empty */ - { 0, 4, 0x0000 }, /* P13: Empty */ - }, - .ddr_refresh_rate_config = 2, /* Force double refresh rate */ - }; - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (bist == 0) - enable_lapic(); - - pch_enable_lpc(); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - setup_pch_gpios(&butterfly_gpio_map); - - /* Initialize console device(s) */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected\n"); - boot_mode = 1; - - /* System is not happy after keyboard reset... */ - printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - sandybridge_early_initialization(SANDYBRIDGE_MOBILE); - printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - - boot_mode = southbridge_detect_s3_resume() ? 2 : 0; - - post_code(0x38); - /* Enable SPD ROMs and DDR-III DRAM */ - enable_smbus(); - - /* Prepare USB controller early in S3 resume */ - if (boot_mode == 2) - enable_usb_bar(); - - post_code(0x39); - - post_code(0x3a); - pei_data.boot_mode = boot_mode; - timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(&pei_data); - - timestamp_add_now(TS_AFTER_INITRAM); - post_code(0x3c); - - rcba_config(); - post_code(0x3d); - - quick_ram_check(); - post_code(0x3e); - - cbmem_was_initted = !cbmem_recovery(boot_mode==2); - if (boot_mode!=2) - save_mrc_data(&pei_data); - - if (boot_mode==2 && !cbmem_was_initted) { - /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); - } - northbridge_romstage_finalize(boot_mode==2); - - post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif - timestamp_add_now(TS_END_ROMSTAGE); +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled usb oc pin length */ + { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ + { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ + { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ + { 0, 0, 0x0000 }, /* P3: Empty */ + { 0, 0, 0x0000 }, /* P4: Empty */ + { 0, 0, 0x0000 }, /* P5: Empty */ + { 0, 0, 0x0000 }, /* P6: Empty */ + { 0, 0, 0x0000 }, /* P7: Empty */ + { 0, 4, 0x0000 }, /* P8: Empty */ + { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ + { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ + { 0, 4, 0x0000 }, /* P11: Empty */ + { 0, 4, 0x0000 }, /* P12: Empty */ + { 0, 4, 0x0000 }, /* P13: Empty */ +}; + +void mainboard_get_spd(spd_raw_data *spd) { + read_spd(&spd[0], 0x50); + read_spd(&spd[2], 0x52); }

1 0

Patch set updated for coreboot: ecb5a6b Move generation of build.h into a shell script
by Martin Roth 04 Mar '15

04 Mar '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8428 -gerrit commit ecb5a6baa0684a9d183639904f341a71f2d1086a Author: Martin Roth <gaumless(a)gmail.com> Date: Thu Feb 12 19:32:41 2015 -0700 Move generation of build.h into a shell script Moving the routines that create build.h into a script offers several advantages. We can create more complex functions to run and we don't have to deal with both bash and Make at the same time. This script combines what is currently in Makefile.inc with a couple of update. - Update how it determines whether to use git for the timestamp - Move the git revision string generation inside the routine that checks to see if we have git. - Add a timeout for the domain name check. Change-Id: I93c131e8d01a0099eb13db720fa865c627985750 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- Makefile.inc | 28 ++------------ util/genbuild_h/genbuild_h.sh | 87 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 90 insertions(+), 25 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index a60df87..f8bd813 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -272,31 +272,9 @@ additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \ $(obj)/build.h: .xcompile @printf " GEN build.h\n" rm -f $(obj)/build.h - printf "/* build system definitions (autogenerated) */\n" > $(obj)/build.ht - printf "#ifndef __BUILD_H\n" >> $(obj)/build.ht - printf "#define __BUILD_H\n\n" >> $(obj)/build.ht - printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" >> $(obj)/build.ht - if git update-index -q --refresh >/dev/null; ! git diff-index --quiet HEAD; then \ - printf "/* `LANG= TZ=UTC git log --date=local --pretty=format:%cd -1` UTC */\n" >> $(obj)/build.ht; \ - printf "#define COREBOOT_VERSION_TIMESTAMP `LANG= git log --pretty=format:%ct -1`\n" >> $(obj)/build.ht; \ - else \ - printf "/* `LANG= TZ=UTC date` */\n" >> $(obj)/build.ht; \ - printf "#define COREBOOT_VERSION_TIMESTAMP `LANG= date +%s`\n" >> $(obj)/build.ht; \ - fi - printf "#define COREBOOT_ORIGIN_GIT_REVISION \"`LANG= git log remotes/origin/master -1 --format=format:%h`\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_BUILD_YEAR_BCD 0x`LANG= date +"%y"`\n" >> $(obj)/build.ht - printf "#define COREBOOT_BUILD_MONTH_BCD 0x`LANG= date +"%m"`\n" >> $(obj)/build.ht - printf "#define COREBOOT_BUILD_DAY_BCD 0x`LANG= date +"%d"`\n" >> $(obj)/build.ht - printf "#define COREBOOT_BUILD_WEEKDAY_BCD 0x`LANG= date +"%w"`\n" >> $(obj)/build.ht - printf "#define COREBOOT_DMI_DATE \"`LANG= date +"%m/%d/%Y"`\"\n" >> $(obj)/build.ht - printf "\n" >> $(obj)/build.ht - printf "#define COREBOOT_COMPILE_TIME \"`LANG= date +%T`\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_COMPILE_BY \"$(subst \,@,$(shell PATH=$$PATH:/usr/ucb whoami))\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_COMPILE_HOST \"$(shell hostname -s 2>/dev/null || hostname 2>/dev/null)\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_COMPILE_DOMAIN \"$(shell test `uname -s` = "Linux" && dnsdomainname || domainname 2>/dev/null)\"\n" >> $(obj)/build.ht - printf "#endif\n" >> $(obj)/build.ht + export KERNELVERSION="$(KERNELVERSION)" + export COREBOOT_EXTRA_VERSION="$(COREBOOT_EXTRA_VERSION)" + util/genbuild_h/genbuild_h.sh > $(obj)/build.ht mv $(obj)/build.ht $(obj)/build.h $(obj)/ldoptions: $(obj)/config.h diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh new file mode 100755 index 0000000..6a7f65e --- /dev/null +++ b/util/genbuild_h/genbuild_h.sh @@ -0,0 +1,87 @@ +#!/bin/sh + +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Sage Electronic Engineering, LLC. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +#get the domain name without hanging the build for an extended period if +#the build system doesn't return a domain name as can happen with the +#dnsdomainname or domainname commands by themselves. +get_domainname() { + MAX_DELAY=1 #maximum time to wait in seconds + TIMEOUT_HOSTNAME_TEXT=unknown.domain #text to return if domain name is not found + TEMPFILE_NAME=coreboot_hostname.txt #temp file to put the domain name into + + # Find the domain name + if [ "$(uname -s)" = "Linux" ] + then + dnsdomainname 2>/dev/null > "$TEMPFILE_NAME" & + else + domainname 2>/dev/null >"$TEMPFILE_NAME" & + fi + + # Get ready to kill the process if it's taking too long + PID=$! + sleep "$MAX_DELAY" && kill "$PID" 2>/dev/null & + wait "$PID" 2>/dev/null + + # See what was found, print our timeout text if the process was killed + # or the domain name if we found one. + HN=$(cat "$TEMPFILE_NAME") + if [ "$HN" = "" ] + then + printf "%s" "$TIMEOUT_HOSTNAME_TEXT" + else + printf "%s" "$HN" + fi + + # Clean up and exit. + rm -f "$TEMPFILE_NAME" +} + +#Print out the information that goes into build.h +printf "/* build system definitions (autogenerated) */\n" +printf "#ifndef __BUILD_H\n" +printf "#define __BUILD_H\n\n" +printf "#define COREBOOT_VERSION %s\n" "\"$KERNELVERSION\"" + +#See if the build is running in a git repo and the git command is available +if [ -d "${top}/.git" ] && [ -f "$(which git)" ]; then + printf "/* %s UTC */\n" "$(LANG= TZ=UTC git log --date=local --pretty=format:%cd -1)" + printf "#define COREBOOT_VERSION_TIMESTAMP %s\n" "$(LANG= git log --pretty=format:%ct -1)" + printf "#define COREBOOT_ORIGIN_GIT_REVISION \"%s\"\n" "$(LANG= git log remotes/origin/master -1 --format=format:%h)" +else + printf "/* `LANG= TZ=UTC date` */\n" + printf "#define COREBOOT_VERSION_TIMESTAMP %s\n" "$(LANG= date +%s)" + printf "#define COREBOOT_ORIGIN_GIT_REVISION \"Unknown\"\n" +fi + +printf "#define COREBOOT_EXTRA_VERSION \"%s\"\n" "$COREBOOT_EXTRA_VERSION" +printf "#define COREBOOT_BUILD \"%s\"\n" "$(date)" +printf "#define COREBOOT_BUILD_YEAR_BCD 0x%s\n" "$(date +%y)" +printf "#define COREBOOT_BUILD_MONTH_BCD 0x%s\n" "$(date +%m)" +printf "#define COREBOOT_BUILD_DAY_BCD 0x%s\n" "$(date +%d)" +printf "#define COREBOOT_BUILD_WEEKDAY_BCD 0x%s\n" "$(date +%w)" +printf "#define COREBOOT_DMI_DATE \"%s\"\n" "$(date +%m/%d/%Y)" +printf "\n" +printf "#define COREBOOT_COMPILE_TIME \"%s\"\n" "$(date +%T)" +printf "#define COREBOOT_COMPILE_BY \"%s\"\n" "$(whoami)" +printf "#define COREBOOT_COMPILE_HOST \"%s\"\n" "$(hostname -s 2>/dev/null)" +printf "#define COREBOOT_COMPILE_DOMAIN \"" +get_domainname +printf "\"\n" +printf "#endif\n"

1 0

New patch to review for coreboot: 22d038e soc/ipq806x: Replace GPT with fine grained DGT timer.
by Marc Jones 04 Mar '15

04 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8596 -gerrit commit 22d038e1b004d60d0600733b87475c899f159288 Author: Deepa Dinamani <deepad(a)codeaurora.org> Date: Mon Jul 14 16:26:11 2014 -0700 soc/ipq806x: Replace GPT with fine grained DGT timer. Support 1MHz libpayload restriction on timer implementation by using DGT (debug) timer instead of GPT (general purpose) timer. BUG=chrome-os-partner:28880 TEST=manual verified DGT timer functions in coreboot and depthcharge. Original-Change-Id: Iab322d7e863e3959c027e9ce876223a64eb7e257 Original-Signed-off-by: Deepa Dinamani <deepad(a)codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201574 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> (cherry picked from commit ddf11eee5ec2d86a62095e932dbec9313b8fb9e1) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Id73e805801fd8d135b607df9f4f8caf567ec5b83 --- src/soc/qualcomm/ipq806x/timer.c | 125 ++++++++++++++------------------------- 1 file changed, 43 insertions(+), 82 deletions(-) diff --git a/src/soc/qualcomm/ipq806x/timer.c b/src/soc/qualcomm/ipq806x/timer.c index 3cb9531..ce11126 100644 --- a/src/soc/qualcomm/ipq806x/timer.c +++ b/src/soc/qualcomm/ipq806x/timer.c @@ -1,8 +1,5 @@ /* - * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. - * Source : APQ8064 LK boot - * - * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * Copyright (c) 2011 - 2014 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -36,103 +33,67 @@ #include <ipq_timer.h> #include <timer.h> -#define GPT_FREQ_KHZ 32 -#define GPT_FREQ (GPT_FREQ_KHZ * 1000) /* 32 KHz */ +/* + * DGT runs at 25 MHz / 4, or 6.25 ticks per microsecond + */ +#define DGT_MHZ_NUM 25 +#define DGT_MHZ_DEN 4 + +#define TIMER_TICKS(us) ((DGT_MHZ_NUM*(us)+(DGT_MHZ_DEN-1))/DGT_MHZ_DEN) +#define TIMER_USECS(ticks) (DGT_MHZ_DEN*(ticks)/DGT_MHZ_NUM) + +/* Clock divider values for the timer. */ +#define DGT_CLK_DIV_1 0 +#define DGT_CLK_DIV_2 1 +#define DGT_CLK_DIV_3 2 +#define DGT_CLK_DIV_4 3 /** * init_timer - initialize timer */ void init_timer(void) { - writel(0, GPT_ENABLE); - writel(GPT_ENABLE_EN, GPT_ENABLE); + /* disable timer */ + writel_i(0, DGT_ENABLE); + + /* DGT uses TCXO source which is 25MHz. + * The timer should run at 1/4th the frequency of TCXO + * according to clock plan. + * Set clock divider to 4. + */ + writel_i(DGT_CLK_DIV_4, DGT_CLK_CTL); + + /* Enable timer */ + writel_i(0, DGT_CLEAR); + writel_i(DGT_ENABLE_EN, DGT_ENABLE); } /** * udelay - generates micro second delay. * @param usec: delay duration in microseconds - * - * With 32KHz clock, minimum possible delay is 31.25 Micro seconds and - * its multiples. In Rumi GPT clock is 32 KHz */ void udelay(unsigned usec) { - unsigned val; - unsigned now, last; - unsigned runcount; + uint32_t now; + uint32_t last; + uint32_t ticks; + uint32_t curr_ticks = 0; - usec = (usec + GPT_FREQ_KHZ - 1) / GPT_FREQ_KHZ; - last = readl(GPT_COUNT_VAL); - runcount = last; - val = usec + last; + /* Calculate number of ticks required. */ + ticks = TIMER_TICKS(usec); - do { - now = readl(GPT_COUNT_VAL); - if (last > now) - runcount += ((GPT_FREQ - last) + now); - else - runcount += (now - last); - last = now; - } while (runcount < val); -} - -void timer_monotonic_get(struct mono_time *mt) -{ - mono_time_set_usecs(mt, (readl(GPT_COUNT_VAL) * 1000) / GPT_FREQ_KHZ); -} - -#if 0 - -/* - * TODO(vbendeb) clean it up later. - * Compile out the below code but leave it for now in case it will become - * necessary later in order to make the platform fully functional. - */ -static unsigned long timestamp; -static unsigned long lastinc; + /* Obtain the current timer value. */ + last = readl_i(DGT_COUNT_VAL); -inline ulong gpt_to_sys_freq(unsigned int gpt) -{ - /* - * get_timer() expects the timer increments to be in terms - * of CONFIG_SYS_HZ. Convert GPT timer values to CONFIG_SYS_HZ - * units. - */ - return (((ulong)gpt) / (GPT_FREQ / CONFIG_SYS_HZ)); -} - -/** - * get_timer_masked - returns current ticks - * - * Returns the current timer ticks, since boot. - */ -ulong get_timer_masked(void) -{ - ulong now = gpt_to_sys_freq(readl(GPT_COUNT_VAL)); - - if (lastinc <= now) { /* normal mode (non roll) */ - /* normal mode */ - timestamp += now - lastinc; - /* move stamp forward with absolute diff ticks */ - } else { /* we have overflow of the count down timer */ - timestamp += now + (TIMER_LOAD_VAL - lastinc); + /* Loop until the right number of ticks. */ + while (curr_ticks < ticks) { + now = readl_i(DGT_COUNT_VAL); + curr_ticks += now - last; + last = now; } - - lastinc = now; - - return timestamp; } -unsigned long long get_ticks(void) -{ - return readl(GPT_COUNT_VAL); -} - -/* - * Return the number of timer ticks per second. - */ -ulong get_tbclk(void) +void timer_monotonic_get(struct mono_time *mt) { - return GPT_FREQ; + mono_time_set_usecs(mt, TIMER_USECS(readl_i(DGT_COUNT_VAL))); } -#endif

1 0

New patch to review for coreboot: eaa9c1f arm64: use one stage_entry for all stages
by Marc Jones 04 Mar '15

04 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8585 -gerrit commit eaa9c1fd180cb8faefc197e244c3fb7630c6a19f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 10 12:40:30 2014 -0500 arm64: use one stage_entry for all stages Ramstage needs an assembly entry point for setting up the initial state of the CPU. Therefore, a function is provided, arm64_el3_startup(), that bootstraps the state of the processor, initializes the stack pointer, and branches to a defined entry symbol. To make this work without adding too much preprocessor macro conditions provide _stack and _estack for all the stages. Currently the entry point after initialization is 'main', however it can be changed/extended to do more work such as seeding the stack contents with tombstones, etc. It should be noted that romstage and bootblock weren't tested. Only ramstage is known to work. BUG=chrome-os-partner:29923 BRANCH=None TEST=Brought up 64-bit ramstage on rush. Original-Change-Id: I1f07d5b6656e13e6667b038cdc1f4be8843d1960 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207262 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 7850ee3a7bf48c05f2e64147edb92161f8308f19) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ia87697f49638c8c249215d441d95f1ec621e0949 --- src/arch/arm64/Makefile.inc | 1 + src/arch/arm64/armv8/bootblock.S | 62 ------------------------------------ src/arch/arm64/bootblock.ld | 8 +++-- src/arch/arm64/include/arch/stages.h | 2 +- src/arch/arm64/ramstage.ld | 7 ++-- src/arch/arm64/romstage.ld | 6 +++- src/arch/arm64/stage_entry.S | 57 +++++++++++++++++++++++++++++++++ src/arch/arm64/stages.c | 5 --- 8 files changed, 74 insertions(+), 74 deletions(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index a080e23..5f778b2 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -109,6 +109,7 @@ ramstage-y += tables.c ramstage-y += memset.S ramstage-y += memcpy.S ramstage-y += memmove.S +ramstage-y += stage_entry.S ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) diff --git a/src/arch/arm64/armv8/bootblock.S b/src/arch/arm64/armv8/bootblock.S index e65515f..ef70645 100644 --- a/src/arch/arm64/armv8/bootblock.S +++ b/src/arch/arm64/armv8/bootblock.S @@ -19,68 +19,6 @@ * MA 02111-1307 USA */ -.section ".start", "a", %progbits -.globl _start -_start: b reset - .balignl 16,0xdeadbeef - -_cbfs_master_header: - /* The CBFS master header is inserted by cbfstool at the first - * aligned offset after the above anchor string is found. - * Hence, we leave some space for it. - * Assumes 64-byte alignment. - */ - .skip 128 - -reset: - /* - * Set the cpu to SVC32 mode and unmask aborts. Aborts might happen - * before logging is turned on and may crash the machine, but at least - * the problem will show up near the code that causes it. - */ - /* FIXME: Not using supervisor mode, does it apply for aarch64? */ - - msr daifclr, #0xc /* Unmask Debug and System exceptions */ - msr daifset, #0x3 /* Mask IRQ, FIQ */ - - bl arm_init_caches - - /* - * Initialize the stack to a known value. This is used to check for - * stack overflow later in the boot process. - */ - ldr x0, .Stack - ldr x1, .Stack_size - sub x0, x0, x1 - ldr x1, .Stack - ldr x2, =0xdeadbeefdeadbeef -init_stack_loop: - str x2, [x0] - add x0, x0, #8 - cmp x0, x1 - bne init_stack_loop - -/* Set stackpointer in internal RAM to call bootblock main() */ -call_bootblock: - ldr x0, .Stack /* Set up stack pointer */ - mov sp, x0 - ldr x0, =0x00000000 - - sub sp, sp, #16 - - /* - * Switch to EL2 already because Linux requires to be - * in EL1 or EL2, see its "Booting AArch64 Linux" doc - */ - bl switch_el3_to_el2 - bl main - -.align 3 -.Stack: - .word CONFIG_STACK_TOP -.align 3 -.Stack_size: - .word CONFIG_STACK_SIZE .section ".id", "a", %progbits .globl __id_start diff --git a/src/arch/arm64/bootblock.ld b/src/arch/arm64/bootblock.ld index 907d009..775111b 100644 --- a/src/arch/arm64/bootblock.ld +++ b/src/arch/arm64/bootblock.ld @@ -28,14 +28,14 @@ PHDRS to_load PT_LOAD; } -ENTRY(_start) +ENTRY(stage_entry) TARGET(binary) SECTIONS { . = CONFIG_BOOTBLOCK_BASE; .bootblock . : { - *(.text._start); + *(.text.stage_entry); KEEP(*(.id)); *(.text); *(.text.*); @@ -49,6 +49,10 @@ SECTIONS *(.sbss.*); } : to_load = 0xff + /* arm64 chipsets need to define CONFIG_BOOTBLOCK_STACK_(TOP|BOTTOM) */ + _stack = CONFIG_BOOTBLOCK_STACK_BOTTOM; + _estack = CONFIG_BOOTBLOCK_STACK_TOP; + preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; /DISCARD/ : { diff --git a/src/arch/arm64/include/arch/stages.h b/src/arch/arm64/include/arch/stages.h index e7a2401..0f82450 100644 --- a/src/arch/arm64/include/arch/stages.h +++ b/src/arch/arm64/include/arch/stages.h @@ -22,7 +22,7 @@ extern void main(void); -void stage_entry(void) __attribute__((section(".text.stage_entry.aarch64"))); +void stage_entry(void); void stage_exit(void *); void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size); diff --git a/src/arch/arm64/ramstage.ld b/src/arch/arm64/ramstage.ld index 5dc55ba..19c9309 100644 --- a/src/arch/arm64/ramstage.ld +++ b/src/arch/arm64/ramstage.ld @@ -39,7 +39,7 @@ SECTIONS .text : { _text = .; _start = .; - *(.text.stage_entry.aarch64); + *(.text.stage_entry); *(.text); *(.text.*); . = ALIGN(16); @@ -116,8 +116,9 @@ SECTIONS } _eheap = .; - _stack = CONFIG_STACK_BOTTOM; - _estack = CONFIG_STACK_TOP; + /* arm64 chipsets need to define CONFIG_RAMSTAGE_STACK_(TOP|BOTTOM) */ + _stack = CONFIG_RAMSTAGE_STACK_BOTTOM; + _estack = CONFIG_RAMSTAGE_STACK_TOP; /* The ram segment. This includes all memory used by the memory * resident copy of coreboot, except the tables that are produced on diff --git a/src/arch/arm64/romstage.ld b/src/arch/arm64/romstage.ld index a8d092c..9e08464 100644 --- a/src/arch/arm64/romstage.ld +++ b/src/arch/arm64/romstage.ld @@ -42,7 +42,7 @@ SECTIONS .romtext . : { _start = .; - *(.text.stage_entry.aarch64); + *(.text.stage_entry); *(.text.startup); *(.text); *(.text.*); @@ -76,6 +76,10 @@ SECTIONS _end = .; + /* arm64 chipsets need to define CONFIG_ROMSTAGE_STACK_(TOP|BOTTOM) */ + _stack = CONFIG_ROMSTAGE_STACK_BOTTOM; + _estack = CONFIG_ROMSTAGE_STACK_TOP; + preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; /* Discard the sections we don't need/want */ diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S new file mode 100644 index 0000000..56eca77 --- /dev/null +++ b/src/arch/arm64/stage_entry.S @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <arch/asm.h> + +ENTRY(arm64_el3_startup) + mov x0, xzr + msr SCTLR_EL3, x0 + msr SCR_EL3, x0 + /* Have stack pointer use SP_EL0. */ + msr SPSel, #0 + isb + + /* Load up the stack if non-zero. */ + ldr x0, .stack + cmp x0, #0 + b.eq 1f + mov sp, x0 + 1: + + ldr x1, .entry + br x1 + + .align 4 + /* + * By default branch to main() and initialize the stack according + * to the Kconfig option for cpu0. However, this code can be relocated + * and reused to start up secondary cpus. + */ + .stack: + .quad _estack + .entry: + .quad main +ENDPROC(arm64_el3_startup) +.global arm64_el3_startup_end +arm64_el3_startup_end: + +ENTRY(stage_entry) + b arm64_el3_startup +ENDPROC(stage_entry) diff --git a/src/arch/arm64/stages.c b/src/arch/arm64/stages.c index e1ab21a..8316b22 100644 --- a/src/arch/arm64/stages.c +++ b/src/arch/arm64/stages.c @@ -31,11 +31,6 @@ #include <arch/stages.h> #include <arch/cache.h> -void stage_entry(void) -{ - main(); -} - /* we had marked 'doit' as 'noreturn'. * There is no apparent harm in leaving it as something we can return from, and in the one * case where we call a payload, the payload is allowed to return.

1 0

New patch to review for coreboot: 25b51a6 arm64: ensure vital sections aren't garbage collected
by Marc Jones 04 Mar '15

04 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8584 -gerrit commit 25b51a63561c1303cca1d8aec599de072ce1f7fd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 10 12:32:17 2014 -0500 arm64: ensure vital sections aren't garbage collected The driver structures live in special sections which have no direct reference to the symbols. Therefore, when garbage collecting sections in the liner the drivers are tossed out resulting in no drivers being linked into ramstage. Fix this by adding the KEEP() directive to those special sections. BUG=chrome-os-partner:29923 BRANCH=None TEST=Built and noted console starts working in ramstage. Original-Change-Id: Iaa0fd428bf975c82d4e6b0e75a17e6fd231fbaa9 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207261 Original-Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 7c1a3e63e398755de0c77524a0483e6f1019aac0) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I1e30e73be754ec849cb3cfac3bcb12e95b0f60d4 --- src/arch/arm64/ramstage.ld | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/arch/arm64/ramstage.ld b/src/arch/arm64/ramstage.ld index e878820..5dc55ba 100644 --- a/src/arch/arm64/ramstage.ld +++ b/src/arch/arm64/ramstage.ld @@ -49,7 +49,7 @@ SECTIONS .ctors : { . = ALIGN(0x100); __CTOR_LIST__ = .; - *(.ctors); + KEEP(*(.ctors)); LONG(0); __CTOR_END__ = .; } @@ -58,17 +58,17 @@ SECTIONS _rodata = .; . = ALIGN(4); console_drivers = .; - *(.rodata.console_drivers) + KEEP(*(.rodata.console_drivers)); econsole_drivers = . ; . = ALIGN(4); pci_drivers = . ; - *(.rodata.pci_driver) + KEEP(*(.rodata.pci_driver)); epci_drivers = . ; cpu_drivers = . ; - *(.rodata.cpu_driver) + KEEP(*(.rodata.cpu_driver)); ecpu_drivers = . ; _bs_init_begin = .; - *(.bs_init) + KEEP(*(.bs_init)); _bs_init_end = .; *(.rodata) *(.rodata.*)

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New patch to review for coreboot: b4a7095 coreboot t132: Stack init re-work
by Marc Jones 04 Mar '15

04 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8583 -gerrit commit b4a7095bb00ea1147b007e8433cfdd43cfa4f7ae Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 7 11:45:15 2014 -0700 coreboot t132: Stack init re-work 1) In order to avoid stack from overflowing during ramstage decompression, initialize stack right at the beginning of romstage. 2) Declare different Kconfig options for stack at each stage. 3) Provide a macro that does stack seeding if required and calls appropriate function. BUG=None BRANCH=None TEST=Compiles and runs successfully on rush. Original-Change-Id: I55d6ce59ea91affba3e86d68406921497c83fb52 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206880 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 5e32d73803a2a9d222fcc4ca5f58efd3abe95d34) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ib833a1badb170a33cbf20d232019425b59db60cd --- src/soc/nvidia/tegra132/Kconfig | 20 ++++++++++++-- src/soc/nvidia/tegra132/Makefile.inc | 1 + src/soc/nvidia/tegra132/bootblock_asm.S | 41 ++++------------------------ src/soc/nvidia/tegra132/romstage.c | 3 ++- src/soc/nvidia/tegra132/romstage_asm.S | 39 +++++++++++++++++++++++++++ src/soc/nvidia/tegra132/stack.S | 47 +++++++++++++++++++++++++++++++++ 6 files changed, 112 insertions(+), 39 deletions(-) diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index a8b9bdc..761685a 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -51,14 +51,30 @@ config RAMSTAGE_BASE hex default 0x80200000 -config STACK_TOP +config BOOTBLOCK_STACK_TOP hex default 0x40020000 -config STACK_BOTTOM +config BOOTBLOCK_STACK_BOTTOM hex default 0x4001c000 +config ROMSTAGE_STACK_TOP + hex + default 0x40020000 + +config ROMSTAGE_STACK_BOTTOM + hex + default 0x4001c000 + +config RAMSTAGE_STACK_TOP + hex + default 0x80020000 + +config RAMSTAGE_STACK_BOTTOM + hex + default 0x8001c000 + config CBFS_CACHE_ADDRESS hex "memory address to put CBFS cache data" default 0x40006000 diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index c14f1c8..8c085a9 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -16,6 +16,7 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif +romstage-y += romstage_asm.S romstage-y += cbfs.c romstage-y += cbmem.c romstage-y += timer.c diff --git a/src/soc/nvidia/tegra132/bootblock_asm.S b/src/soc/nvidia/tegra132/bootblock_asm.S index ebd64a7..1b2fbb7 100644 --- a/src/soc/nvidia/tegra132/bootblock_asm.S +++ b/src/soc/nvidia/tegra132/bootblock_asm.S @@ -31,6 +31,8 @@ #include <arch/asm.h> +#include "stack.S" + ENTRY(_start) /* * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data @@ -40,40 +42,7 @@ ENTRY(_start) */ msr cpsr_cxf, #0xdf - /* - * Initialize the stack to a known value. This is used to check for - * stack overflow later in the boot process. - */ - ldr r0, .Stack - ldr r1, .Stack_size - sub r0, r0, r1 - ldr r1, .Stack - ldr r2, =0xdeadbeef -init_stack_loop: - str r2, [r0] - add r0, #4 - cmp r0, r1 - bne init_stack_loop - -/* Set stackpointer in internal RAM to call bootblock main() */ -call_bootblock: - ldr sp, .Stack /* Set up stack pointer */ - ldr r0,=0x00000000 - /* - * The current design of cpu_info places the - * struct at the top of the stack. The number of - * words pushed must be at least as large as that - * struct. - */ - push {r0-r2} - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - /* - * Use "bl" instead of "b" even though we do not intend to return. - * "bl" gets compiled to "blx" if we're transitioning from ARM to - * Thumb. However, "b" will not and GCC may attempt to create a - * wrapper which is currently broken. - */ - bl main + stack_init stack=.Stack size=.Stack_size seed=1 func=main ENDPROC(_start) /* we do it this way because it's a 32-bit constant and @@ -82,8 +51,8 @@ ENDPROC(_start) */ .align 2 .Stack: - .word CONFIG_STACK_TOP + .word CONFIG_BOOTBLOCK_STACK_TOP .align 2 /* create this size the same way we do in ramstage.ld: top-bottom */ .Stack_size: - .word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM + .word CONFIG_BOOTBLOCK_STACK_TOP - CONFIG_BOOTBLOCK_STACK_BOTTOM diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index 3bc2231..6d51403 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -26,7 +26,8 @@ #include "sdram.h" #include "ccplex.h" -void main(void) +void romstage(void); +void romstage(void) { void *entry; diff --git a/src/soc/nvidia/tegra132/romstage_asm.S b/src/soc/nvidia/tegra132/romstage_asm.S new file mode 100644 index 0000000..ac3c93e --- /dev/null +++ b/src/soc/nvidia/tegra132/romstage_asm.S @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/asm.h> +#include "stack.S" + + .section ".text", "ax", %progbits + +ENTRY(main) + stack_init stack=.Stack size=.Stack_size seed=0 func=romstage +ENDPROC(main) + +/* we do it this way because it's a 32-bit constant and + * in some cases too far away to be loaded as just an offset + * from IP + */ +.align 2 +.Stack: + .word CONFIG_ROMSTAGE_STACK_TOP +.align 2 +.Stack_size: + .word CONFIG_ROMSTAGE_STACK_TOP - CONFIG_ROMSTAGE_STACK_BOTTOM + diff --git a/src/soc/nvidia/tegra132/stack.S b/src/soc/nvidia/tegra132/stack.S new file mode 100644 index 0000000..6d3cd4e --- /dev/null +++ b/src/soc/nvidia/tegra132/stack.S @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Macro to initialize stack, perform seeding if required and finally call the + * function provided + * @stack : Stack address + * @size : Stack size + * @seed : Stack seeding required (1=yes/otherwise=no) + * @func : Function to call after initializing stack + */ +.macro stack_init stack, size, seed, func + /* Check if stack seeding is required */ + mov r0, #\seed + cmp r0, #1 + bne call_func + /* Stack seeding */ + ldr r0, \stack + ldr r1, \size + sub r0, r0, r1 + ldr r1, \stack + ldr r2, =0xdeadbeef +init_stack_loop: + str r2, [r0] + add r0, #4 + cmp r0, r1 + bne init_stack_loop + +call_func: + ldr sp, \stack /* Set up stack pointer */ + bl \func +.endm

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New patch to review for coreboot: 134b1e3 rush: PMIC: initial AS3722 PMIC writes for Rush
by Marc Jones 04 Mar '15

04 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8582 -gerrit commit 134b1e30f5c1fbf88eaf192351da9e81e801c3e0 Author: Tom Warren <twarren(a)nvidia.com> Date: Tue Jul 1 17:08:27 2014 -0700 rush: PMIC: initial AS3722 PMIC writes for Rush Still waiting on VDD_CPU value, etc. from board guys, but this is a start. BUG=None BRANCH=None TEST=Built and flashed rush, saw 'PMIC init done' string OK. Original-Change-Id: I6f8b16c4ebf1e9c159f8175d59262119ef0e498f Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206412 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 96a9ff8f632c2b9bf3f81f5b8fc4f3b6784a02bc) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I9d3d7ff55f2d6ca88ebdcc8ad1d7de135f5136d2 --- src/mainboard/google/rush/pmic.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/rush/pmic.c b/src/mainboard/google/rush/pmic.c index c114066..7aa7dc9 100644 --- a/src/mainboard/google/rush/pmic.c +++ b/src/mainboard/google/rush/pmic.c @@ -92,19 +92,13 @@ void pmic_init(unsigned bus) /* Restore PMIC POR defaults, in case kernel changed 'em */ pmic_slam_defaults(bus); - /* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */ - if (board_id() == 0) - pmic_write_reg(bus, 0x00, 0x3c, 1); - else - pmic_write_reg(bus, 0x00, 0x50, 1); + /* SDO0: Set VDD_CPU to 1.2V. */ + pmic_write_reg(bus, 0x00, 0x50, 1); - /* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */ + /* SDO6: Set VDD_GPU to 1.0V. */ pmic_write_reg(bus, 0x06, 0x28, 1); - /* - * First set +1.2V_GEN_AVDD to 1.2V, then enable the +1.2V_GEN_AVDD - * regulator. - */ + /* LDO2: Set +1.2V_GEN_AVDD to 1.2V */ pmic_write_reg(bus, 0x12, 0x10, 1); /* @@ -113,4 +107,6 @@ void pmic_init(unsigned bus) */ pmic_write_reg(bus, 0x0c, 0x07, 0); pmic_write_reg(bus, 0x20, 0x10, 1); + + printk(BIOS_DEBUG, "PMIC init done\n"); }

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New patch to review for coreboot: ead2b9c t132: kick off core complex after loading MTS microcode
by Marc Jones 04 Mar '15

04 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8581 -gerrit commit ead2b9c4e2acda9fa801283e2108ead61ea9d1f2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jul 1 13:51:21 2014 -0500 t132: kick off core complex after loading MTS microcode Once the MTS microcode is loaded the core complex can be directed to decode the MTS and start running. The cores, however, won't start executing until instructed to do so. BUG=chrome-os-partner:29222 BRANCH=None TEST=Built, booted, ran. Noted it took about 920ms for the core complex to decode and handshake back. Original-Change-Id: I0a9ed53e596eb65801461b2769d133710a92a48a Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/206075 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> (cherry picked from commit 6edb6e21a69d84ba5b23137e9e390954159e7887) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I179e561bb3a34b206620eecde6781a1c05a3744e --- src/soc/nvidia/tegra132/ccplex.c | 48 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c index b569bd2..b774630 100644 --- a/src/soc/nvidia/tegra132/ccplex.c +++ b/src/soc/nvidia/tegra132/ccplex.c @@ -21,12 +21,58 @@ #include <console/console.h> #include <arch/io.h> #include <cbfs.h> +#include <timer.h> #include <soc/addressmap.h> +#include "clk_rst.h" #include "ccplex.h" #include "mc.h" +#include "pmc.h" +#define CLK_RST_REGS (void *)(uintptr_t)(TEGRA_CLK_RST_BASE) +#define PMC_REGS (void *)(uintptr_t)(TEGRA_PMC_BASE) #define MTS_FILE_NAME "mts" +static int ccplex_start(void) +{ + struct mono_time t1, t2; + const long timeout_us = 1500000; + long wait_time; + const uint32_t handshake_mask = 1; + const uint32_t cxreset1_mask = 1 << 21; + uint32_t reg; + struct tegra_pmc_regs * const pmc = PMC_REGS; + struct clk_rst_ctlr * const clk_rst = CLK_RST_REGS; + + /* Set the handshake bit to be knocked down. */ + write32(handshake_mask, &pmc->scratch118); + + /* Assert nCXRSET[1] */ + reg = read32(&clk_rst->rst_cpu_cmplx_set); + reg |= cxreset1_mask; + write32(reg, &clk_rst->rst_cpu_cmplx_set); + + timer_monotonic_get(&t1); + while (1) { + reg = read32(&pmc->scratch118); + timer_monotonic_get(&t2); + + wait_time = mono_time_diff_microseconds(&t1, &t2); + + /* Wait for the bit to be knocked down. */ + if ((reg & handshake_mask) != handshake_mask) + break; + + if (wait_time >= timeout_us) { + printk(BIOS_DEBUG, "MTS handshake timeout.\n"); + return -1; + } + } + + printk(BIOS_DEBUG, "MTS handshake took %ld us.\n", wait_time); + + return 0; +} + int ccplex_load_mts(void) { struct cbfs_file file; @@ -57,5 +103,5 @@ int ccplex_load_mts(void) printk(BIOS_DEBUG, "MTS: %zu bytes loaded @ %p\n", nread, mts); - return 0; + return ccplex_start(); }

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New patch to review for coreboot: e415fa9 t132: load MTS microcode
by Marc Jones 04 Mar '15

04 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8580 -gerrit commit e415fa9b16dd3bb7eca11e50d41702225e00beb0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jun 30 16:37:13 2014 -0500 t132: load MTS microcode The armv8 cores need to have microcode loaded before they can be taken out of reset. Locate and load the MTS microcode at the fixed address of 0x82000000. The ccplex, once enabled, will decode and transfer the microcode to the carveout region. BUG=chrome-os-partner:29922 BRANCH=None TEST=Built and ran. Confirmed dump of MTS region after loading code. Original-Change-Id: Ie5ab72e5363cbdb251d169356f718020d375fce6 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/206290 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 6726d8862c08b155b9218aa5e2e39428a105089e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I425c2e2fd1eaec49d81bef1ff4bf4f36da9296df --- src/soc/nvidia/tegra132/Makefile.inc | 1 + src/soc/nvidia/tegra132/ccplex.c | 61 ++++++++++++++++++++++++++++++++++++ src/soc/nvidia/tegra132/ccplex.h | 28 +++++++++++++++++ src/soc/nvidia/tegra132/romstage.c | 7 +++-- 4 files changed, 95 insertions(+), 2 deletions(-) diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index a984674..c14f1c8 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -19,6 +19,7 @@ endif romstage-y += cbfs.c romstage-y += cbmem.c romstage-y += timer.c +romstage-y += ccplex.c romstage-y += clock.c romstage-y += spi.c romstage-y += i2c.c diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c new file mode 100644 index 0000000..b569bd2 --- /dev/null +++ b/src/soc/nvidia/tegra132/ccplex.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <console/console.h> +#include <arch/io.h> +#include <cbfs.h> +#include <soc/addressmap.h> +#include "ccplex.h" +#include "mc.h" + +#define MTS_FILE_NAME "mts" + +int ccplex_load_mts(void) +{ + struct cbfs_file file; + ssize_t offset; + size_t nread; + /* + * MTS location is hard coded to this magic address. The hardware will + * take the MTS from this location and place it in the final resting + * place in the carveout region. + */ + void * const mts = (void *)(uintptr_t)MTS_LOAD_ADDRESS; + struct cbfs_media *media = CBFS_DEFAULT_MEDIA; + + offset = cbfs_locate_file(media, &file, MTS_FILE_NAME); + if (offset < 0) { + printk(BIOS_DEBUG, "MTS file not found: %s\n", MTS_FILE_NAME); + return -1; + } + + /* Read MTS file into the carveout region. */ + nread = cbfs_read(media, mts, offset, file.len); + + if (nread != file.len) { + printk(BIOS_DEBUG, "MTS bytes read (%zu) != file length(%u)!\n", + nread, file.len); + return -1; + } + + printk(BIOS_DEBUG, "MTS: %zu bytes loaded @ %p\n", nread, mts); + + return 0; +} diff --git a/src/soc/nvidia/tegra132/ccplex.h b/src/soc/nvidia/tegra132/ccplex.h new file mode 100644 index 0000000..6b9699c --- /dev/null +++ b/src/soc/nvidia/tegra132/ccplex.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_CCPLEX_H__ +#define __SOC_NVIDIA_TEGRA132_CCPLEX_H__ + +#define MTS_LOAD_ADDRESS 0x82000000 + +/* Loads the MTS microcode. Return 0 on success, < 0 on error. */ +int ccplex_load_mts(void); + +#endif /* __SOC_NVIDIA_TEGRA132_CCPLEX_H__ */ diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index 20429a5..3bc2231 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -23,7 +23,8 @@ #include <arch/exception.h> #include <soc/sdram_configs.h> -#include <soc/nvidia/tegra132/sdram.h> +#include "sdram.h" +#include "ccplex.h" void main(void) { @@ -35,9 +36,11 @@ void main(void) printk(BIOS_INFO, "T132: romstage here\n"); sdram_init(get_sdram_config()); - printk(BIOS_INFO, "T132 romstage: sdram_init done\n"); + ccplex_load_mts(); + printk(BIOS_INFO, "T132 romstage: MTS loading done\n"); + while (1); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,

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coreboot-gerrit March 2015