coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 367371a coreboot t132: Add clock.c to all three stages of coreboot
by Marc Jones 03 Mar '15

03 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8569 -gerrit commit 367371ac71e97e0d2c39a16c995f5a09a59d5784 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jun 24 15:24:22 2014 -0700 coreboot t132: Add clock.c to all three stages of coreboot Enable adding of clock.c to romstage and ramstage in addition to bootblock. Code for enabling armv8 core is not included yet. clock_init added to bootblock.c BUG=None BRANCH=None TEST=Compiles successfully for rush. Original-Change-Id: I858c41a83d665da2c406707586b5e35a732177d4 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205581 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 61dbf1db72307815c4abdc218799479c334a4882) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I688e1e1373dea26557a84507a8e92d3055862801 --- src/soc/nvidia/tegra132/Makefile.inc | 2 ++ src/soc/nvidia/tegra132/bootblock.c | 4 +++ src/soc/nvidia/tegra132/clock.c | 53 ------------------------------------ 3 files changed, 6 insertions(+), 53 deletions(-) diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 5c6fe81..af33e2d 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -14,6 +14,7 @@ endif romstage-y += cbfs.c romstage-y += cbmem.c romstage-y += timer.c +romstage-y += clock.c romstage-y += ../tegra/gpio.c romstage-y += ../tegra/pinmux.c romstage-$(CONFIG_DRIVERS_UART) += uart.c @@ -21,6 +22,7 @@ romstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += cbfs.c ramstage-y += cbmem.c ramstage-y += timer.c +ramstage-y += clock.c ramstage-y += ../tegra/gpio.c ramstage-y += ../tegra/pinmux.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c index 2d8c10f..3544c65 100644 --- a/src/soc/nvidia/tegra132/bootblock.c +++ b/src/soc/nvidia/tegra132/bootblock.c @@ -56,4 +56,8 @@ void main(void) exception_init(); printk(BIOS_INFO, "Tegra132: Bootblock here\n"); } + + clock_init(); + + while(1); } diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c index 2da7ea1..9db957c 100644 --- a/src/soc/nvidia/tegra132/clock.c +++ b/src/soc/nvidia/tegra132/clock.c @@ -476,59 +476,6 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, void clock_cpu0_config_and_reset(void *entry) { - void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100; - - write32(CONFIG_STACK_TOP, &maincpu_stack_pointer); - write32((uintptr_t)entry, &maincpu_entry_point); - write32((uintptr_t)&maincpu_setup, evp_cpu_reset); - - /* Set active CPU cluster to G */ - clrbits_le32(&flow->cluster_control, 1); - - /* Set up cclk_brst and divider. */ - write32((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | - (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | - (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | - (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | - (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28), - &clk_rst->cclk_brst_pol); - write32(CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB, - &clk_rst->super_cclk_div); - - /* Enable the clocks for CPUs 0-3. */ - uint32_t cpu_cmplx_clr = read32(&clk_rst->clk_cpu_cmplx_clr); - cpu_cmplx_clr |= CRC_CLK_CLR_CPU0_STP | CRC_CLK_CLR_CPU1_STP | - CRC_CLK_CLR_CPU2_STP | CRC_CLK_CLR_CPU3_STP; - write32(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr); - - /* Enable other CPU related clocks. */ - setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU); - setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPUG); - setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPULP); - - /* Disable the reset on the non-CPU parts of the fast cluster. */ - write32(CRC_RST_CPUG_CLR_NONCPU, - &clk_rst->rst_cpug_cmplx_clr); - /* Disable the various resets on the CPUs. */ - write32(CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | - CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | - CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | - CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 | - CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 | - CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 | - CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | - CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | - CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG, - &clk_rst->rst_cpug_cmplx_clr); - - /* Disable the reset on the non-CPU parts of the slow cluster. */ - write32(CRC_RST_CPULP_CLR_NONCPU, - &clk_rst->rst_cpulp_cmplx_clr); - /* Disable the various resets on the LP CPU. */ - write32(CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | - CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | - CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG, - &clk_rst->rst_cpulp_cmplx_clr); } void clock_halt_avp(void)

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Patch merged into coreboot/master: 67b0374 coreboot arm64: Correct cache function names
by gerrit＠coreboot.org 02 Mar '15

02 Mar '15

the following patch was just integrated into master: commit 67b03746497f326f157a2bc82b25d8dbe365a0ff Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jun 24 17:35:30 2014 -0700 coreboot arm64: Correct cache function names Correct function names to make them consistent with generic calling name BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I50499936e1c8da0aafd7e36a22c2c6ab373230f6 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205582 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 16668529527224fca3086ee88955d29e3a268516) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I449e63b05680ca12ae81a3260fc03836686d7317 Reviewed-on: http://review.coreboot.org/8469 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8469 for details. -gerrit

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Patch merged into coreboot/master: d653ae8 coreboot arm: Define function for setting cntfrq register
by gerrit＠coreboot.org 02 Mar '15

02 Mar '15

the following patch was just integrated into master: commit d653ae89606459d3fccc507c923bdfce262c0f7b Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jun 24 15:21:03 2014 -0700 coreboot arm: Define function for setting cntfrq register Define functions for setting cntfrq register in arm and arm64 arch. This allows SoCs to set this register independently of the architecture being used. BUG=None BRANCH=None TEST=Compiles successfully for nyan and rush Original-Change-Id: I93240419b2c012eee29a408deff34a42af943a63 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205580 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 768463fef5d630dec915aa0b95e7724d4a6f74b6) armv8: GPL license armv8 lib BUG=None BRANCH=None TEST=Compiles successfully. Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250950 Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I298c3e76cb52f0876bce3dd4f54d875f62e9310a Reviewed-on: http://review.coreboot.org/8468 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8468 for details. -gerrit

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Patch set updated for coreboot: b48d607 coreboot arm: Define function for setting cntfrq register
by Marc Jones 02 Mar '15

02 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8468 -gerrit commit b48d607327d3bdafec119677c2c3b46ecf98fdc4 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jun 24 15:21:03 2014 -0700 coreboot arm: Define function for setting cntfrq register Define functions for setting cntfrq register in arm and arm64 arch. This allows SoCs to set this register independently of the architecture being used. BUG=None BRANCH=None TEST=Compiles successfully for nyan and rush Original-Change-Id: I93240419b2c012eee29a408deff34a42af943a63 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205580 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 768463fef5d630dec915aa0b95e7724d4a6f74b6) armv8: GPL license armv8 lib BUG=None BRANCH=None TEST=Compiles successfully. Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250950 Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I298c3e76cb52f0876bce3dd4f54d875f62e9310a --- src/arch/arm/Makefile.inc | 3 ++ src/arch/arm/clock.c | 36 +++++++++++++++ src/arch/arm/include/arch/clock.h | 25 +++++++++++ src/arch/arm64/armv8/lib/Makefile.inc | 2 +- src/arch/arm64/armv8/lib/clock.c | 32 +++++++++++++ src/arch/arm64/include/arch/clock.h | 25 +++++++++++ src/soc/nvidia/tegra124/clock.c | 3 +- src/soc/nvidia/tegra132/clock.c | 84 ++++++++++++++++++++--------------- 8 files changed, 172 insertions(+), 38 deletions(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 96c8b49..0fcbf6c 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -60,6 +60,7 @@ bootblock-y += memset.S bootblock-y += memcpy.S bootblock-y += memmove.S bootblock-y += div0.c +bootblock-y += clock.c $(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) $$(VERSTAGE_LIB) @printf " LINK $(subst $(obj)/,,$(@))\n" @@ -91,6 +92,7 @@ romstage-y += eabi_compat.c romstage-y += memset.S romstage-y += memcpy.S romstage-y += memmove.S +romstage-y += clock.c VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o @@ -115,6 +117,7 @@ ramstage-y += tables.c ramstage-y += memset.S ramstage-y += memcpy.S ramstage-y += memmove.S +ramstage-y += clock.c ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $$(ramstage-objs) $(src)/arch/arm/ramstage.ld $(obj)/ldoptions diff --git a/src/arch/arm/clock.c b/src/arch/arm/clock.c new file mode 100644 index 0000000..5f68e6f --- /dev/null +++ b/src/arch/arm/clock.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#include <stdint.h> +#include <arch/clock.h> + +void set_cntfrq(uint32_t freq) +{ + __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0\n" :: "r"(freq)); +} diff --git a/src/arch/arm/include/arch/clock.h b/src/arch/arm/include/arch/clock.h new file mode 100644 index 0000000..a11fbd4 --- /dev/null +++ b/src/arch/arm/include/arch/clock.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ARM_CLOCK_H_ +#define __ARM_CLOCK_H_ + +void set_cntfrq(uint32_t); + +#endif //__ARM_CLOCK_H_ diff --git a/src/arch/arm64/armv8/lib/Makefile.inc b/src/arch/arm64/armv8/lib/Makefile.inc index bda203b..3e393bb 100644 --- a/src/arch/arm64/armv8/lib/Makefile.inc +++ b/src/arch/arm64/armv8/lib/Makefile.inc @@ -20,7 +20,7 @@ ## ################################################################################ -lib_access = pstate.c sysctrl.c cache.c tlb.c misc.c +lib_access = pstate.c sysctrl.c cache.c tlb.c misc.c clock.c ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV8_64),y) bootblock-y += $(lib_access) diff --git a/src/arch/arm64/armv8/lib/clock.c b/src/arch/arm64/armv8/lib/clock.c new file mode 100644 index 0000000..00c9208 --- /dev/null +++ b/src/arch/arm64/armv8/lib/clock.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * clock.c: Functions for accessing clock and timer related registers + * Reference: ARM Architecture Reference Manual, ARMv8-A edition + */ + +#include <stdint.h> + +#include <arch/clock.h> + +void set_cntfrq(uint32_t freq) +{ + __asm__ __volatile__("msr cntfrq_el0, %0" :: "r"(freq)); +} diff --git a/src/arch/arm64/include/arch/clock.h b/src/arch/arm64/include/arch/clock.h new file mode 100644 index 0000000..a11fbd4 --- /dev/null +++ b/src/arch/arm64/include/arch/clock.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ARM_CLOCK_H_ +#define __ARM_CLOCK_H_ + +void set_cntfrq(uint32_t); + +#endif //__ARM_CLOCK_H_ diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index e3c0e71..fa33283 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -20,6 +20,7 @@ #include <soc/addressmap.h> #include <soc/clock.h> #include <stdlib.h> +#include <arch/clock.h> #include "clk_rst.h" #include "flow.h" #include "maincpu.h" @@ -181,7 +182,7 @@ void clock_init_arm_generic_timer(void) { uint32_t freq = clock_get_osc_khz() * 1000; // Set the cntfrq register. - __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0\n" :: "r"(freq)); + set_cntfrq(freq); // Record the system timer frequency. write32(freq, &sysctr->cntfid0); diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c index 5237712..2da7ea1 100644 --- a/src/soc/nvidia/tegra132/clock.c +++ b/src/soc/nvidia/tegra132/clock.c @@ -20,6 +20,7 @@ #include <soc/addressmap.h> #include <soc/clock.h> #include <stdlib.h> +#include <arch/clock.h> #include "clk_rst.h" #include "flow.h" #include "maincpu.h" @@ -180,12 +181,12 @@ int clock_get_pll_input_khz(void) void clock_init_arm_generic_timer(void) { uint32_t freq = clock_get_osc_khz() * 1000; - // Set the cntfrq register. - __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0\n" :: "r"(freq)); + /* Set the cntfrq register. */ + set_cntfrq(freq); - // Record the system timer frequency. + /* Record the system timer frequency. */ write32(freq, &sysctr->cntfid0); - // Enable the system counter. + /* Enable the system counter. */ uint32_t cntcr = read32(&sysctr->cntcr); cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG; write32(cntcr, &sysctr->cntcr); @@ -282,7 +283,7 @@ static void graphics_pll(void) * I don't want to find out in a few months * that it is needed. */ - u32 scfg = (1<<28) | (1<<24) | (1<<22); + u32 scfg = (1 << 28) | (1 << 24) | (1 << 22); writel(scfg, cfg); init_pll(&clk_rst->plldp_base, &clk_rst->plldp_misc, osc_table[osc].plldp, PLLDPD2_MISC_LOCK_ENABLE); @@ -309,8 +310,9 @@ clock_display(u32 frequency) * iterate all possible values. Note Tegra 124 supports 11 bits for n, * but our pll_fields has only 10 bits for n. * - * Note values undershoot or overshoot target output frequency may not - * work if the values are not in "safe" range by panel specification. + * Note, values that undershoot or overshoot the target output frequency + * may not work if the values are not in "safe" range by panel + * specification. */ struct pllpad_dividers plld = { 0 }; u32 ref = clock_get_pll_input_khz() * 1000, m, n, p = 0; @@ -366,11 +368,10 @@ clock_display(u32 frequency) else plld.cpcon = 12; - if (best_diff) { + if (best_diff) printk(BIOS_ERR, "%s: Failed to match output frequency %u, " "best difference is %u.\n", __func__, frequency, best_diff); - } printk(BIOS_DEBUG, "%s: PLLD=%u ref=%u, m/n/p/cpcon=%u/%u/%u/%u\n", __func__, (ref / plld.m * plld.n) >> plld.p, ref, plld.m, plld.n, @@ -424,10 +425,10 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, u32 misc1 = ((setup << PLLM_MISC1_SETUP_SHIFT) | (ph45 << PLLM_MISC1_PD_LSHIFT_PH45_SHIFT) | (ph90 << PLLM_MISC1_PD_LSHIFT_PH90_SHIFT) | - (ph135 << PLLM_MISC1_PD_LSHIFT_PH135_SHIFT)), - misc2 = ((kvco << PLLM_MISC2_KVCO_SHIFT) | - (kcp << PLLM_MISC2_KCP_SHIFT)), - base; + (ph135 << PLLM_MISC1_PD_LSHIFT_PH135_SHIFT)); + u32 misc2 = ((kvco << PLLM_MISC2_KVCO_SHIFT) | + (kcp << PLLM_MISC2_KCP_SHIFT)); + u32 base; if (same_freq) emc_source |= CLK_SOURCE_EMC_MC_EMC_SAME_FREQ; @@ -455,9 +456,9 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, /* stable_time is required, before we can start to check lock. */ udelay(stable_time); - while (!(readl(&clk_rst->pllm_base) & PLL_BASE_LOCK)) { + while (!(readl(&clk_rst->pllm_base) & PLL_BASE_LOCK)) udelay(1); - } + /* * After PLLM reports being locked, we have to delay 10us before * enabling PLLM_OUT. @@ -484,7 +485,7 @@ void clock_cpu0_config_and_reset(void *entry) /* Set active CPU cluster to G */ clrbits_le32(&flow->cluster_control, 1); - // Set up cclk_brst and divider. + /* Set up cclk_brst and divider. */ write32((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | @@ -494,21 +495,21 @@ void clock_cpu0_config_and_reset(void *entry) write32(CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB, &clk_rst->super_cclk_div); - // Enable the clocks for CPUs 0-3. + /* Enable the clocks for CPUs 0-3. */ uint32_t cpu_cmplx_clr = read32(&clk_rst->clk_cpu_cmplx_clr); cpu_cmplx_clr |= CRC_CLK_CLR_CPU0_STP | CRC_CLK_CLR_CPU1_STP | CRC_CLK_CLR_CPU2_STP | CRC_CLK_CLR_CPU3_STP; write32(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr); - // Enable other CPU related clocks. + /* Enable other CPU related clocks. */ setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU); setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPUG); setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPULP); - // Disable the reset on the non-CPU parts of the fast cluster. + /* Disable the reset on the non-CPU parts of the fast cluster. */ write32(CRC_RST_CPUG_CLR_NONCPU, &clk_rst->rst_cpug_cmplx_clr); - // Disable the various resets on the CPUs. + /* Disable the various resets on the CPUs. */ write32(CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | @@ -520,10 +521,10 @@ void clock_cpu0_config_and_reset(void *entry) CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG, &clk_rst->rst_cpug_cmplx_clr); - // Disable the reset on the non-CPU parts of the slow cluster. + /* Disable the reset on the non-CPU parts of the slow cluster. */ write32(CRC_RST_CPULP_CLR_NONCPU, &clk_rst->rst_cpulp_cmplx_clr); - // Disable the various resets on the LP CPU. + /* Disable the various resets on the LP CPU. */ write32(CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG, @@ -532,11 +533,10 @@ void clock_cpu0_config_and_reset(void *entry) void clock_halt_avp(void) { - for (;;) { + for (;;) write32(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT, &flow->halt_cop_events); - } } void clock_init(void) @@ -601,22 +601,34 @@ void clock_init(void) void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) { - if (l) writel(l, &clk_rst->clk_enb_l_set); - if (h) writel(h, &clk_rst->clk_enb_h_set); - if (u) writel(u, &clk_rst->clk_enb_u_set); - if (v) writel(v, &clk_rst->clk_enb_v_set); - if (w) writel(w, &clk_rst->clk_enb_w_set); - if (x) writel(x, &clk_rst->clk_enb_x_set); + if (l) + writel(l, &clk_rst->clk_enb_l_set); + if (h) + writel(h, &clk_rst->clk_enb_h_set); + if (u) + writel(u, &clk_rst->clk_enb_u_set); + if (v) + writel(v, &clk_rst->clk_enb_v_set); + if (w) + writel(w, &clk_rst->clk_enb_w_set); + if (x) + writel(x, &clk_rst->clk_enb_x_set); /* Give clocks time to stabilize. */ udelay(IO_STABILIZATION_DELAY); - if (l) writel(l, &clk_rst->rst_dev_l_clr); - if (h) writel(h, &clk_rst->rst_dev_h_clr); - if (u) writel(u, &clk_rst->rst_dev_u_clr); - if (v) writel(v, &clk_rst->rst_dev_v_clr); - if (w) writel(w, &clk_rst->rst_dev_w_clr); - if (x) writel(x, &clk_rst->rst_dev_x_clr); + if (l) + writel(l, &clk_rst->rst_dev_l_clr); + if (h) + writel(h, &clk_rst->rst_dev_h_clr); + if (u) + writel(u, &clk_rst->rst_dev_u_clr); + if (v) + writel(v, &clk_rst->rst_dev_v_clr); + if (w) + writel(w, &clk_rst->rst_dev_w_clr); + if (x) + writel(x, &clk_rst->rst_dev_x_clr); } void clock_reset_l(u32 bit)

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Patch set updated for coreboot: 723afe6 coreboot arm64: Correct cache function names
by Marc Jones 02 Mar '15

02 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8469 -gerrit commit 723afe6e469e6eb3f8f9e2e745458bedcc5ee6b4 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jun 24 17:35:30 2014 -0700 coreboot arm64: Correct cache function names Correct function names to make them consistent with generic calling name BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I50499936e1c8da0aafd7e36a22c2c6ab373230f6 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205582 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 16668529527224fca3086ee88955d29e3a268516) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I449e63b05680ca12ae81a3260fc03836686d7317 --- src/arch/arm64/armv8/cache.c | 6 +++--- src/arch/arm64/include/armv8/arch/cache.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index 918a883..97822ff 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -101,17 +101,17 @@ static void dcache_op_va(void const *addr, size_t len, enum dcache_op op) isb(); } -void dcache_clean_by_va(void const *addr, size_t len) +void dcache_clean_by_mva(void const *addr, size_t len) { dcache_op_va(addr, len, OP_DCCVAC); } -void dcache_clean_invalidate_by_va(void const *addr, size_t len) +void dcache_clean_invalidate_by_mva(void const *addr, size_t len) { dcache_op_va(addr, len, OP_DCCIVAC); } -void dcache_invalidate_by_va(void const *addr, size_t len) +void dcache_invalidate_by_mva(void const *addr, size_t len) { dcache_op_va(addr, len, OP_DCIVAC); } diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h index 977edba..2d42011 100644 --- a/src/arch/arm64/include/armv8/arch/cache.h +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -59,13 +59,13 @@ /* dcache clean by virtual address to PoC */ -void dcache_clean_by_va(void const *addr, size_t len); +void dcache_clean_by_mva(void const *addr, size_t len); /* dcache clean and invalidate by virtual address to PoC */ -void dcache_clean_invalidate_by_va(void const *addr, size_t len); +void dcache_clean_invalidate_by_mva(void const *addr, size_t len); /* dcache invalidate by virtual address to PoC */ -void dcache_invalidate_by_va(void const *addr, size_t len); +void dcache_invalidate_by_mva(void const *addr, size_t len); /* dcache invalidate all */ void flush_dcache_all(void);

1 0

Patch merged into coreboot/master: 732b83e tegra132: Enable bootblock support in tegra132 including UART support
by gerrit＠coreboot.org 02 Mar '15

02 Mar '15

the following patch was just integrated into master: commit 732b83ed3667d7c3066d2c16406ab6acdd8f32b9 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jun 9 13:20:04 2014 -0700 tegra132: Enable bootblock support in tegra132 including UART support BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: Ia9420cfec5333dd5477f04cf080bdad8a37db025 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203143 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit a1037f203c6a07cb116eeb1632cb7200ad022cd3) This cherry-pick was modified to match the tegra124 uart.c, which uses the idx and base address calculations instead of Kconfig settings. This driver could use the 8250MEM driver when the ARM vs x86 IO calling convention is worked out. Change-Id: I6e439359b8bb541db4679ac144c519cf251ffed6 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/8517 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8517 for details. -gerrit

1 0

Patch set updated for coreboot: e8f80fe ectool: add --dump / -d for RAM dump
by Alexander Couzens 02 Mar '15

02 Mar '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8381 -gerrit commit e8f80fe124b24f7a09c80c616969005b84aefb2c Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sat Feb 7 04:10:12 2015 +0100 ectool: add --dump / -d for RAM dump This moves the ram dump behind an argument, but it still be called by default when no over arguments given. Change-Id: I82648e8cf1eac455e9937bd3669a0e91a3ee87cf Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- util/ectool/ectool.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/util/ectool/ectool.c b/util/ectool/ectool.c index fddf340..2ed7ddf 100644 --- a/util/ectool/ectool.c +++ b/util/ectool/ectool.c @@ -46,11 +46,12 @@ void print_version(void) void print_usage(const char *name) { - printf("usage: %s [-vh?Vi] [-w 0x<addr> -z 0x<data>]\n", name); + printf("usage: %s [-vh?Vid] [-w 0x<addr> -z 0x<data>]\n", name); printf("\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" " -V | --verbose: print debug information\n" + " -d | --dump: print RAM\n" " -i | --idx: print IDX RAM\n" " -w <addr in hex> write to addr\n" " -z <data in hex> write to data\n" @@ -58,7 +59,7 @@ void print_usage(const char *name) exit(1); } -int verbose = 0, dump_idx = 0; +int verbose = 0, dump_idx = 0, dump_ram = 0; int main(int argc, char *argv[]) { @@ -74,7 +75,7 @@ int main(int argc, char *argv[]) {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "vh?Viw:z:", + while ((opt = getopt_long(argc, argv, "vh?Vidw:z:", long_options, &option_index)) != EOF) { switch (opt) { case 'v': @@ -93,6 +94,9 @@ int main(int argc, char *argv[]) case 'z': write_data = strtol(optarg , NULL, 16); break; + case 'd': + dump_ram = 1; + break; case 'h': case '?': default: @@ -113,13 +117,19 @@ int main(int argc, char *argv[]) ec_write(write_addr & 0xff, write_data & 0xff); } - printf("EC RAM:\n"); - for (i = 0; i < 0x100; i++) { - if ((i % 0x10) == 0) - printf("\n%02x: ", i); - printf("%02x ", ec_read(i)); + /* preserve default - dump_ram if nothing selected */ + if (!dump_ram && !dump_idx) + dump_ram = 1; + + if (dump_ram) { + printf("EC RAM:\n"); + for (i = 0; i < 0x100; i++) { + if ((i % 0x10) == 0) + printf("\n%02x: ", i); + printf("%02x ", ec_read(i)); + } + printf("\n\n"); } - printf("\n\n"); if (dump_idx) { printf("EC IDX RAM:\n");

1 0

Patch set updated for coreboot: a6c06e7 ectool: add query function to ectool
by Alexander Couzens 02 Mar '15

02 Mar '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8382 -gerrit commit a6c06e7656ecce2a5de5af7ca70eb923c68ba02b Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Fri Feb 6 22:27:33 2015 +0100 ectool: add query function to ectool `ectool -q` - Query the EC IRQ byte. Should return 0x00 otherwise the IRQ handler is usally broken or disabled. Tested-on: Lenovo X201t Change-Id: I0b8c2dbcf38d2eab89d0fbea05795759c4517f6d Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- util/ectool/ec.c | 6 ++++++ util/ectool/ec.h | 1 + util/ectool/ectool.c | 17 +++++++++++++---- 3 files changed, 20 insertions(+), 4 deletions(-) diff --git a/util/ectool/ec.c b/util/ectool/ec.c index 0f5b891..dba11cd 100644 --- a/util/ectool/ec.c +++ b/util/ectool/ec.c @@ -147,3 +147,9 @@ uint8_t ec_idx_read(uint16_t addr) return inb(lpc_idx + 3); } + +uint8_t ec_query(void) +{ + send_ec_command(0x84); + return recv_ec_data(); +} diff --git a/util/ectool/ec.h b/util/ectool/ec.h index a7b10e4..f25a3d9 100644 --- a/util/ectool/ec.h +++ b/util/ectool/ec.h @@ -50,4 +50,5 @@ int ec_write(uint8_t addr, uint8_t data); uint8_t ec_ext_read(uint16_t addr); int ec_ext_write(uint16_t addr, uint8_t data); uint8_t ec_idx_read(uint16_t addr); +uint8_t ec_query(void); #endif diff --git a/util/ectool/ectool.c b/util/ectool/ectool.c index a256390..cfb5bfc 100644 --- a/util/ectool/ectool.c +++ b/util/ectool/ectool.c @@ -46,20 +46,21 @@ void print_version(void) void print_usage(const char *name) { - printf("usage: %s [-vh?Vid] [-w 0x<addr> -z 0x<data>]\n", name); + printf("usage: %s [-vh?Vidq] [-w 0x<addr> -z 0x<data>]\n", name); printf("\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" " -V | --verbose: print debug information\n" " -d | --dump: print RAM\n" " -i | --idx: print IDX RAM\n" + " -q | --query: print query byte\n" " -w <addr in hex> write to addr\n" " -z <data in hex> write to data\n" "\n"); exit(1); } -int verbose = 0, dump_idx = 0, dump_ram = 0; +int verbose = 0, dump_idx = 0, dump_ram = 0, dump_query = 0; int main(int argc, char *argv[]) { @@ -72,10 +73,11 @@ int main(int argc, char *argv[]) {"help", 0, 0, 'h'}, {"verbose", 0, 0, 'V'}, {"idx", 0, 0, 'i'}, + {"query", 0, 0, 'q'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "vh?Vidw:z:", + while ((opt = getopt_long(argc, argv, "vh?Vidqw:z:", long_options, &option_index)) != EOF) { switch (opt) { case 'v': @@ -97,6 +99,9 @@ int main(int argc, char *argv[]) case 'd': dump_ram = 1; break; + case 'q': + dump_query = 1; + break; case 'h': case '?': default: @@ -118,7 +123,7 @@ int main(int argc, char *argv[]) } /* preserve default - dump_ram if nothing selected */ - if (!dump_ram && !dump_idx) { + if (!dump_ram && !dump_idx && !dump_query) { dump_ram = 1; } @@ -132,6 +137,10 @@ int main(int argc, char *argv[]) printf("\n\n"); } + if (dump_query) { + printf("EC QUERY %02x\n", ec_query()); + } + if (dump_idx) { printf("EC IDX RAM:\n"); for (i = 0; i < 0x10000; i++) {

1 0

New patch to review for coreboot: bbac79d inteltool: add ICH8M-E support
by Lubomir Rintel 02 Mar '15

02 Mar '15

Lubomir Rintel (lkundrak(a)v3.sk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8568 -gerrit commit bbac79da8d88a170d0b64bf22bbbe6539492da67 Author: Lubomir Rintel <lkundrak(a)v3.sk> Date: Sun Mar 1 10:14:15 2015 +0100 inteltool: add ICH8M-E support Tested on a Lenovo X61. Change-Id: I047f5a029d9be9fe6a000e2b45be44c7f14b33d7 Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk> --- 3rdparty | 2 +- util/inteltool/gpio.c | 1 + util/inteltool/inteltool.c | 1 + util/inteltool/inteltool.h | 1 + util/inteltool/powermgt.c | 1 + util/inteltool/rootcmplx.c | 1 + util/inteltool/spi.c | 1 + 7 files changed, 7 insertions(+), 1 deletion(-) diff --git a/3rdparty b/3rdparty index 5eb7a9c..45f0c04 160000 --- a/3rdparty +++ b/3rdparty @@ -1 +1 @@ -Subproject commit 5eb7a9cf0897134f2fbe6d32b3b6e45b7981932f +Subproject commit 45f0c04fd788fb29d9e303b2b2d1657ddb03448a diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 97dc5e5..aaacd57 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -959,6 +959,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) break; case PCI_DEVICE_ID_INTEL_ICH8: case PCI_DEVICE_ID_INTEL_ICH8M: + case PCI_DEVICE_ID_INTEL_ICH8ME: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = ich8_gpio_registers; size = ARRAY_SIZE(ich8_gpio_registers); diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 38ab061..1a6bda2 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -95,6 +95,7 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9M, "ICH9M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9ME, "ICH9M-E" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8ME, "ICH8M-E" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8, "ICH8" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10, "NM10" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 3f22641..3014b3e 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -53,6 +53,7 @@ #define PCI_DEVICE_ID_INTEL_NM10 0x27bc #define PCI_DEVICE_ID_INTEL_ICH8 0x2810 #define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 +#define PCI_DEVICE_ID_INTEL_ICH8ME 0x2811 #define PCI_DEVICE_ID_INTEL_ICH9DH 0x2912 #define PCI_DEVICE_ID_INTEL_ICH9DO 0x2914 #define PCI_DEVICE_ID_INTEL_ICH9R 0x2916 diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 579524b..2cefabe 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -736,6 +736,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) break; case PCI_DEVICE_ID_INTEL_ICH8: case PCI_DEVICE_ID_INTEL_ICH8M: + case PCI_DEVICE_ID_INTEL_ICH8ME: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich8_pm_registers; size = ARRAY_SIZE(ich8_pm_registers); diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index 5cf3ebd..ec2c3a8 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -38,6 +38,7 @@ int print_rcba(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_ICH7MDH: case PCI_DEVICE_ID_INTEL_ICH8: case PCI_DEVICE_ID_INTEL_ICH8M: + case PCI_DEVICE_ID_INTEL_ICH8ME: case PCI_DEVICE_ID_INTEL_ICH9DH: case PCI_DEVICE_ID_INTEL_ICH9DO: case PCI_DEVICE_ID_INTEL_ICH9R: diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index 3d5ddc3..e4a77b6 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -111,6 +111,7 @@ int print_spibar(struct pci_dev *sb) { case PCI_DEVICE_ID_INTEL_ICH7MDH: case PCI_DEVICE_ID_INTEL_ICH8: case PCI_DEVICE_ID_INTEL_ICH8M: + case PCI_DEVICE_ID_INTEL_ICH8ME: case PCI_DEVICE_ID_INTEL_ICH9DH: case PCI_DEVICE_ID_INTEL_ICH9DO: case PCI_DEVICE_ID_INTEL_ICH9R:

1 0

Patch merged into coreboot/master: 280a29d devicetree: Drop redundant scan_bus() ops
by gerrit＠coreboot.org 01 Mar '15

01 Mar '15

the following patch was just integrated into master: commit 280a29d5bb5ea53ae92380a95cf8eb4543f96749 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 25 10:30:42 2015 +0200 devicetree: Drop redundant scan_bus() ops Change-Id: If96e0843f507b9f1db9977b5d0c47f5ed1c59999 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8533 Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8533 for details. -gerrit

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coreboot-gerrit March 2015