coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 1c69ce6 timestamp: use wrapper macro for romstage static variables
by Stefan Reinauer 04 Mar '15

04 Mar '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8603 -gerrit commit 1c69ce630a508ed58338c933d33a18603761c3fd Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Mar 4 20:20:19 2015 +0100 timestamp: use wrapper macro for romstage static variables Keeping this up as a reminder that there's a TODO. Change-Id: Ic567b93f14f96154fe038471767339cc5fbfc767 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/lib/timestamp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 67635f8..844a061 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -55,7 +55,7 @@ static void timestamp_real_init(uint64_t base) void timestamp_add(enum timestamp_id id, uint64_t ts_time) { struct timestamp_entry *tse; - struct timestamp_table *ts_table = NULL; + MAYBE_STATIC struct timestamp_table *ts_table = NULL; if (!boot_cpu()) return;

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Patch set updated for coreboot: 2cfae54 Add and consistently use wrapper macro for romstage static variables
by Stefan Reinauer 04 Mar '15

04 Mar '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8055 -gerrit commit 2cfae5490aced293a5351eea8b240f8bb80cc55b Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Jun 6 16:10:56 2014 -0700 Add and consistently use wrapper macro for romstage static variables x86 systems run their romstage as execute-in-place from flash, which prevents them from having writable data segments. In several code pieces that get linked into both romstage and ramstage, this has been worked around by using a local variable and having the 'static' storage class guarded by #ifndef __PRE_RAM__. However, x86 is the only architecture using execute-in-place (for now), so it does not make sense to impose the restriction globally. Rather than fixing the #ifdef at every occurrence, this should really be wrapped in a way that makes it easier to modify in a single place. The chromeos/cros_vpd.c file already had a nice approach for a wrapper macro, but unfortunately restricted it to one file... this patch moves it to stddef.h and employs it consistently throughout coreboot. BRANCH=nyan BUG=None TEST=Measured boot time on Nyan_Big before and after, confirmed that it gained 6ms from caching the FMAP in vboot_loader.c. Original-Change-Id: Ia53b94ab9c6a303b979db7ff20b79e14bc51f9f8 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203033 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit c8127e4ac9811517f6147cf019ba6a948cdaa4a5) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I44dacc10214351992b775aca52d6b776a74ee922 --- src/include/stddef.h | 7 +++++++ src/lib/lzma.c | 7 +------ src/vendorcode/google/chromeos/cros_vpd.c | 18 ++++-------------- src/vendorcode/google/chromeos/fmap.c | 5 +---- 4 files changed, 13 insertions(+), 24 deletions(-) diff --git a/src/include/stddef.h b/src/include/stddef.h index 3a030e1..60e3459 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -49,4 +49,11 @@ typedef unsigned int wint_t; #define ROMSTAGE_CONST #endif +/* Work around non-writable data segment in execute-in-place romstage on x86. */ +#if defined(__PRE_RAM__) && CONFIG_ARCH_X86 +#define MAYBE_STATIC +#else +#define MAYBE_STATIC static +#endif + #endif /* STDDEF_H */ diff --git a/src/lib/lzma.c b/src/lib/lzma.c index ea5f15f..8efa1e6 100644 --- a/src/lib/lzma.c +++ b/src/lib/lzma.c @@ -24,12 +24,7 @@ unsigned long ulzma(unsigned char * src, unsigned char * dst) int res; CLzmaDecoderState state; SizeT mallocneeds; -#if !defined(__PRE_RAM__) - /* in ramstage, this can go in BSS */ - static -#endif - /* in pre-ram, it must go on the stack */ - unsigned char scratchpad[15980]; + MAYBE_STATIC unsigned char scratchpad[15980]; unsigned char *cp; memcpy(properties, src, LZMA_PROPERTIES_SIZE); diff --git a/src/vendorcode/google/chromeos/cros_vpd.c b/src/vendorcode/google/chromeos/cros_vpd.c index 26b01ee..df2b5bf 100644 --- a/src/vendorcode/google/chromeos/cros_vpd.c +++ b/src/vendorcode/google/chromeos/cros_vpd.c @@ -15,16 +15,6 @@ #include "lib_vpd.h" #include "vpd_tables.h" -/* - * Static variables are available in ramstage (all platforms), and romstage for - * some platforms (ex, ARM, which uses SRAM). - */ -#if defined(__PRE_RAM__) && CONFIG_ARCH_X86 -#define STATIC_VAR -#else -#define STATIC_VAR static -#endif - /* Currently we only support Google VPD 2.0, which has a fixed offset. */ enum { GOOGLE_VPD_2_0_OFFSET = 0x600, @@ -39,10 +29,10 @@ struct vpd_gets_arg { static int cros_vpd_load(uint8_t **vpd_address, int32_t *vpd_size) { - STATIC_VAR int cached = 0; - STATIC_VAR uint8_t *cached_address = NULL; - STATIC_VAR int32_t cached_size = 0; - STATIC_VAR int result = -1; + MAYBE_STATIC int cached = 0; + MAYBE_STATIC uint8_t *cached_address = NULL; + MAYBE_STATIC int32_t cached_size = 0; + MAYBE_STATIC int result = -1; struct google_vpd_info info; int32_t base; diff --git a/src/vendorcode/google/chromeos/fmap.c b/src/vendorcode/google/chromeos/fmap.c index d758f57..a8425c0 100644 --- a/src/vendorcode/google/chromeos/fmap.c +++ b/src/vendorcode/google/chromeos/fmap.c @@ -92,10 +92,7 @@ const struct fmap_area *find_fmap_area(const struct fmap *fmap, int find_fmap_entry(const char name[], void **pointer) { -#ifndef __PRE_RAM__ - static -#endif - const struct fmap *fmap = NULL; + MAYBE_STATIC const struct fmap *fmap = NULL; const struct fmap_area *area; void *base = NULL;

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New patch to review for coreboot: 7f92886 As part of our standardization of license text, following the recommendation of Eben Moglen, put this license at the top level.
by Ronald G. Minnich 04 Mar '15

04 Mar '15

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8602 -gerrit commit 7f9288693a0e8d6f1176f8d94a728e1b2cdc889d Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Mar 4 10:52:38 2015 -0800 As part of our standardization of license text, following the recommendation of Eben Moglen, put this license at the top level. New files should include the following text: /* * This file is part of coreboot. It is subject to the license * terms in the LICENSE file found in the top-level directory of this * distribution and at [[ URL to be set at coreboot.org]]. No * part of coreboot, including this file, may be copied, * modified, propagated, or distributed except according to the terms contained * in the LICENSE file. */ I'll fix the URL and such on the wiki assuming this file is approved. Change-Id: I089e35d3895de8cd2aa0a593d5bafc657c738e8e Signed-off-by: Ronald G. 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Patch merged into coreboot/master: bc772c3 arm64: Set 16 byte alignment and ramstage start address
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit bc772c3f3da6152d09e60be4e4e72a782cfa4201 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 10 17:04:25 2014 -0500 arm64: Set 16 byte alignment and ramstage start address To align with arm use the RAMSTAGE_BASE Kconfig option for start of ramstage. Also, use 16-byte alignment for the start and end of the sections. 4 bytes were previously used, but it definitely seems more appropriate to at least have the heap handing out 16-byte aligned pointers. BUG=chrome-os-partner:29923 BRANCH=None TEST=Built and booted through attempting to load payload Original-Change-Id: I39329055696ae21a9ed1d9a64769981ab4dcdddd Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207432 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 6291f3bed705154743be78a881a26dfc9d041c5e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ic280b4c6435c4f8e0e783fe5bd4694832ce9b550 Reviewed-on: http://review.coreboot.org/8588 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8588 for details. -gerrit

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Patch merged into coreboot/master: 00263d0 arm64: remove assembly code string functions
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit 00263d0d8ee23bbe60ea359ea9cb33d551688980 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 10 17:01:22 2014 -0500 arm64: remove assembly code string functions Inconsistent progress was observed running ramstage. It was determined that the hand-coded assembly functions were causing issues. Some of the comments seems suspect about the hardware taking care of alignment. The prudent thing to do is to use the C ones. Optimization can come later after maturity. BUG=chrome-os-partner:29923 BRANCH=None TEST=Built and booted to attempting to payload Original-Change-Id: I4137adf9b36b638ed207e4efd57adaac64c6a6c1 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207431 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 2762e478c6b59dd30c59aa87a922d0f78c00c0c4) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Id3196b0c2bf41a21db31f999ba437d118875a236 Reviewed-on: http://review.coreboot.org/8587 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8587 for details. -gerrit

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Patch set updated for coreboot: 05dc976 arm64: Set 16 byte alignment and ramstage start address
by Marc Jones 04 Mar '15

04 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8588 -gerrit commit 05dc9766cb00d193679643146ff72052c3f940c6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 10 17:04:25 2014 -0500 arm64: Set 16 byte alignment and ramstage start address To align with arm use the RAMSTAGE_BASE Kconfig option for start of ramstage. Also, use 16-byte alignment for the start and end of the sections. 4 bytes were previously used, but it definitely seems more appropriate to at least have the heap handing out 16-byte aligned pointers. BUG=chrome-os-partner:29923 BRANCH=None TEST=Built and booted through attempting to load payload Original-Change-Id: I39329055696ae21a9ed1d9a64769981ab4dcdddd Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207432 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 6291f3bed705154743be78a881a26dfc9d041c5e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ic280b4c6435c4f8e0e783fe5bd4694832ce9b550 --- src/arch/arm64/ramstage.ld | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/src/arch/arm64/ramstage.ld b/src/arch/arm64/ramstage.ld index 19c9309..de13fcc 100644 --- a/src/arch/arm64/ramstage.ld +++ b/src/arch/arm64/ramstage.ld @@ -32,7 +32,7 @@ PHDRS SECTIONS { - . = CONFIG_SYS_SDRAM_BASE; + . = CONFIG_RAMSTAGE_BASE; /* First we place the code and read only data (typically const declared). * This could theoretically be placed in rom. */ @@ -56,11 +56,11 @@ SECTIONS .rodata : { _rodata = .; - . = ALIGN(4); + . = ALIGN(16); console_drivers = .; KEEP(*(.rodata.console_drivers)); econsole_drivers = . ; - . = ALIGN(4); + . = ALIGN(16); pci_drivers = . ; KEEP(*(.rodata.pci_driver)); epci_drivers = . ; @@ -75,7 +75,7 @@ SECTIONS /* kevinh/Ispiri - Added an align, because the objcopy tool * incorrectly converts sections that are not long word aligned. */ - . = ALIGN(4); + . = ALIGN(16); _erodata = .; } @@ -100,6 +100,7 @@ SECTIONS *(.bss) *(.sbss) *(COMMON) + . = ALIGN(16); } _ebss = .; _end = .; @@ -108,13 +109,13 @@ SECTIONS * this line. */ - _heap = .; - .heap . : { - /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ - . = CONFIG_HEAP_SIZE ; - . = ALIGN(4); - } - _eheap = .; + _heap = .; + .heap . : { + /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ + . = CONFIG_HEAP_SIZE ; + . = ALIGN(16); + } + _eheap = .; /* arm64 chipsets need to define CONFIG_RAMSTAGE_STACK_(TOP|BOTTOM) */ _stack = CONFIG_RAMSTAGE_STACK_BOTTOM;

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Patch merged into coreboot/master: 0df877a arm64: use one stage_entry for all stages
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit 0df877a65ac6563f1e46eea9e15e34a366d7105f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 10 12:40:30 2014 -0500 arm64: use one stage_entry for all stages Ramstage needs an assembly entry point for setting up the initial state of the CPU. Therefore, a function is provided, arm64_el3_startup(), that bootstraps the state of the processor, initializes the stack pointer, and branches to a defined entry symbol. To make this work without adding too much preprocessor macro conditions provide _stack and _estack for all the stages. Currently the entry point after initialization is 'main', however it can be changed/extended to do more work such as seeding the stack contents with tombstones, etc. It should be noted that romstage and bootblock weren't tested. Only ramstage is known to work. BUG=chrome-os-partner:29923 BRANCH=None TEST=Brought up 64-bit ramstage on rush. Original-Change-Id: I1f07d5b6656e13e6667b038cdc1f4be8843d1960 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207262 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 7850ee3a7bf48c05f2e64147edb92161f8308f19) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ia87697f49638c8c249215d441d95f1ec621e0949 Reviewed-on: http://review.coreboot.org/8585 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8585 for details. -gerrit

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Patch merged into coreboot/master: 6ba1b62 arm64: ensure vital sections aren't garbage collected
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit 6ba1b628eeabef60ea6b0abeea0d2825ddf99dfe Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 10 12:32:17 2014 -0500 arm64: ensure vital sections aren't garbage collected The driver structures live in special sections which have no direct reference to the symbols. Therefore, when garbage collecting sections in the linker the drivers are tossed out resulting in no drivers being linked into ramstage. Fix this by adding the KEEP() directive to those special sections. BUG=chrome-os-partner:29923 BRANCH=None TEST=Built and noted console starts working in ramstage. Original-Change-Id: Iaa0fd428bf975c82d4e6b0e75a17e6fd231fbaa9 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207261 Original-Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 7c1a3e63e398755de0c77524a0483e6f1019aac0) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I1e30e73be754ec849cb3cfac3bcb12e95b0f60d4 Reviewed-on: http://review.coreboot.org/8584 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8584 for details. -gerrit

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Patch set updated for coreboot: a7a9bcf arm64: ensure vital sections aren't garbage collected
by Marc Jones 04 Mar '15

04 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8584 -gerrit commit a7a9bcf3f822362b61278f2df4d232a21001fd01 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 10 12:32:17 2014 -0500 arm64: ensure vital sections aren't garbage collected The driver structures live in special sections which have no direct reference to the symbols. Therefore, when garbage collecting sections in the linker the drivers are tossed out resulting in no drivers being linked into ramstage. Fix this by adding the KEEP() directive to those special sections. BUG=chrome-os-partner:29923 BRANCH=None TEST=Built and noted console starts working in ramstage. Original-Change-Id: Iaa0fd428bf975c82d4e6b0e75a17e6fd231fbaa9 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207261 Original-Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 7c1a3e63e398755de0c77524a0483e6f1019aac0) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I1e30e73be754ec849cb3cfac3bcb12e95b0f60d4 --- src/arch/arm64/ramstage.ld | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/arch/arm64/ramstage.ld b/src/arch/arm64/ramstage.ld index e878820..5dc55ba 100644 --- a/src/arch/arm64/ramstage.ld +++ b/src/arch/arm64/ramstage.ld @@ -49,7 +49,7 @@ SECTIONS .ctors : { . = ALIGN(0x100); __CTOR_LIST__ = .; - *(.ctors); + KEEP(*(.ctors)); LONG(0); __CTOR_END__ = .; } @@ -58,17 +58,17 @@ SECTIONS _rodata = .; . = ALIGN(4); console_drivers = .; - *(.rodata.console_drivers) + KEEP(*(.rodata.console_drivers)); econsole_drivers = . ; . = ALIGN(4); pci_drivers = . ; - *(.rodata.pci_driver) + KEEP(*(.rodata.pci_driver)); epci_drivers = . ; cpu_drivers = . ; - *(.rodata.cpu_driver) + KEEP(*(.rodata.cpu_driver)); ecpu_drivers = . ; _bs_init_begin = .; - *(.bs_init) + KEEP(*(.bs_init)); _bs_init_end = .; *(.rodata) *(.rodata.*)

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Patch merged into coreboot/master: e5d014c coreboot t132: Stack init re-work
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit e5d014c29abc724e15c23c7a33a7d1742277e057 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 7 11:45:15 2014 -0700 coreboot t132: Stack init re-work 1) In order to avoid stack from overflowing during ramstage decompression, initialize stack right at the beginning of romstage. 2) Declare different Kconfig options for stack at each stage. 3) Provide a macro that does stack seeding if required and calls appropriate function. BUG=None BRANCH=None TEST=Compiles and runs successfully on rush. Original-Change-Id: I55d6ce59ea91affba3e86d68406921497c83fb52 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206880 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 5e32d73803a2a9d222fcc4ca5f58efd3abe95d34) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ib833a1badb170a33cbf20d232019425b59db60cd Reviewed-on: http://review.coreboot.org/8583 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8583 for details. -gerrit

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