coreboot-gerrit March 2015

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Patch set updated for coreboot: 95f08b0 t132: bring up 64-bit denver core
by Marc Jones 05 Mar '15

05 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8586 -gerrit commit 95f08b0a41504ae06b1ad3a2b3675d0dc5609a1e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 10 12:50:27 2014 -0500 t132: bring up 64-bit denver core The startup sequence for cpu0 is implemented while also providing a trampoline for transitioning to 64-bit mode because the denver cores on t132 come out of cold reset in 32-bit mode. Mainboard callbacks are provided for providing the board-specific bits of the bringup sequence. BUG=chrome-os-partner:29923 BRANCH=None TEST=Built and booted through ramstage. Original-Change-Id: I50755fb6b06db994af8667969d8493f214a70aae Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207263 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer(a)google.com> (cherry picked from commit 17f09bf4bdb43986c19067ca8fd65d4c5365a7c6) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I14d99c24dd6e29a4584c8c548c4b26c92b6ade97 --- src/mainboard/google/rush/Makefile.inc | 1 + src/mainboard/google/rush/romstage.c | 29 ++++++ src/soc/nvidia/tegra132/Makefile.inc | 1 + src/soc/nvidia/tegra132/ccplex.c | 132 +++++++++++++++++++++++++ src/soc/nvidia/tegra132/ccplex.h | 6 ++ src/soc/nvidia/tegra132/include/soc/romstage.h | 26 +++++ src/soc/nvidia/tegra132/power.c | 57 +++++++++++ src/soc/nvidia/tegra132/power.h | 6 +- src/soc/nvidia/tegra132/romstage.c | 10 +- 9 files changed, 261 insertions(+), 7 deletions(-) diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc index 6f4a774..3c2b5da 100644 --- a/src/mainboard/google/rush/Makefile.inc +++ b/src/mainboard/google/rush/Makefile.inc @@ -33,6 +33,7 @@ bootblock-y += pmic.c bootblock-y += reset.c romstage-y += reset.c +romstage-y += romstage.c romstage-y += sdram_configs.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c new file mode 100644 index 0000000..bb173c0 --- /dev/null +++ b/src/mainboard/google/rush/romstage.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/romstage.h> + +void mainboard_configure_pmc(void) +{ +} + +void mainboard_enable_vdd_cpu(void) +{ + /* VDD_CPU is already enabled in bootblock. */ +} diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 8c085a9..252f1a2 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -27,6 +27,7 @@ romstage-y += i2c.c romstage-y += dma.c romstage-y += monotonic_timer.c romstage-y += romstage.c +romstage-y += power.c romstage-y += sdram.c romstage-y += sdram_lp0.c romstage-y += ../tegra/gpio.c diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c index b774630..9f85707 100644 --- a/src/soc/nvidia/tegra132/ccplex.c +++ b/src/soc/nvidia/tegra132/ccplex.c @@ -23,11 +23,15 @@ #include <cbfs.h> #include <timer.h> #include <soc/addressmap.h> +#include <soc/romstage.h> #include "clk_rst.h" #include "ccplex.h" +#include "flow.h" #include "mc.h" #include "pmc.h" +#include "power.h" +#define EVP_CPU_RESET_VECTOR (void *)(uintptr_t)(TEGRA_EVP_BASE + 0x100) #define CLK_RST_REGS (void *)(uintptr_t)(TEGRA_CLK_RST_BASE) #define PMC_REGS (void *)(uintptr_t)(TEGRA_PMC_BASE) #define MTS_FILE_NAME "mts" @@ -105,3 +109,131 @@ int ccplex_load_mts(void) return ccplex_start(); } + +static void enable_cpu_clocks(void) +{ + struct clk_rst_ctlr * const clk_rst = CLK_RST_REGS; + uint32_t reg; + + reg = read32(&clk_rst->clk_enb_l_set); + reg |= CLK_ENB_CPU; + write32(reg, &clk_rst->clk_enb_l_set); + + reg = read32(&clk_rst->clk_enb_v_set); + reg |= SET_CLK_ENB_CPUG_ENABLE | SET_CLK_ENB_CPULP_ENABLE; + write32(reg, &clk_rst->clk_enb_v_set); +} + +static void enable_cpu_power_partitions(void) +{ + /* Bring up fast cluster, non-CPU, CPU0, and CPU1 partitions. */ + power_ungate_partition(POWER_PARTID_CRAIL); + power_ungate_partition(POWER_PARTID_C0NC); + power_ungate_partition(POWER_PARTID_CE0); + power_ungate_partition(POWER_PARTID_CE1); +} + + +static void request_ram_repair(void) +{ + struct flow_ctlr * const flow = (void *)(uintptr_t)TEGRA_FLOW_BASE; + const uint32_t req = 1 << 0; + const uint32_t sts = 1 << 1; + uint32_t reg; + struct mono_time t1, t2; + + printk(BIOS_DEBUG, "Requesting RAM repair.\n"); + + reg = read32(&flow->ram_repair); + reg |= req; + write32(reg, &flow->ram_repair); + + timer_monotonic_get(&t1); + while ((read32(&flow->ram_repair) & sts) != sts); + timer_monotonic_get(&t2); + + printk(BIOS_DEBUG, "RAM repair complete in %ld usecs.\n", + mono_time_diff_microseconds(&t1, &t2)); +} + +void ccplex_cpu_prepare(void) +{ + enable_cpu_clocks(); + enable_cpu_power_partitions(); + + mainboard_configure_pmc(); + mainboard_enable_vdd_cpu(); + + request_ram_repair(); +} + +static void start_cpu0(void) +{ + struct clk_rst_ctlr * const clk_rst = CLK_RST_REGS; + + /* Clear fast CPU partition reset. */ + write32(CRC_RST_CPUG_CLR_NONCPU, &clk_rst->rst_cpug_cmplx_clr); + + /* Clear reset of CPU0 components. */ + write32(CRC_RST_CPUG_CLR_CPU0 | + CRC_RST_CPUG_CLR_DBG0 | + CRC_RST_CPUG_CLR_CORE0 | + CRC_RST_CPUG_CLR_CX0 | + CRC_RST_CPUG_CLR_L2 | + CRC_RST_CPUG_CLR_PDBG, &clk_rst->rst_cpug_cmplx_clr); +} + +/* + * The Denver cores come up in aarch32 mode. In order to transition to + * 64-bit mode a write to the RMR (reset mangement register) with the + * AA64 bit (0) set while setting RR (reset request bit 1). + */ +static const uint32_t aarch32to64[] = { + 0xe3a00003, /* mov r0, #3 */ + 0xee0c0f50, /* mcr 15, 0, r0, cr12, cr0, {2} */ +}; + +static void load_aarch64_trampoline(void *addr) +{ + const size_t trampoline_size = sizeof(aarch32to64); + const void * const trampoline = &aarch32to64[0]; + + /* Copy trampoline into ram. */ + memcpy(addr, trampoline, trampoline_size); +} + +void ccplex_cpu_start(void *entry_addr) +{ + struct tegra_pmc_regs * const pmc = PMC_REGS; + void * const evp_cpu_reset_vector = EVP_CPU_RESET_VECTOR; + void *trampoline; + uint32_t entry_point; + + /* + * Just place the trampoline at the MTS_LOAD_ADDRESS. This assumes + * the program to run doesn't overlap this address. + */ + const uint32_t trampoline_addr = MTS_LOAD_ADDRESS; + trampoline = (void *)(uintptr_t)trampoline_addr; + + /* The arm entry points have bit 0 set if thumb code. Mask that off. */ + entry_point = (uint32_t)(uintptr_t)entry_addr; + + load_aarch64_trampoline(trampoline); + + /* Warm reset vector is pulled from the PMC scratch registers. */ + write32(entry_point, &pmc->secure_scratch34); + write32(0, &pmc->secure_scratch35); + + printk(BIOS_DEBUG, "Starting CPU0 @ %p trampolining to %08x.\n", + trampoline, entry_point); + + /* + * The Denver cores start in 32-bit mode. Therefore a trampoline + * is needed to get into 64-bit mode. Point the cold reset vector + * to the trampoline location. + */ + write32(trampoline_addr, evp_cpu_reset_vector); + + start_cpu0(); +} diff --git a/src/soc/nvidia/tegra132/ccplex.h b/src/soc/nvidia/tegra132/ccplex.h index 6b9699c..c3f8a04 100644 --- a/src/soc/nvidia/tegra132/ccplex.h +++ b/src/soc/nvidia/tegra132/ccplex.h @@ -22,7 +22,13 @@ #define MTS_LOAD_ADDRESS 0x82000000 +/* Prepare the clocks and rails to start the cpu. */ +void ccplex_cpu_prepare(void); + /* Loads the MTS microcode. Return 0 on success, < 0 on error. */ int ccplex_load_mts(void); +/* Start cpu0 and have it start executing at entry_addr */ +void ccplex_cpu_start(void *entry_addr); + #endif /* __SOC_NVIDIA_TEGRA132_CCPLEX_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/romstage.h b/src/soc/nvidia/tegra132/include/soc/romstage.h new file mode 100644 index 0000000..f9eac26 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/romstage.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ +#define __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ + +void mainboard_configure_pmc(void); +void mainboard_enable_vdd_cpu(void); + +#endif /* __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ */ diff --git a/src/soc/nvidia/tegra132/power.c b/src/soc/nvidia/tegra132/power.c new file mode 100644 index 0000000..5c7cc05 --- /dev/null +++ b/src/soc/nvidia/tegra132/power.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <soc/addressmap.h> + +#include "pmc.h" +#include "power.h" + +static struct tegra_pmc_regs * const pmc = (void *)TEGRA_PMC_BASE; + +static int partition_powered(int id) +{ + return read32(&pmc->pwrgate_status) & (0x1 << id); +} + +void power_ungate_partition(uint32_t id) +{ + printk(BIOS_INFO, "Ungating power partition %d.\n", id); + + if (!partition_powered(id)) { + uint32_t pwrgate_toggle = read32(&pmc->pwrgate_toggle); + pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK); + pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT); + pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START; + write32(pwrgate_toggle, &pmc->pwrgate_toggle); + + /* Wait for the request to be accepted. */ + while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START) + ; + printk(BIOS_DEBUG, "Power gate toggle request accepted.\n"); + + /* Wait for the partition to be powered. */ + while (!partition_powered(id)) + ; + } + + printk(BIOS_INFO, "Ungated power partition %d.\n", id); +} diff --git a/src/soc/nvidia/tegra132/power.h b/src/soc/nvidia/tegra132/power.h index 9283b55..b36f91f 100644 --- a/src/soc/nvidia/tegra132/power.h +++ b/src/soc/nvidia/tegra132/power.h @@ -20,10 +20,8 @@ #ifndef __SOC_NVIDIA_TEGRA132_POWER_H__ #define __SOC_NVIDIA_TEGRA132_POWER_H__ -// This function does not enable the external power to the rail, it enables -// the rail itself internal to the SOC. -void power_enable_cpu_rail(void); +#include "pmc.h" -void power_ungate_cpu(void); +void power_ungate_partition(uint32_t id); #endif /* __SOC_NVIDIA_TEGRA132_POWER_H__ */ diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index 6d51403..1d6acca 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -39,12 +39,16 @@ void romstage(void) sdram_init(get_sdram_config()); printk(BIOS_INFO, "T132 romstage: sdram_init done\n"); + ccplex_cpu_prepare(); + printk(BIOS_INFO, "T132 romstage: cpu prepare done\n"); + ccplex_load_mts(); printk(BIOS_INFO, "T132 romstage: MTS loading done\n"); - while (1); - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX "/ramstage"); - stage_exit(entry); + + ccplex_cpu_start(entry); + + while (1); }

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Patch set updated for coreboot: e893989 Include LICENSE.gpl in the tree.
by Ronald G. Minnich 05 Mar '15

05 Mar '15

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8602 -gerrit commit e89398943ff8d57c676db058331fb58d8960fda8 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Mar 4 10:52:38 2015 -0800 Include LICENSE.gpl in the tree. As part of our standardization of license text, following the recommendation of Eben Moglen, put this license at the top level. I'll fix the URL and such on the wiki assuming this file is approved. I'm looking forward to *that* discussion. Change-Id: I089e35d3895de8cd2aa0a593d5bafc657c738e8e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- LICENSE.gpl | 339 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 339 insertions(+) diff --git a/LICENSE.gpl b/LICENSE.gpl new file mode 100644 index 0000000..d159169 --- /dev/null +++ b/LICENSE.gpl @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. 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For software which is copyrighted by the Free +Software Foundation, write to the Free Software Foundation; we sometimes +make exceptions for this. Our decision will be guided by the two goals +of preserving the free status of all derivatives of our free software and +of promoting the sharing and reuse of software generally. + + NO WARRANTY + + 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + <one line to give the program's name and a brief idea of what it does.> + Copyright (C) <year> <name of author> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + <signature of Ty Coon>, 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License.

1 0

Patch set updated for coreboot: 55fdb75 Include LICENSE.gpl in the tree.
by Ronald G. Minnich 05 Mar '15

05 Mar '15

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8602 -gerrit commit 55fdb7521569fdd1ba79c19ad5cfbfc35e947106 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Mar 4 10:52:38 2015 -0800 Include LICENSE.gpl in the tree. As part of our standardization of license text, following the recommendation of Eben Moglen, put this license at the top level. I'll fix the URL and such on the wiki assuming this file is approved. Change-Id: I089e35d3895de8cd2aa0a593d5bafc657c738e8e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- LICENSE.gpl | 339 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 339 insertions(+) diff --git a/LICENSE.gpl b/LICENSE.gpl new file mode 100644 index 0000000..d159169 --- /dev/null +++ b/LICENSE.gpl @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. 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The Free Software Foundation may publish revised and/or new versions +of the General Public License from time to time. Such new versions will +be similar in spirit to the present version, but may differ in detail to +address new problems or concerns. + +Each version is given a distinguishing version number. If the Program +specifies a version number of this License which applies to it and "any +later version", you have the option of following the terms and conditions +either of that version or of any later version published by the Free +Software Foundation. If the Program does not specify a version number of +this License, you may choose any version ever published by the Free Software +Foundation. + + 10. If you wish to incorporate parts of the Program into other free +programs whose distribution conditions are different, write to the author +to ask for permission. For software which is copyrighted by the Free +Software Foundation, write to the Free Software Foundation; we sometimes +make exceptions for this. Our decision will be guided by the two goals +of preserving the free status of all derivatives of our free software and +of promoting the sharing and reuse of software generally. + + NO WARRANTY + + 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + <one line to give the program's name and a brief idea of what it does.> + Copyright (C) <year> <name of author> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + <signature of Ty Coon>, 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License.

1 0

New patch to review for coreboot: ec681fe AGESA: Split S3 support file
by Kyösti Mälkki 04 Mar '15

04 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8607 -gerrit commit ec681fe4f8a408b471eca6bceb3f3975a04aba94 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 1 17:51:51 2015 +0200 AGESA: Split S3 support file Separate it to low-memory backup in romstage and MTRR recovery in ramstage. How much of the MTRR part we really need will be resolved later. Change-Id: Ic64b3f74cf6ef0954eda6e84754745de81c465b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/Makefile.inc | 2 +- src/cpu/amd/agesa/s3_mtrr.c | 138 +++++++++++++++++++++++++++++++++++++++++ src/cpu/amd/agesa/s3_resume.c | 129 -------------------------------------- 3 files changed, 139 insertions(+), 130 deletions(-) diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index a434381..173ba80 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -25,7 +25,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) += family15rl subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb romstage-y += s3_resume.c -ramstage-y += s3_resume.c +ramstage-y += s3_mtrr.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/s3_mtrr.c b/src/cpu/amd/agesa/s3_mtrr.c new file mode 100644 index 0000000..a18e9b7 --- /dev/null +++ b/src/cpu/amd/agesa/s3_mtrr.c @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/x86/cache.h> +#include <string.h> +#include "s3_resume.h" + +static void write_mtrr(u8 **p_nvram_pos, unsigned idx) +{ + msr_t msr_data; + msr_data = rdmsr(idx); + + memcpy(*p_nvram_pos, &msr_data, sizeof(msr_data)); + *p_nvram_pos += sizeof(msr_data); +} + +void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size) +{ + u8 *nvram_pos = mtrr_store; + msr_t msr_data; + u32 i; + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYSCFG_MSR); + msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr_data); + + /* Fixed MTRRs */ + write_mtrr(&nvram_pos, 0x250); + write_mtrr(&nvram_pos, 0x258); + write_mtrr(&nvram_pos, 0x259); + + for (i = 0x268; i < 0x270; i++) + write_mtrr(&nvram_pos, i); + + /* Disable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYSCFG_MSR); + msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr_data); + + /* Variable MTRRs */ + for (i = 0x200; i < 0x210; i++) + write_mtrr(&nvram_pos, i); + + /* SYSCFG_MSR */ + write_mtrr(&nvram_pos, SYSCFG_MSR); + /* TOM */ + write_mtrr(&nvram_pos, 0xC001001A); + /* TOM2 */ + write_mtrr(&nvram_pos, 0xC001001D); + + *mtrr_store_size = nvram_pos - (u8*) mtrr_store; +} + +void restore_mtrr(void) +{ + volatile u32 *msrPtr = (u32 *) OemS3Saved_MTRR_Storage(); + u32 msr; + msr_t msr_data; + + if (!msrPtr) + return; + + disable_cache(); + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYSCFG_MSR); + msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr_data); + + /* Now restore the Fixed MTRRs */ + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x250, msr_data); + + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x258, msr_data); + + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x259, msr_data); + + for (msr = 0x268; msr <= 0x26F; msr++) { + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(msr, msr_data); + } + + /* Disable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYSCFG_MSR); + msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr_data); + + /* Restore the Variable MTRRs */ + for (msr = 0x200; msr <= 0x20F; msr++) { + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(msr, msr_data); + } + + /* Restore SYSCFG MTRR */ + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(SYSCFG_MSR, msr_data); +} diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 501e29f..5e1325e 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -17,8 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <AGESA.h> -#include <Lib/amdlib.h> #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -26,85 +24,10 @@ #include <cpu/amd/mtrr.h> #include <cpu/x86/cache.h> #include <cbmem.h> -#include <device/device.h> -#include <arch/io.h> -#include <arch/acpi.h> #include <string.h> -#include "Porting.h" #include <northbridge/amd/agesa/BiosCallOuts.h> #include "s3_resume.h" - -#ifndef __PRE_RAM__ - -void restore_mtrr(void) -{ - volatile u32 *msrPtr = (u32 *) OemS3Saved_MTRR_Storage(); - u32 msr; - msr_t msr_data; - - if (!msrPtr) - return; - - disable_cache(); - - /* Enable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYS_CFG); - msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYS_CFG, msr_data); - - /* Now restore the Fixed MTRRs */ - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(0x250, msr_data); - - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(0x258, msr_data); - - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(0x259, msr_data); - - for (msr = 0x268; msr <= 0x26F; msr++) { - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(msr, msr_data); - } - - /* Disable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYS_CFG); - msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYS_CFG, msr_data); - - /* Restore the Variable MTRRs */ - for (msr = 0x200; msr <= 0x20F; msr++) { - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(msr, msr_data); - } - - /* Restore SYSCFG MTRR */ - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(SYS_CFG, msr_data); -} - -#endif - -#ifdef __PRE_RAM__ static void *backup_resume(void) { void *resume_backup_memory; @@ -136,58 +59,7 @@ static void move_stack_high_mem(void) (high_stack - BSP_STACK_BASE_ADDR) :); } -#endif - -#ifndef __PRE_RAM__ -static void write_mtrr(u8 **p_nvram_pos, unsigned idx) -{ - msr_t msr_data; - msr_data = rdmsr(idx); - - memcpy(*p_nvram_pos, &msr_data, sizeof(msr_data)); - *p_nvram_pos += sizeof(msr_data); -} - -void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size) -{ - u8 *nvram_pos = mtrr_store; - msr_t msr_data; - u32 i; - - /* Enable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYS_CFG); - msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYS_CFG, msr_data); - - /* Fixed MTRRs */ - write_mtrr(&nvram_pos, 0x250); - write_mtrr(&nvram_pos, 0x258); - write_mtrr(&nvram_pos, 0x259); - - for (i = 0x268; i < 0x270; i++) - write_mtrr(&nvram_pos, i); - - /* Disable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYS_CFG); - msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYS_CFG, msr_data); - - /* Variable MTRRs */ - for (i = 0x200; i < 0x210; i++) - write_mtrr(&nvram_pos, i); - - /* SYS_CFG */ - write_mtrr(&nvram_pos, 0xC0010010); - /* TOM */ - write_mtrr(&nvram_pos, 0xC001001A); - /* TOM2 */ - write_mtrr(&nvram_pos, 0xC001001D); - - *mtrr_store_size = nvram_pos - (u8*) mtrr_store; -} -#endif -#ifdef __PRE_RAM__ static void set_resume_cache(void) { msr_t msr; @@ -237,4 +109,3 @@ void prepare_for_resume(void) printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); } -#endif

1 0

New patch to review for coreboot: d26fa4c AGESA: Refactor OEM S3 storage
by Kyösti Mälkki 04 Mar '15

04 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8606 -gerrit commit d26fa4c610971402c72c1792ac2adc4d0a994017 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Dec 16 19:50:47 2014 +0200 AGESA: Refactor OEM S3 storage Use function prototypes that match more closely with the structure of other OEM hooks in agesawrappers. Change-Id: Id241fdce78a21a5138ef60ac2f841b694da92241 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/Makefile.inc | 1 - src/cpu/amd/agesa/s3_resume.c | 89 ++-------------- src/cpu/amd/agesa/s3_resume.h | 15 +-- src/cpu/amd/agesa/spi.c | 49 --------- src/northbridge/amd/agesa/Makefile.inc | 3 + src/northbridge/amd/agesa/agesawrapper.c | 37 ++----- src/northbridge/amd/agesa/agesawrapper.h | 5 + src/northbridge/amd/agesa/oem_s3.c | 170 +++++++++++++++++++++++++++++++ 8 files changed, 198 insertions(+), 171 deletions(-) diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 668efbe..a434381 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -26,7 +26,6 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb romstage-y += s3_resume.c ramstage-y += s3_resume.c -ramstage-$(CONFIG_SPI_FLASH) += spi.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index fc619f7..501e29f 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -34,52 +34,17 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include "s3_resume.h" -/* The size needs to be 4k aligned, which is the sector size of most flashes. */ -#define S3_DATA_VOLATILE_SIZE 0x6000 -#define S3_DATA_MTRR_SIZE 0x1000 -#define S3_DATA_NONVOLATILE_SIZE 0x1000 - -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \ - (S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE -#error "Please increase the value of S3_DATA_SIZE" -#endif -static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len) -{ - /* FIXME: Find file from CBFS. */ - u32 s3_data = CONFIG_S3_DATA_POS; - - switch (S3DataType) { - case S3DataTypeVolatile: - *pos = s3_data; - *len = S3_DATA_VOLATILE_SIZE; - break; - case S3DataTypeMTRR: - *pos = s3_data + S3_DATA_VOLATILE_SIZE; - *len = S3_DATA_MTRR_SIZE; - break; - case S3DataTypeNonVolatile: - *pos = s3_data + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE; - *len = S3_DATA_NONVOLATILE_SIZE; - break; - default: - *pos = 0; - *len = 0; - break; - } -} +#ifndef __PRE_RAM__ void restore_mtrr(void) { + volatile u32 *msrPtr = (u32 *) OemS3Saved_MTRR_Storage(); u32 msr; - volatile UINT32 *msrPtr; msr_t msr_data; - printk(BIOS_SPEW, "%s\n", __func__); - - u32 pos, size; - get_s3nv_data(S3DataTypeMTRR, &pos, &size); - msrPtr = (UINT32 *)(pos + sizeof(UINT32)); + if (!msrPtr) + return; disable_cache(); @@ -137,6 +102,8 @@ void restore_mtrr(void) wrmsr(SYS_CFG, msr_data); } +#endif + #ifdef __PRE_RAM__ static void *backup_resume(void) { @@ -172,9 +139,6 @@ static void move_stack_high_mem(void) #endif #ifndef __PRE_RAM__ -/* FIXME: Why store MTRR in SPI, just use CBMEM ? */ -static u8 mtrr_store[S3_DATA_MTRR_SIZE]; - static void write_mtrr(u8 **p_nvram_pos, unsigned idx) { msr_t msr_data; @@ -184,13 +148,12 @@ static void write_mtrr(u8 **p_nvram_pos, unsigned idx) *p_nvram_pos += sizeof(msr_data); } -void OemAgesaSaveMtrr(void) +void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size) { + u8 *nvram_pos = mtrr_store; msr_t msr_data; u32 i; - u8 *nvram_pos = (u8 *) mtrr_store; - /* Enable access to AMD RdDram and WrDram extension bits */ msr_data = rdmsr(SYS_CFG); msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; @@ -220,44 +183,10 @@ void OemAgesaSaveMtrr(void) /* TOM2 */ write_mtrr(&nvram_pos, 0xC001001D); -#if IS_ENABLED(CONFIG_SPI_FLASH) - u32 pos, size; - get_s3nv_data(S3DataTypeMTRR, &pos, &size); - spi_SaveS3info(pos, size, mtrr_store, nvram_pos - (u8 *) mtrr_store); -#endif -} - -u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) -{ -#if IS_ENABLED(CONFIG_SPI_FLASH) - u32 pos, size; - get_s3nv_data(S3DataType, &pos, &size); - spi_SaveS3info(pos, size, Data, DataSize); -#endif - return AGESA_SUCCESS; + *mtrr_store_size = nvram_pos - (u8*) mtrr_store; } #endif -void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data) -{ - AMD_CONFIG_PARAMS StdHeader; - - u32 pos, size; - get_s3nv_data(S3DataType, &pos, &size); - - if (S3DataType == S3DataTypeNonVolatile) { - *DataSize = *(UINT32 *) pos; - *Data = (void *) (pos + sizeof(UINT32)); - } else if (S3DataType == S3DataTypeVolatile) { - u32 len = *(UINT32 *) pos; - void *src = (void *) (pos + sizeof(UINT32)); - void *dst = (void *) GetHeapBase(&StdHeader); - memcpy(dst, src, len); - *DataSize = len; - *Data = dst; - } -} - #ifdef __PRE_RAM__ static void set_resume_cache(void) { diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index 14984df..df13257 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -20,19 +20,10 @@ #ifndef S3_RESUME_H #define S3_RESUME_H -typedef enum { - S3DataTypeNonVolatile=0, ///< NonVolatile Data Type - S3DataTypeVolatile, ///< Volatile Data Type - S3DataTypeMTRR ///< MTRR storage -} S3_DATA_TYPE; - void restore_mtrr(void); -void prepare_for_resume(void); +void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size); +const void *OemS3Saved_MTRR_Storage(void); -u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data); -void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data); -void OemAgesaSaveMtrr (void); - -void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len); +void prepare_for_resume(void); #endif diff --git a/src/cpu/amd/agesa/spi.c b/src/cpu/amd/agesa/spi.c deleted file mode 100644 index 1c652fd..0000000 --- a/src/cpu/amd/agesa/spi.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <spi-generic.h> -#include <spi_flash.h> - -#include "s3_resume.h" - -void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) -{ - struct spi_flash *flash; - - spi_init(); - flash = spi_flash_probe(0, 0); - if (!flash) { - printk(BIOS_DEBUG, "Could not find SPI device\n"); - /* Dont make flow stop. */ - return; - } - - flash->spi->rw = SPI_WRITE_FLAG; - spi_claim_bus(flash->spi); - - flash->erase(flash, pos, size); - flash->write(flash, pos, sizeof(len), &len); - flash->write(flash, pos + sizeof(len), len, buf); - - flash->spi->rw = SPI_WRITE_FLAG; - spi_release_bus(flash->spi); - - return; -} diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index 8cf9ae3..04fe26d 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -26,3 +26,6 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb romstage-y += def_callouts.c agesawrapper.c eventlog.c ramstage-y += def_callouts.c agesawrapper.c eventlog.c + +romstage-y += oem_s3.c +ramstage-y += oem_s3.c diff --git a/src/northbridge/amd/agesa/agesawrapper.c b/src/northbridge/amd/agesa/agesawrapper.c index cd1347d..4f2fcf0 100644 --- a/src/northbridge/amd/agesa/agesawrapper.c +++ b/src/northbridge/amd/agesa/agesawrapper.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <string.h> -#include <cpu/amd/agesa/s3_resume.h> #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "amdlib.h" @@ -125,7 +124,6 @@ AGESA_STATUS agesawrapper_amdinitresume(void) AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); @@ -141,13 +139,9 @@ AGESA_STATUS agesawrapper_amdinitresume(void) AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; + OemInitResume(AmdResumeParamsPtr); - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); + status = AmdInitResume(AmdResumeParamsPtr); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); @@ -185,7 +179,6 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) AMD_INTERFACE_PARAMS AmdInterfaceParams; AMD_S3LATE_PARAMS AmdS3LateParams; AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); @@ -199,12 +192,12 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) AmdCreateStruct(&AmdInterfaceParams); +#if 0 + /* TODO: What to do with NvStorage here? */ + AmdS3LateParamsPtr->S3DataBlock.NvStorageSize = 0; +#endif AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + OemS3LateRestore(AmdS3LateParamsPtr); status = AmdS3LateRestore(AmdS3LateParamsPtr); AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); @@ -249,7 +242,6 @@ AGESA_STATUS agesawrapper_amdS3Save(void) AGESA_STATUS status; AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS)); @@ -269,21 +261,8 @@ AGESA_STATUS agesawrapper_amdS3Save(void) AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); ASSERT(status == AGESA_SUCCESS); - S3DataType = S3DataTypeNonVolatile; - - status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } + OemS3Save(AmdS3SaveParamsPtr); - OemAgesaSaveMtrr(); AmdReleaseStruct(&AmdInterfaceParams); return status; diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h index 09cb07d..2050f7f 100644 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ b/src/northbridge/amd/agesa/agesawrapper.h @@ -71,4 +71,9 @@ struct OEM_HOOK extern const struct OEM_HOOK OemCustomize; +/* For suspend-to-ram support. */ +AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams); +AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams); +AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams); + #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c new file mode 100644 index 0000000..6c3168c --- /dev/null +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -0,0 +1,170 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <AGESA.h> +#include <spi-generic.h> +#include <spi_flash.h> +#include <string.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <northbridge/amd/agesa/agesawrapper.h> + +typedef enum { + S3DataTypeNonVolatile=0, ///< NonVolatile Data Type + S3DataTypeVolatile, ///< Volatile Data Type + S3DataTypeMTRR ///< MTRR storage +} S3_DATA_TYPE; + +/* The size needs to be 4k aligned, which is the sector size of most flashes. */ +#define S3_DATA_VOLATILE_SIZE 0x6000 +#define S3_DATA_MTRR_SIZE 0x1000 +#define S3_DATA_NONVOLATILE_SIZE 0x1000 + +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \ + (S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE +#error "Please increase the value of S3_DATA_SIZE" +#endif + +static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len) +{ + /* FIXME: Find file from CBFS. */ + u32 s3_data = CONFIG_S3_DATA_POS; + + switch (S3DataType) { + case S3DataTypeVolatile: + *pos = s3_data; + *len = S3_DATA_VOLATILE_SIZE; + break; + case S3DataTypeMTRR: + *pos = s3_data + S3_DATA_VOLATILE_SIZE; + *len = S3_DATA_MTRR_SIZE; + break; + case S3DataTypeNonVolatile: + *pos = s3_data + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE; + *len = S3_DATA_NONVOLATILE_SIZE; + break; + default: + *pos = 0; + *len = 0; + break; + } +} + +#if defined(__PRE_RAM__) + +AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams) +{ + AMD_S3_PARAMS *dataBlock = &ResumeParams->S3DataBlock; + u32 pos, size; + + get_s3nv_data(S3DataTypeNonVolatile, &pos, &size); + + /* TODO: Our NvStorage is really const. */ + dataBlock->NvStorageSize = *(UINT32 *) pos; + dataBlock->NvStorage = (void *) (pos + sizeof(UINT32)); + return AGESA_SUCCESS; +} + +AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams) +{ + AMD_S3_PARAMS *dataBlock = &S3LateParams->S3DataBlock; + AMD_CONFIG_PARAMS StdHeader; + u32 pos, size; + + get_s3nv_data(S3DataTypeVolatile, &pos, &size); + + u32 len = *(UINT32 *) pos; + void *src = (void *) (pos + sizeof(UINT32)); + void *dst = (void *) GetHeapBase(&StdHeader); + + memcpy(dst, src, len); + dataBlock->VolatileStorageSize = len; + dataBlock->VolatileStorage = dst; + return AGESA_SUCCESS; +} + +#else + +static int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) +{ +#if IS_ENABLED(CONFIG_SPI_FLASH) + struct spi_flash *flash; + + spi_init(); + flash = spi_flash_probe(0, 0); + if (!flash) + return -1; + + flash->spi->rw = SPI_WRITE_FLAG; + spi_claim_bus(flash->spi); + + flash->erase(flash, pos, size); + flash->write(flash, pos, sizeof(len), &len); + flash->write(flash, pos + sizeof(len), len, buf); + + flash->spi->rw = SPI_WRITE_FLAG; + spi_release_bus(flash->spi); + return 0; +#else + return -1; +#endif +} + +AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams) +{ + AMD_S3_PARAMS *dataBlock = &S3SaveParams->S3DataBlock; + u8 MTRRStorage[S3_DATA_MTRR_SIZE]; + u32 MTRRStorageSize = 0; + u32 pos, size; + + /* To be consumed in AmdInitResume. */ + get_s3nv_data(S3DataTypeNonVolatile, &pos, &size); + if (size && dataBlock->NvStorageSize) + spi_SaveS3info(pos, size, dataBlock->NvStorage, + dataBlock->NvStorageSize); + + /* To be consumed in AmdS3LateRestore. */ + get_s3nv_data(S3DataTypeVolatile, &pos, &size); + if (size && dataBlock->VolatileStorageSize) + spi_SaveS3info(pos, size, dataBlock->VolatileStorage, + dataBlock->VolatileStorageSize); + + /* Collect MTRR setup. */ + backup_mtrr(MTRRStorage, &MTRRStorageSize); + + /* To be consumed in restore_mtrr, CPU enumeration in ramstage. */ + get_s3nv_data(S3DataTypeMTRR, &pos, &size); + if (size && MTRRStorageSize) + spi_SaveS3info(pos, size, MTRRStorage, MTRRStorageSize); + + return AGESA_SUCCESS; +} + +const void *OemS3Saved_MTRR_Storage(void) +{ + u32 pos, size; + get_s3nv_data(S3DataTypeMTRR, &pos, &size); + if (!size) + return NULL; + + return (void*)(pos + sizeof(UINT32)); +} + +#endif +

1 0

New patch to review for coreboot: 1ace1ba AGESA: Move agesawrappers related to HAVE_ACPI_RESUME support
by Kyösti Mälkki 04 Mar '15

04 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8605 -gerrit commit 1ace1ba37175e343838227874f617a4ca29f9f26 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Dec 16 16:28:12 2014 +0200 AGESA: Move agesawrappers related to HAVE_ACPI_RESUME support This change brings all agesawrappers in a single file to make it easier to understand the actual execution flow. Change-Id: Ifbb2b16e4cccfaa17aaf10887a856797be9b6877 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/Makefile.inc | 4 +- src/cpu/amd/agesa/agesawrapper_s3.c | 147 ------------------------------- src/northbridge/amd/agesa/agesawrapper.c | 115 ++++++++++++++++++++++++ 3 files changed, 117 insertions(+), 149 deletions(-) diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 1b7ff3c..668efbe 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -24,8 +24,8 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) += family15rl subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb -romstage-y += s3_resume.c agesawrapper_s3.c -ramstage-y += s3_resume.c agesawrapper_s3.c +romstage-y += s3_resume.c +ramstage-y += s3_resume.c ramstage-$(CONFIG_SPI_FLASH) += spi.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/agesawrapper_s3.c b/src/cpu/amd/agesa/agesawrapper_s3.c deleted file mode 100644 index 72bcf42..0000000 --- a/src/cpu/amd/agesa/agesawrapper_s3.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define __SIMPLE_DEVICE__ - -#include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <stdint.h> -#include <string.h> - -#include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "heapManager.h" - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); - - AmdCreateStruct(&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - status = AmdS3LateRestore(AmdS3LateParamsPtr); - AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); - ASSERT(status == AGESA_SUCCESS); - - return status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - AmdCreateStruct(&AmdInterfaceParams); - - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); - ASSERT(status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - - status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - - OemAgesaSaveMtrr(); - AmdReleaseStruct(&AmdInterfaceParams); - - return status; -} -#endif /* #ifndef __PRE_RAM__ */ diff --git a/src/northbridge/amd/agesa/agesawrapper.c b/src/northbridge/amd/agesa/agesawrapper.c index a73817c..cd1347d 100644 --- a/src/northbridge/amd/agesa/agesawrapper.c +++ b/src/northbridge/amd/agesa/agesawrapper.c @@ -19,6 +19,8 @@ #include <stdint.h> #include <string.h> + +#include <cpu/amd/agesa/s3_resume.h> #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "amdlib.h" @@ -118,6 +120,41 @@ AGESA_STATUS agesawrapper_amdinitpost(void) return status; } +AGESA_STATUS agesawrapper_amdinitresume(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + + OemAgesaGetS3Info(S3DataType, + (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); + + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + AGESA_STATUS agesawrapper_amdinitenv(void) { AGESA_STATUS status; @@ -142,6 +179,40 @@ AGESA_STATUS agesawrapper_amdinitenv(void) return status; } +AGESA_STATUS agesawrapper_amds3laterestore(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); + + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info(S3DataType, + (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + status = AmdS3LateRestore(AmdS3LateParamsPtr); + AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); + ASSERT(status == AGESA_SUCCESS); + + return status; +} + #else /* __PRE_RAM__ */ AGESA_STATUS agesawrapper_amdinitmid(void) @@ -173,6 +244,50 @@ AGESA_STATUS agesawrapper_amdinitmid(void) return status; } +AGESA_STATUS agesawrapper_amdS3Save(void) +{ + AGESA_STATUS status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + status = AmdS3Save(AmdS3SaveParamsPtr); + AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); + ASSERT(status == AGESA_SUCCESS); + + S3DataType = S3DataTypeNonVolatile; + + status = OemAgesaSaveS3Info(S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + status = OemAgesaSaveS3Info(S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + } + + OemAgesaSaveMtrr(); + AmdReleaseStruct(&AmdInterfaceParams); + + return status; +} /* We will reference AmdLateParams later to copy ACPI tables. */ static AMD_LATE_PARAMS *AmdLateParams = NULL;

1 0

New patch to review for coreboot: da37099 AGESA: Use same HeapManager for all BiosCallOuts
by Kyösti Mälkki 04 Mar '15

04 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8604 -gerrit commit da3709908facfedb40b9cf01904143aa2127d987 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jan 2 22:46:32 2015 +0200 AGESA: Use same HeapManager for all BiosCallOuts We do not allow platforms to mess around with memory layout. Change-Id: I316ff522c8833fa3b7ad20f2c5a9cae21f4174d8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/heapmanager.c | 29 +++++++++++++++++++--- src/mainboard/amd/dinar/BiosCallOuts.c | 3 --- src/mainboard/amd/inagua/BiosCallOuts.c | 3 --- src/mainboard/amd/olivehill/BiosCallOuts.c | 3 --- src/mainboard/amd/parmer/BiosCallOuts.c | 3 --- src/mainboard/amd/persimmon/BiosCallOuts.c | 3 --- src/mainboard/amd/south_station/BiosCallOuts.c | 3 --- src/mainboard/amd/thatcher/BiosCallOuts.c | 3 --- src/mainboard/amd/torpedo/BiosCallOuts.c | 3 --- src/mainboard/amd/union_station/BiosCallOuts.c | 3 --- src/mainboard/asrock/e350m1/BiosCallOuts.c | 3 --- src/mainboard/asrock/imb-a180/BiosCallOuts.c | 3 --- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 3 --- src/mainboard/asus/f2a85-m_le/BiosCallOuts.c | 3 --- src/mainboard/gizmosphere/gizmo/BiosCallOuts.c | 3 --- src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c | 3 --- src/mainboard/hp/abm/BiosCallOuts.c | 3 --- src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c | 3 --- src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 3 --- src/mainboard/lenovo/g505s/BiosCallOuts.c | 3 --- .../lippert/frontrunner-af/BiosCallOuts.c | 3 --- src/mainboard/lippert/toucan-af/BiosCallOuts.c | 3 --- src/mainboard/pcengines/apu1/BiosCallOuts.c | 3 --- src/mainboard/supermicro/h8qgi/BiosCallOuts.c | 3 --- src/mainboard/supermicro/h8scm/BiosCallOuts.c | 3 --- src/mainboard/tyan/s8226/BiosCallOuts.c | 3 --- src/northbridge/amd/agesa/BiosCallOuts.h | 16 +----------- src/northbridge/amd/agesa/def_callouts.c | 6 +++++ 28 files changed, 33 insertions(+), 93 deletions(-) diff --git a/src/cpu/amd/agesa/heapmanager.c b/src/cpu/amd/agesa/heapmanager.c index f1333af..bfe8b29 100644 --- a/src/cpu/amd/agesa/heapmanager.c +++ b/src/cpu/amd/agesa/heapmanager.c @@ -52,7 +52,18 @@ static AGESA_STATUS alloc_cbmem(AGESA_BUFFER_PARAMS *AllocParams) { } #endif -AGESA_STATUS agesa_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +typedef struct _BIOS_HEAP_MANAGER { + UINT32 StartOfAllocatedNodes; + UINT32 StartOfFreedNodes; +} BIOS_HEAP_MANAGER; + +typedef struct _BIOS_BUFFER_NODE { + UINT32 BufferHandle; + UINT32 BufferSize; + UINT32 NextNodeOffset; +} BIOS_BUFFER_NODE; + +static AGESA_STATUS agesa_AllocateBuffer(UINT32 Func, UINT32 Data, VOID *ConfigPtr) { UINT32 AvailableHeapSize; UINT8 *BiosHeapBaseAddr; @@ -188,7 +199,7 @@ AGESA_STATUS agesa_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return AGESA_SUCCESS; } -AGESA_STATUS agesa_DeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS agesa_DeallocateBuffer(UINT32 Func, UINT32 Data, VOID *ConfigPtr) { UINT8 *BiosHeapBaseAddr; @@ -307,7 +318,7 @@ AGESA_STATUS agesa_DeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return AGESA_SUCCESS; } -AGESA_STATUS agesa_LocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS agesa_LocateBuffer(UINT32 Func, UINT32 Data, VOID *ConfigPtr) { UINT32 AllocNodeOffset; UINT8 *BiosHeapBaseAddr; @@ -340,3 +351,15 @@ AGESA_STATUS agesa_LocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return AGESA_SUCCESS; } + +AGESA_STATUS HeapManagerCallout(UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + if (Func == AGESA_LOCATE_BUFFER) + return agesa_LocateBuffer(Func, Data, ConfigPtr); + else if (Func == AGESA_ALLOCATE_BUFFER) + return agesa_AllocateBuffer(Func, Data, ConfigPtr); + else if (Func == AGESA_DEALLOCATE_BUFFER) + return agesa_DeallocateBuffer(Func, Data, ConfigPtr); + else + return AGESA_UNSUPPORTED; +} diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c index dee4920..cbd7329 100644 --- a/src/mainboard/amd/dinar/BiosCallOuts.c +++ b/src/mainboard/amd/dinar/BiosCallOuts.c @@ -81,9 +81,6 @@ static AGESA_STATUS board_ReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer}, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, board_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index 69bb2c2..c0796db 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -30,9 +30,6 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *Conf const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index 97f8769..03465d8 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -34,9 +34,6 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index e09218e..13f036d 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -34,9 +34,6 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 7fa0534..e40e402 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -29,9 +29,6 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *Conf const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 693f159..a256eaf 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -30,9 +30,6 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *Conf const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index 3bd7237..0bf4536 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -34,9 +34,6 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c index 3a89da2..21f1d4c 100644 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ b/src/mainboard/amd/torpedo/BiosCallOuts.c @@ -32,9 +32,6 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *Conf const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index 693f159..a256eaf 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -30,9 +30,6 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *Conf const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index 7a4ee26..8ed7c49 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -29,9 +29,6 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *Config const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/asrock/imb-a180/BiosCallOuts.c b/src/mainboard/asrock/imb-a180/BiosCallOuts.c index 53b6871..ff5d3cf 100644 --- a/src/mainboard/asrock/imb-a180/BiosCallOuts.c +++ b/src/mainboard/asrock/imb-a180/BiosCallOuts.c @@ -32,9 +32,6 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index 13bee0c..71ce94f 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -29,9 +29,6 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/asus/f2a85-m_le/BiosCallOuts.c b/src/mainboard/asus/f2a85-m_le/BiosCallOuts.c index cfc0ee1..dee5535 100644 --- a/src/mainboard/asus/f2a85-m_le/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m_le/BiosCallOuts.c @@ -29,9 +29,6 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c index 574ca64..943d14d 100644 --- a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c @@ -28,9 +28,6 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *Config const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd_from_cbfs }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c index 44273ab..2faf6cd 100644 --- a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c @@ -34,9 +34,6 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd_from_cbfs }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/hp/abm/BiosCallOuts.c b/src/mainboard/hp/abm/BiosCallOuts.c index d55bc06..ba86679 100644 --- a/src/mainboard/hp/abm/BiosCallOuts.c +++ b/src/mainboard/hp/abm/BiosCallOuts.c @@ -32,9 +32,6 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index 5373d90..fd1c479 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -30,9 +30,6 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index cb94337..2c31727 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -31,9 +31,6 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *Config const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/lenovo/g505s/BiosCallOuts.c b/src/mainboard/lenovo/g505s/BiosCallOuts.c index 5373d90..fd1c479 100644 --- a/src/mainboard/lenovo/g505s/BiosCallOuts.c +++ b/src/mainboard/lenovo/g505s/BiosCallOuts.c @@ -30,9 +30,6 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c index 9fc4f74..2ab810e 100644 --- a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c +++ b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c @@ -34,9 +34,6 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *Config const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/lippert/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/toucan-af/BiosCallOuts.c index 4b30c39..6345ec2 100644 --- a/src/mainboard/lippert/toucan-af/BiosCallOuts.c +++ b/src/mainboard/lippert/toucan-af/BiosCallOuts.c @@ -35,9 +35,6 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *Config const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c index 0bd74fe..90368f6 100644 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c @@ -31,9 +31,6 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *Conf const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, board_ReadSpd_from_cbfs }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c index 06b2f3e..6fc0154 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c @@ -76,9 +76,6 @@ static AGESA_STATUS board_ReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); #include <stdlib.h> const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, board_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/supermicro/h8scm/BiosCallOuts.c b/src/mainboard/supermicro/h8scm/BiosCallOuts.c index 58908c9..d82f527 100644 --- a/src/mainboard/supermicro/h8scm/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8scm/BiosCallOuts.c @@ -28,9 +28,6 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.c b/src/mainboard/tyan/s8226/BiosCallOuts.c index 7fe90c5..d31b696 100644 --- a/src/mainboard/tyan/s8226/BiosCallOuts.c +++ b/src/mainboard/tyan/s8226/BiosCallOuts.c @@ -84,9 +84,6 @@ static AGESA_STATUS board_ReadSpd (UINT32 Func,UINT32 Data, VOID *ConfigPtr); const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, board_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, diff --git a/src/northbridge/amd/agesa/BiosCallOuts.h b/src/northbridge/amd/agesa/BiosCallOuts.h index a57d051..54b21bb 100644 --- a/src/northbridge/amd/agesa/BiosCallOuts.h +++ b/src/northbridge/amd/agesa/BiosCallOuts.h @@ -40,25 +40,10 @@ #endif -typedef struct _BIOS_HEAP_MANAGER { - UINT32 StartOfAllocatedNodes; - UINT32 StartOfFreedNodes; -} BIOS_HEAP_MANAGER; - -typedef struct _BIOS_BUFFER_NODE { - UINT32 BufferHandle; - UINT32 BufferSize; - UINT32 NextNodeOffset; -} BIOS_BUFFER_NODE; UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); void EmptyHeap(void); - -AGESA_STATUS agesa_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS agesa_DeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS agesa_LocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); - AGESA_STATUS agesa_NoopUnsupported (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS agesa_NoopSuccess (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS agesa_EmptyIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); @@ -69,6 +54,7 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt AGESA_STATUS agesa_ReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS HeapManagerCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); typedef struct { diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c index d0aacd4..26b1c0d 100644 --- a/src/northbridge/amd/agesa/def_callouts.c +++ b/src/northbridge/amd/agesa/def_callouts.c @@ -30,8 +30,14 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { + AGESA_STATUS status; UINTN i; + /* One HeapManager serves them all. */ + status = HeapManagerCallout(Func, Data, ConfigPtr); + if (status != AGESA_UNSUPPORTED) + return status; + for (i = 0; i < BiosCalloutsLen; i++) { if (BiosCallouts[i].CalloutName == Func) break;

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Patch merged into coreboot/master: d2df4e4 libpayload: Don't try to free individual xhci device slots
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit d2df4e4d0f5e7ca657d07aee84b5292d13161763 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Feb 22 22:50:32 2015 +0100 libpayload: Don't try to free individual xhci device slots `di` points to a single item in xhci->dev[], which is malloc'd collectively. Trying to free() leads to pain. Change-Id: Ibd99eda905d43cbf2d2c111dfd0186ed6b119329 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/8515 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8515 for details. -gerrit

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Patch merged into coreboot/master: 48e78cf board-status: update mediawiki interface
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit 48e78cf6fd04b6086f4bcb04703fad936c35f56c Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Mar 1 21:25:59 2015 +0100 board-status: update mediawiki interface Our Mediawiki instance doesn't accept the old txt format anymore. Change-Id: I94b9f5366900ec8e192abab3ed716dbced4fc4f7 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/8567 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8567 for details. -gerrit

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Patch merged into coreboot/master: 90105d5 Only update submodules if the source is in a git repo
by gerrit＠coreboot.org 04 Mar '15

04 Mar '15

the following patch was just integrated into master: commit 90105d546826498603eb6db1999ada92dca08b82 Author: Martin Roth <gaumless(a)gmail.com> Date: Thu Feb 12 19:34:11 2015 -0700 Only update submodules if the source is in a git repo This change just adds a check to verify that the build is happening inside a git repo and that git is a valid command before trying to update the submodules. Use 'command -v' instead of 'which' to stay portable. Change-Id: Idfa27645c3dbfd684f90002ecb01626d71eacc8f Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/8427 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/8427 for details. -gerrit

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coreboot-gerrit March 2015