coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: f752d01 storm: Provide ability to build ap148 variant
by gerrit＠coreboot.org 05 Mar '15

05 Mar '15

the following patch was just integrated into master: commit f752d013b0cede9e7d4a8463827b6ef3a8238e0d Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Jul 10 15:24:18 2014 -0700 storm: Provide ability to build ap148 variant With BOARD_VARIANT_AP148 configuration option enabled the image will be built for 512MB DRAM instead of 1024MB and the mainboard_part_number field in the lb_mainboard entry will be set to "AP148" instead of "Storm". BUG=chrome-os-partner:30440 TEST=manual . built and booted both AP148 and proto0 all the way to reading the kernel . verified that the config file includes correct part number and memory size . verified proper machine IDs reportted when starting the kernel Original-Change-Id: Ie609544a460fc991e66e8b95e8d7a3ed5e845f7b Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207427 Original-Reviewed-by: Trevor Bourget <tbourget(a)codeaurora.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit a80ab00f27eef9e3aa2f761659d6945d6fce2ef6) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I477e672dc4f48fa9c9893bf0759704501ea07b1a Reviewed-on: http://review.coreboot.org/8590 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/8590 for details. -gerrit

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Patch merged into coreboot/master: 30cda7e arm64: provide early SoC initialization
by gerrit＠coreboot.org 05 Mar '15

05 Mar '15

the following patch was just integrated into master: commit 30cda7e83f06f5a84eb9dfea3be9f435bb36d392 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jul 15 10:25:48 2014 -0500 arm64: provide early SoC initialization Some of the SoC's need an early hook to configure certain registers. One example of this is on t132 where ramstage is the first thing being ran on the arm64 core and it is the only entity that can configure certain registers required for the rest of ramstage. Therefore, provide the opportunity for the SoC to implement such requirements. BUG=chrome-os-partner:30572 BRANCH=None TEST=Built and ran through coreboot. Original-Change-Id: Ib352f3788872f888581b398c9b394b7c4e54b02a Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208061 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 2c50e2b39e75d1383e8e573c576630a5b7313349) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I38df63e46c5c21b2d319fc9eb42053c3a0d61bc8 Reviewed-on: http://review.coreboot.org/8595 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/8595 for details. -gerrit

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Patch merged into coreboot/master: 072e0cc rush_ryu: Add new mainboard
by gerrit＠coreboot.org 05 Mar '15

05 Mar '15

the following patch was just integrated into master: commit 072e0cc899aa11ca55fecd9e8a384a045975f735 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 14 19:09:23 2014 -0500 rush_ryu: Add new mainboard This is a clone of rush for the time being. All the incompatible bits can be moved later. Additional patches to follow. BUG=chrome-os-partner:30569 BRANCH=None TEST=Built coreboot for rush_ryu board Original-Change-Id: Iae56d016d0c328d83242b95f307fefaa8c68deec Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207838 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit cf2b88963743e40a35d841ef522172cb2448abbf) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I92a8b4d31fac4a25e3afa3b6e158e1dba0f80aab Reviewed-on: http://review.coreboot.org/8594 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8594 for details. -gerrit

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Patch merged into coreboot/master: 5f66b52 tegra132: add support for TZ carve-out
by gerrit＠coreboot.org 05 Mar '15

05 Mar '15

the following patch was just integrated into master: commit 5f66b5246443e4387a4147745666dc091556ff07 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 14 15:00:41 2014 -0500 tegra132: add support for TZ carve-out The TrustZone carve-out needs to be taken into account when determining the memory layout. However, things are complicated by the fact that TZ carve-out registers are not accessible by the AVP. BUG=chrome-os-partner:30572 BRANCH=None TEST=Built and booted to end of ramstage. Noted that denver cores can read TZ registers while AVP doesn't bother. Original-Change-Id: I2d2d27e33a334bf639af52260b99d8363906c646 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207835 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> (cherry picked from commit a4d792f4ed6a0c39eab09d90f4454d3d5dc3db26) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I8fbef03d5ac42d300e1e41aeba9b86c929e01494 Reviewed-on: http://review.coreboot.org/8593 Reviewed-by: Aaron Durbin <adurbin(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8593 for details. -gerrit

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Patch merged into coreboot/master: 9c8cfc5 coreboot arm64: Add proper masks for setting SCTLR and SCR regs to 0 at init
by gerrit＠coreboot.org 05 Mar '15

05 Mar '15

the following patch was just integrated into master: commit 9c8cfc5c25876991751ff4e533a0c421203139c8 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 14 11:50:09 2014 -0700 coreboot arm64: Add proper masks for setting SCTLR and SCR regs to 0 at init Since RES1 and RES0 bits are marked as SBOP(Should-Be-One-or-Preserved) and SBZP(Should-Be-Zero-or-Preserved) respectively, resetting the SCTLR and SCR registers should be done with proper bitmask. BUG=None BRANCH=None TEST=Compiles successfully and verified that the RES bits are preserved across register writes. Original-Change-Id: I5094ba7e51e8ea6f7d7612ba4d11b10dcbdb1607 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/207815 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit dfb196b4063e4f94d1ba9d5e2d19bae624ed46b3) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I033a68b723fea83817aaa6402b86c78abd3e1da9 Reviewed-on: http://review.coreboot.org/8592 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8592 for details. -gerrit

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Patch merged into coreboot/master: f13c567 t132: handle carve-outs for addressable memory
by gerrit＠coreboot.org 05 Mar '15

05 Mar '15

the following patch was just integrated into master: commit f13c567c9713538789ec3ef3f478e1c52816d959 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jul 11 15:56:31 2014 -0500 t132: handle carve-outs for addressable memory The carve-out regions need to be taken into account when calculating addressable memory because those regions aren't accessible from the main cpu. The additional exposed functions are to accommodate adding resources during ramstage resource reading. The TZ (trust zone) region is empty for now until more documentation is provided on determining its location. BUG=None TEST=Built and booted through attempting payload loading. MTS carve-out is taken into account programmatically. Original-Change-Id: I3301b2a12680ad79047198ada41f32eb1b7fa68b Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207585 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 15b9c74dd1ef5bfb1fd7c6dab50624f815658e14) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I46d54dbbb8e102fc70ab34bc4bbd2361ef1ea504 Reviewed-on: http://review.coreboot.org/8591 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/8591 for details. -gerrit

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Patch merged into coreboot/master: eeacf74 t132: Enable cbmem console support
by gerrit＠coreboot.org 05 Mar '15

05 Mar '15

the following patch was just integrated into master: commit eeacf74a7ce9f3302d813287e6409d660da43958 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 10 15:05:13 2014 -0500 t132: Enable cbmem console support Enabled CBMEM support for t132 platforms. Some of the existing code is moved around to avoid dependencies in the other stages that need it. BUG=None BRANCH=None TEST=Built and booted a rush with cbmem support. Original-Change-Id: I78a31b58ab9cc01a7b5d1fffdb6c8ae0c446c7dd Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207163 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit f552197dbda06c754b5664c3bed4ed361154229a) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I8fa2919714b467cc976e5bb5c4716e5b7979694b Reviewed-on: http://review.coreboot.org/8589 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8589 for details. -gerrit

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Patch merged into coreboot/master: 5626d8f t132: bring up 64-bit denver core
by gerrit＠coreboot.org 05 Mar '15

05 Mar '15

the following patch was just integrated into master: commit 5626d8f59a4a70da4724e778a38e0fe6847fa5d8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 10 12:50:27 2014 -0500 t132: bring up 64-bit denver core The startup sequence for cpu0 is implemented while also providing a trampoline for transitioning to 64-bit mode because the denver cores on t132 come out of cold reset in 32-bit mode. Mainboard callbacks are provided for providing the board-specific bits of the bringup sequence. BUG=chrome-os-partner:29923 BRANCH=None TEST=Built and booted through ramstage. Original-Change-Id: I50755fb6b06db994af8667969d8493f214a70aae Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207263 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer(a)google.com> (cherry picked from commit 17f09bf4bdb43986c19067ca8fd65d4c5365a7c6) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I14d99c24dd6e29a4584c8c548c4b26c92b6ade97 Reviewed-on: http://review.coreboot.org/8586 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8586 for details. -gerrit

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Patch set updated for coreboot: b484762 qemu: 2.1+ smbios tables support
by Gerd Hoffmann 05 Mar '15

05 Mar '15

Gerd Hoffmann (kraxel(a)redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8608 -gerrit commit b4847626ce0fa6db7553e719ad2d8f75d9c7a623 Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Wed Aug 27 11:25:13 2014 +0200 qemu: 2.1+ smbios tables support Starting with version 2.1 qemu provides a full set of smbios tables for the virtual hardware emulated, except type 0 (bios information). This patch adds support for loading those tables to coreboot. The code is used by both i440fx and q35. Change-Id: Id034f0c214e8890194145a92f06354201dee7963 Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/mainboard/emulation/qemu-i440fx/fw_cfg.c | 83 +++++++++++++++++++++++ src/mainboard/emulation/qemu-i440fx/fw_cfg.h | 1 + src/mainboard/emulation/qemu-i440fx/northbridge.c | 5 ++ 3 files changed, 89 insertions(+) diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 44256be..242f218 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -362,6 +362,89 @@ static void fw_cfg_smbios_init(void) } } +static unsigned long smbios_next(unsigned long current) +{ + struct smbios_type0 *t0; + int l, count = 0; + char *s; + + t0 = (void*)current; + current += t0->length; + for (;;) { + s = (void*)current; + l = strlen(s); + if (!l) + return current + (count ? 1 : 2); + current += l + 1; + count++; + } +} + +/* + * Starting with version 2.1 qemu provides a full set of smbios tables + * for the virtual hardware emulated, except type 0 (bios information). + * + * What we are going to do here is find the type0 table, keep it, and + * override everything else generated by coreboot with the qemu smbios + * tables. + * + * It's a bit hackish, but qemu is a special case (compared to real + * hardware) and this way we don't need special qemu support in the + * generic smbios code. + */ +unsigned long fw_cfg_smbios_tables(int *handle, unsigned long *current) +{ + struct smbios_type0 *t0; + unsigned long start, end; + int len, ret, i, count = 1; + char *str; + + len = fw_cfg_check_file("etc/smbios/smbios-tables"); + if (len < 0) + return 0; + printk(BIOS_DEBUG, "QEMU: found smbios tables in fw_cfg (len %d).\n", len); + + /* + * Search backwards for "coreboot" (first string in type0 table, + * see src/arch/x86/boot/smbios.c), then find type0 table. + */ + for (i = 0; i < 16384; i++) { + str = (char*)(*current - i); + if (strcmp(str, "coreboot") == 0) + break; + } + if (i == 16384) + return 0; + i += sizeof(struct smbios_type0) - 2; + t0 = (struct smbios_type0*)(*current - i); + if (t0->type != SMBIOS_BIOS_INFORMATION || t0->handle != 0) + return 0; + printk(BIOS_DEBUG, "QEMU: coreboot type0 table found at 0x%lx.\n", + *current - i); + start = smbios_next(*current - i); + + /* + * Fetch smbios tables from qemu, go find the end marker. + * We'll exclude the end marker as coreboot will add one. + */ + printk(BIOS_DEBUG, "QEMU: loading smbios tables to 0x%lx\n", start); + fw_cfg_load_file("etc/smbios/smbios-tables", (void*)start); + end = start; + do { + t0 = (struct smbios_type0*)end; + if (t0->type == SMBIOS_END_OF_TABLE) + break; + end = smbios_next(end); + count++; + } while (end < start + len); + + /* final fixups. */ + ret = end - *current; + *current = end; + *handle = count; + return ret; +} + const char *smbios_mainboard_manufacturer(void) { fw_cfg_smbios_init(); diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg.h index 2a10d8b..51ecaa8 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.h @@ -19,3 +19,4 @@ void fw_cfg_get(int entry, void *dst, int dstlen); int fw_cfg_check_file(const char *name); void fw_cfg_load_file(const char *name, void *dst); int fw_cfg_max_cpus(void); +unsigned long fw_cfg_smbios_tables(int *handle, unsigned long *current); diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 08d563f..f12a272 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -213,6 +213,11 @@ static int qemu_get_smbios_data17(int handle, int parent_handle, unsigned long * static int qemu_get_smbios_data(device_t dev, int *handle, unsigned long *current) { int len; + + len = fw_cfg_smbios_tables(handle, current); + if (len != 0) + return len; + len = qemu_get_smbios_data16(*handle, current); len += qemu_get_smbios_data17(*handle+1, *handle, current); *handle += 2;

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Patch set updated for coreboot: 75527e7 AMD: Uniformly define MSRs for TOP_MEM and TOP_MEM2
by Kyösti Mälkki 05 Mar '15

05 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8609 -gerrit commit 75527e7fbf61f728184652ce694d9fbe0230ccd3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 5 14:35:04 2015 +0200 AMD: Uniformly define MSRs for TOP_MEM and TOP_MEM2 Make the build tolerate re-definitions. Change-Id: Ia7505837c70b1f749262508b26576e95c7865576 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/cache_as_ram.inc | 4 ++-- src/include/cpu/amd/mtrr.h | 13 ++++++------- src/vendorcode/amd/agesa/f10/AGESA.h | 8 ++------ src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h | 2 +- src/vendorcode/amd/agesa/f12/AGESA.h | 8 ++------ src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h | 2 +- src/vendorcode/amd/agesa/f14/AGESA.h | 8 ++------ src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h | 2 +- src/vendorcode/amd/agesa/f15/AGESA.h | 10 ++-------- src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.h | 2 +- src/vendorcode/amd/agesa/f16kb/AGESA.h | 4 ---- 11 files changed, 20 insertions(+), 43 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index dadf8f7..f7dec30 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -468,8 +468,8 @@ all_mtrr_msrs: .long IORRMask_MSR(1) /* Top of memory MTRR MSRs */ - .long TOP_MEM_MSR - .long TOP_MEM2_MSR + .long TOP_MEM + .long TOP_MEM2 .long 0x000 /* NULL, end of table */ diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index a9e672b..be816ba 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -25,13 +25,12 @@ #define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg)) #define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1) -#define TOP_MEM_MSR 0xC001001A -#define TOP_MEM2_MSR 0xC001001D -#ifndef TOP_MEM - #define TOP_MEM TOP_MEM_MSR -#endif -#ifndef TOP_MEM2 - #define TOP_MEM2 TOP_MEM2_MSR +#if defined(__ASSEMBLER__) +#define TOP_MEM 0xC001001A +#define TOP_MEM2 0xC001001D +#else +#define TOP_MEM 0xC001001Aul +#define TOP_MEM2 0xC001001Dul #endif #define TOP_MEM_MASK 0x007fffff diff --git a/src/vendorcode/amd/agesa/f10/AGESA.h b/src/vendorcode/amd/agesa/f10/AGESA.h index c38bf40..a128116 100644 --- a/src/vendorcode/amd/agesa/f10/AGESA.h +++ b/src/vendorcode/amd/agesa/f10/AGESA.h @@ -1012,12 +1012,8 @@ typedef enum { ///< CPU MSR Register definitions ------------------------------------------ #define SYS_CFG 0xC0010010 -#ifndef TOP_MEM - #define TOP_MEM 0xC001001A -#endif -#ifndef TOP_MEM2 - #define TOP_MEM2 0xC001001D -#endif +#define TOP_MEM 0xC001001Aul +#define TOP_MEM2 0xC001001Dul #define HWCR 0xC0010015 #define NB_CFG 0xC001001F diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h index 34d2568..1777c5d 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h @@ -92,7 +92,7 @@ #define NorthbridgeCapabilities 0xE8 #define DRAMBase0 0x40 #define MMIOBase0 0x80 -#define TOP_MEM 0xC001001A +#define TOP_MEM 0xC001001Aul #define LOW_NODE_DEVICEID 24 #define LOW_APICID 0 diff --git a/src/vendorcode/amd/agesa/f12/AGESA.h b/src/vendorcode/amd/agesa/f12/AGESA.h index 9660f35..abe72b6 100644 --- a/src/vendorcode/amd/agesa/f12/AGESA.h +++ b/src/vendorcode/amd/agesa/f12/AGESA.h @@ -1279,12 +1279,8 @@ typedef enum { ///< CPU MSR Register definitions ------------------------------------------ #define SYS_CFG 0xC0010010 -#ifndef TOP_MEM -#define TOP_MEM 0xC001001A -#endif -#ifndef TOP_MEM2 -#define TOP_MEM2 0xC001001D -#endif +#define TOP_MEM 0xC001001Aul +#define TOP_MEM2 0xC001001Dul #define HWCR 0xC0010015 #define NB_CFG 0xC001001F diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h index 29f4070..b871845 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h @@ -101,7 +101,7 @@ AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE); #define NorthbridgeCapabilities 0xE8 #define DRAMBase0 0x40 #define MMIOBase0 0x80 -#define TOP_MEM 0xC001001A +#define TOP_MEM 0xC001001Aul #define LOW_NODE_DEVICEID 24 #define LOW_APICID 0 diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h index a8ede95..d997ad1 100644 --- a/src/vendorcode/amd/agesa/f14/AGESA.h +++ b/src/vendorcode/amd/agesa/f14/AGESA.h @@ -1129,12 +1129,8 @@ typedef enum { ///< CPU MSR Register definitions ------------------------------------------ #define SYS_CFG 0xC0010010 -#ifndef TOP_MEM -#define TOP_MEM 0xC001001A -#endif -#ifndef TOP_MEM2 -#define TOP_MEM2 0xC001001D -#endif +#define TOP_MEM 0xC001001Aul +#define TOP_MEM2 0xC001001Dul #define HWCR 0xC0010015 #define NB_CFG 0xC001001F diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h index 6369bfc..a6f6c78 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h @@ -98,7 +98,7 @@ #define NorthbridgeCapabilities 0xE8 #define DRAMBase0 0x40 #define MMIOBase0 0x80 -#define TOP_MEM 0xC001001A +#define TOP_MEM 0xC001001Aul #define LOW_NODE_DEVICEID 24 #define LOW_APICID 0 diff --git a/src/vendorcode/amd/agesa/f15/AGESA.h b/src/vendorcode/amd/agesa/f15/AGESA.h index 6b0171b..ffa37ae 100644 --- a/src/vendorcode/amd/agesa/f15/AGESA.h +++ b/src/vendorcode/amd/agesa/f15/AGESA.h @@ -1418,14 +1418,8 @@ typedef enum { ///< CPU MSR Register definitions ------------------------------------------ #define SYS_CFG 0xC0010010 -//#define TOP_MEM 0xC001001A -//#define TOP_MEM2 0xC001001D -#ifndef TOP_MEM - #define TOP_MEM 0xC001001A -#endif -#ifndef TOP_MEM2 - #define TOP_MEM2 0xC001001D -#endif +#define TOP_MEM 0xC001001Aul +#define TOP_MEM2 0xC001001Dul #define HWCR 0xC0010015 #define NB_CFG 0xC001001F diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.h index 050ec53..d010347 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.h +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.h @@ -116,7 +116,7 @@ CpuLateInitApTask ( #define NorthbridgeCapabilities 0xE8 #define DRAMBase0 0x40 #define MMIOBase0 0x80 -#define TOP_MEM 0xC001001A +#define TOP_MEM 0xC001001Aul #define LOW_NODE_DEVICEID 24 #define LOW_APICID 0 diff --git a/src/vendorcode/amd/agesa/f16kb/AGESA.h b/src/vendorcode/amd/agesa/f16kb/AGESA.h index 3e58d23..6c2f19c 100644 --- a/src/vendorcode/amd/agesa/f16kb/AGESA.h +++ b/src/vendorcode/amd/agesa/f16kb/AGESA.h @@ -1590,12 +1590,8 @@ typedef enum { ///< CPU MSR Register definitions ------------------------------------------ #define SYS_CFG 0xC0010010ul -#ifndef TOP_MEM #define TOP_MEM 0xC001001Aul -#endif -#ifndef TOP_MEM2 #define TOP_MEM2 0xC001001Dul -#endif #define HWCR 0xC0010015ul #define NB_CFG 0xC001001Ful

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coreboot-gerrit March 2015