coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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2443 discussions

Patch set updated for coreboot: 3ef5a67 tegra132: add preboot MTS to bct generation
by Marc Jones 07 Mar '15

07 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8466 -gerrit commit 3ef5a67fa3e51f6b7b1ff2e85bcd197ce7e359a1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jun 20 14:58:05 2014 -0500 tegra132: add preboot MTS to bct generation The preboot MTS microcode needs to be supplied within the bct so the BootROM can load it. The size of the bootblock space in SPI needed to be extended to accomodate the extra length. BUG=chrome-os-partner:29059 BUG=chrome-os-partner:29060 BRANCH=None TEST=Built rush with updated cbootimage with t132 support. Original-Change-Id: Iafc1837cd81cc1165a9be5da6ec7425cec2e2ffc Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204940 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 22e054496465c74fc12afd865d14b87c5858d889) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I5e46c408a7215ecc789b0a0f35070ef9036a7d11 --- src/soc/nvidia/tegra132/Makefile.inc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 5bbeefa..7371dbb 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -51,6 +51,7 @@ ramstage-y += ../tegra/pinmux.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c CPPFLAGS_common += -Isrc/soc/nvidia/tegra132/include/ +CBOOTIMAGE_OPTS = --soc tegra132 # We want to grab the bootblock right before it goes into the image and wrap # it inside a BCT, but ideally we would do that without making special, one @@ -69,14 +70,17 @@ $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf $(obj)/generated/bct.bin: $(obj)/generated/bct.cfg $(CBOOTIMAGE) @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n" - $(CBOOTIMAGE) -gbct --soc tegra132 $< $@ + $(CBOOTIMAGE) -gbct $(CBOOTIMAGE_OPTS) $< $@ BCT_BIN = $(obj)/generated/bct.bin BCT_WRAPPER = $(obj)/generated/bct.wrapper +PREBOOT_MTS_FILE = 3rdparty/cpu/nvidia/tegra132/current/prod/preboot_cr.bin $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BCT_BIN) $(CBOOTIMAGE) echo "Version = 1;" > $(BCT_WRAPPER) echo "Redundancy = 1;" >> $(BCT_WRAPPER) + echo "Bctcopy = 1;" >> $(BCT_WRAPPER) echo "Bctfile = $(BCT_BIN);" >> $(BCT_WRAPPER) + echo "MtsPreboot = $(PREBOOT_MTS_FILE),0x4000f000,0x4000f000,Complete;" >> $(BCT_WRAPPER) echo "BootLoader = $<,$(CONFIG_BOOTBLOCK_BASE),$(CONFIG_BOOTBLOCK_BASE),Complete;" >> $(BCT_WRAPPER) @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n" - $(CBOOTIMAGE) $(BCT_WRAPPER) $@ + $(CBOOTIMAGE) $(CBOOTIMAGE_OPTS) $(BCT_WRAPPER) $@

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Patch merged into coreboot/master: a425b96 AMD Fam10h: Only create _PR scope if it is filled in
by gerrit＠coreboot.org 06 Mar '15

06 Mar '15

the following patch was just integrated into master: commit a425b960914003ece27612233929b1be2fc2c15a Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Mar 5 20:18:21 2015 +0100 AMD Fam10h: Only create _PR scope if it is filled in The former pstates_algorithm() function has two early exit points now, and so it might never get around to writing pstates data. Change-Id: I19ca937375c6d33b78bd5b1859fa5c25473be9b6 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/8610 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8610 for details. -gerrit

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Patch merged into coreboot/master: e236204 Move generation of build.h into a shell script
by gerrit＠coreboot.org 06 Mar '15

06 Mar '15

the following patch was just integrated into master: commit e236204d537808180ace7b78c1dc293ed59d9878 Author: Martin Roth <gaumless(a)gmail.com> Date: Thu Feb 12 19:32:41 2015 -0700 Move generation of build.h into a shell script Moving the routines that create build.h into a script offers several advantages. We can create more complex functions to run and we don't have to deal with both bash and Make at the same time. This script combines what is currently in Makefile.inc with a couple of updates. - Update how it determines whether to use git for the timestamp - Move the git revision string generation inside the routine that checks to see if we have git. - Add a timeout for the domain name check. Change-Id: I93c131e8d01a0099eb13db720fa865c627985750 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/8428 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8428 for details. -gerrit

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Patch set updated for coreboot: 8802de6 Move generation of build.h into a shell script
by Martin Roth 06 Mar '15

06 Mar '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8428 -gerrit commit 8802de6581aa5a85920ac3976053fc7ccc8a2289 Author: Martin Roth <gaumless(a)gmail.com> Date: Thu Feb 12 19:32:41 2015 -0700 Move generation of build.h into a shell script Moving the routines that create build.h into a script offers several advantages. We can create more complex functions to run and we don't have to deal with both bash and Make at the same time. This script combines what is currently in Makefile.inc with a couple of updates. - Update how it determines whether to use git for the timestamp - Move the git revision string generation inside the routine that checks to see if we have git. - Add a timeout for the domain name check. Change-Id: I93c131e8d01a0099eb13db720fa865c627985750 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- Makefile.inc | 28 +------------- util/genbuild_h/genbuild_h.sh | 87 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+), 26 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index eb8b601..89a0553 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -243,7 +243,7 @@ CBFS_PAYLOAD_COMPRESS_FLAG:=LZMA endif ifneq ($(CONFIG_LOCALVERSION),"") -COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION)) +export COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION)) endif CPPFLAGS_common := -Isrc -Isrc/include -I$(obj) @@ -274,31 +274,7 @@ additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \ $(obj)/build.h: .xcompile @printf " GEN build.h\n" rm -f $(obj)/build.h - printf "/* build system definitions (autogenerated) */\n" > $(obj)/build.ht - printf "#ifndef __BUILD_H\n" >> $(obj)/build.ht - printf "#define __BUILD_H\n\n" >> $(obj)/build.ht - printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" >> $(obj)/build.ht - if git update-index -q --refresh >/dev/null; ! git diff-index --quiet HEAD; then \ - printf "/* `LANG= TZ=UTC git log --date=local --pretty=format:%cd -1` UTC */\n" >> $(obj)/build.ht; \ - printf "#define COREBOOT_VERSION_TIMESTAMP `LANG= git log --pretty=format:%ct -1`\n" >> $(obj)/build.ht; \ - else \ - printf "/* `LANG= TZ=UTC date` */\n" >> $(obj)/build.ht; \ - printf "#define COREBOOT_VERSION_TIMESTAMP `LANG= date +%s`\n" >> $(obj)/build.ht; \ - fi - printf "#define COREBOOT_ORIGIN_GIT_REVISION \"`LANG= git log remotes/origin/master -1 --format=format:%h`\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_BUILD_YEAR_BCD 0x`LANG= date +"%y"`\n" >> $(obj)/build.ht - printf "#define COREBOOT_BUILD_MONTH_BCD 0x`LANG= date +"%m"`\n" >> $(obj)/build.ht - printf "#define COREBOOT_BUILD_DAY_BCD 0x`LANG= date +"%d"`\n" >> $(obj)/build.ht - printf "#define COREBOOT_BUILD_WEEKDAY_BCD 0x`LANG= date +"%w"`\n" >> $(obj)/build.ht - printf "#define COREBOOT_DMI_DATE \"`LANG= date +"%m/%d/%Y"`\"\n" >> $(obj)/build.ht - printf "\n" >> $(obj)/build.ht - printf "#define COREBOOT_COMPILE_TIME \"`LANG= date +%T`\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_COMPILE_BY \"$(subst \,@,$(shell PATH=$$PATH:/usr/ucb whoami))\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_COMPILE_HOST \"$(shell hostname -s 2>/dev/null || hostname 2>/dev/null)\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_COMPILE_DOMAIN \"$(shell test `uname -s` = "Linux" && dnsdomainname || domainname 2>/dev/null)\"\n" >> $(obj)/build.ht - printf "#endif\n" >> $(obj)/build.ht + util/genbuild_h/genbuild_h.sh > $(obj)/build.ht mv $(obj)/build.ht $(obj)/build.h $(obj)/ldoptions: $(obj)/config.h diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh new file mode 100755 index 0000000..e79e41b --- /dev/null +++ b/util/genbuild_h/genbuild_h.sh @@ -0,0 +1,87 @@ +#!/bin/sh + +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Sage Electronic Engineering, LLC. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +#get the domain name without hanging the build for an extended period if +#the build system doesn't return a domain name as can happen with the +#dnsdomainname or domainname commands by themselves. +get_domainname() { + MAX_DELAY=1 #maximum time to wait in seconds + TIMEOUT_HOSTNAME_TEXT=unknown.domain #text to return if domain name is not found + TEMPFILE_NAME=coreboot_hostname.txt #temp file to put the domain name into + + # Find the domain name + if [ "$(uname -s)" = "Linux" ] + then + dnsdomainname 2>/dev/null > "$TEMPFILE_NAME" & + else + domainname 2>/dev/null >"$TEMPFILE_NAME" & + fi + + # Get ready to kill the process if it's taking too long + PID=$! + sleep "$MAX_DELAY" && kill "$PID" 2>/dev/null & + wait "$PID" 2>/dev/null + + # See what was found, print our timeout text if the process was killed + # or the domain name if we found one. + HN=$(cat "$TEMPFILE_NAME") + if [ "$HN" = "" ] + then + printf "%s" "$TIMEOUT_HOSTNAME_TEXT" + else + printf "%s" "$HN" + fi + + # Clean up and exit. + rm -f "$TEMPFILE_NAME" +} + +#Print out the information that goes into build.h +printf "/* build system definitions (autogenerated) */\n" +printf "#ifndef __BUILD_H\n" +printf "#define __BUILD_H\n\n" +printf "#define COREBOOT_VERSION %s\n" "\"$KERNELVERSION\"" + +#See if the build is running in a git repo and the git command is available +if [ -d "${top}/.git" ] && [ -f "$(command -v git)" ]; then + printf "/* %s UTC */\n" "$(LANG= TZ=UTC git log --date=local --pretty=format:%cd -1)" + printf "#define COREBOOT_VERSION_TIMESTAMP %s\n" "$(LANG= git log --pretty=format:%ct -1)" + printf "#define COREBOOT_ORIGIN_GIT_REVISION \"%s\"\n" "$(LANG= git log remotes/origin/master -1 --format=format:%h)" +else + printf "/* `LANG= TZ=UTC date` */\n" + printf "#define COREBOOT_VERSION_TIMESTAMP %s\n" "$(LANG= date +%s)" + printf "#define COREBOOT_ORIGIN_GIT_REVISION \"Unknown\"\n" +fi + +printf "#define COREBOOT_EXTRA_VERSION \"%s\"\n" "$COREBOOT_EXTRA_VERSION" +printf "#define COREBOOT_BUILD \"%s\"\n" "$(date)" +printf "#define COREBOOT_BUILD_YEAR_BCD 0x%s\n" "$(date +%y)" +printf "#define COREBOOT_BUILD_MONTH_BCD 0x%s\n" "$(date +%m)" +printf "#define COREBOOT_BUILD_DAY_BCD 0x%s\n" "$(date +%d)" +printf "#define COREBOOT_BUILD_WEEKDAY_BCD 0x%s\n" "$(date +%w)" +printf "#define COREBOOT_DMI_DATE \"%s\"\n" "$(date +%m/%d/%Y)" +printf "\n" +printf "#define COREBOOT_COMPILE_TIME \"%s\"\n" "$(date +%T)" +printf "#define COREBOOT_COMPILE_BY \"%s\"\n" "$(whoami)" +printf "#define COREBOOT_COMPILE_HOST \"%s\"\n" "$(hostname -s 2>/dev/null)" +printf "#define COREBOOT_COMPILE_DOMAIN \"" +get_domainname +printf "\"\n" +printf "#endif\n"

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New patch to review for coreboot: 7ebf17d Makefile.inc: derive all timestamp variable from one timestamp
by Alexander Couzens 06 Mar '15

06 Mar '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8612 -gerrit commit 7ebf17db4423c4f970a54108f706ef765b2a5edf Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Fri Mar 6 02:39:05 2015 +0100 Makefile.inc: derive all timestamp variable from one timestamp Every timestamp variable based on an indepent call of `date`. This could lead in inconsistant timestamps. The master timestamp will be replaced by git commit timestamp when compiling a clean checkout. Change-Id: I664e05b622626f5916086917d1d957ab912ecd67 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- Makefile.inc | 30 +++++++++++++----------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index d209872..4081888 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -269,6 +269,8 @@ additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \ $(objutil)/ifdfake $(objutil)/options $(objutil)/fletcher \ $(objutil)/cbootimage +DATE=$(shell if git update-index -q --refresh >/dev/null; git diff-index --quiet HEAD; then git log --date=local --pretty=format:%ct -1; else date +%s ; fi) + ####################################################################### # generate build support files $(obj)/build.h: .xcompile @@ -278,26 +280,20 @@ $(obj)/build.h: .xcompile printf "#ifndef __BUILD_H\n" >> $(obj)/build.ht printf "#define __BUILD_H\n\n" >> $(obj)/build.ht printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" >> $(obj)/build.ht - if git update-index -q --refresh >/dev/null; git diff-index --quiet HEAD; then \ - printf "/* `LANG= TZ=UTC git log --date=local --pretty=format:%cd -1` UTC */\n" >> $(obj)/build.ht; \ - printf "#define COREBOOT_VERSION_TIMESTAMP `LANG= git log --pretty=format:%ct -1`\n" >> $(obj)/build.ht; \ - else \ - printf "/* `LANG= TZ=UTC date` */\n" >> $(obj)/build.ht; \ - printf "#define COREBOOT_VERSION_TIMESTAMP `LANG= date +%s`\n" >> $(obj)/build.ht; \ - fi + printf "#define COREBOOT_VERSION_TIMESTAMP `LANG= date -d @$(DATE) +%s`\n" >> $(obj)/build.ht; \ printf "#define COREBOOT_ORIGIN_GIT_REVISION \"`LANG= git log remotes/origin/master -1 --format=format:%h`\"\n" >> $(obj)/build.ht printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_BUILD_YEAR_BCD 0x`LANG= date +"%y"`\n" >> $(obj)/build.ht - printf "#define COREBOOT_BUILD_MONTH_BCD 0x`LANG= date +"%m"`\n" >> $(obj)/build.ht - printf "#define COREBOOT_BUILD_DAY_BCD 0x`LANG= date +"%d"`\n" >> $(obj)/build.ht - printf "#define COREBOOT_BUILD_WEEKDAY_BCD 0x`LANG= date +"%w"`\n" >> $(obj)/build.ht - printf "#define COREBOOT_DMI_DATE \"`LANG= date +"%m/%d/%Y"`\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_BUILD \"`LANG= date -d @$(DATE)`\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_BUILD_YEAR_BCD 0x`LANG= date -d @$(DATE) +"%y"`\n" >> $(obj)/build.ht + printf "#define COREBOOT_BUILD_MONTH_BCD 0x`LANG= date -d @$(DATE) +"%m"`\n" >> $(obj)/build.ht + printf "#define COREBOOT_BUILD_DAY_BCD 0x`LANG= date -d @$(DATE) +"%d"`\n" >> $(obj)/build.ht + printf "#define COREBOOT_BUILD_WEEKDAY_BCD 0x`LANG= date -d @$(DATE) +"%w"`\n" >> $(obj)/build.ht + printf "#define COREBOOT_DMI_DATE \"`LANG= date -d @$(DATE) +"%m/%d/%Y"`\"\n" >> $(obj)/build.ht printf "\n" >> $(obj)/build.ht - printf "#define COREBOOT_COMPILE_TIME \"`LANG= date +%T`\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_COMPILE_BY \"$(subst \,@,$(shell PATH=$$PATH:/usr/ucb whoami))\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_COMPILE_HOST \"$(shell hostname -s 2>/dev/null || hostname 2>/dev/null)\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_COMPILE_DOMAIN \"$(shell test `uname -s` = "Linux" && dnsdomainname || domainname 2>/dev/null)\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_COMPILE_TIME \"`LANG= date -d @$(DATE) +%T`\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_COMPILE_BY \"builduser\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_COMPILE_HOST \"buildhost\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_COMPILE_DOMAIN \"builddomain\"\n" >> $(obj)/build.ht printf "#endif\n" >> $(obj)/build.ht mv $(obj)/build.ht $(obj)/build.h

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New patch to review for coreboot: 52beddd Makefile.inc: fix build timestamp logic for clean builds
by Alexander Couzens 06 Mar '15

06 Mar '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8611 -gerrit commit 52beddd3949f89d6c2b1459bfbbeb310fe8d0f24 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Fri Mar 6 01:18:15 2015 +0100 Makefile.inc: fix build timestamp logic for clean builds When the build system detects a clean checkout it uses the git commit timestamp as `now` timestamp. The logic was wrong and it detect a clean checkout when it was dirty and vice versa. Change-Id: I20fc8648c84882fbc43ea7964aa4204941580f1e Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index eb8b601..d209872 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -278,7 +278,7 @@ $(obj)/build.h: .xcompile printf "#ifndef __BUILD_H\n" >> $(obj)/build.ht printf "#define __BUILD_H\n\n" >> $(obj)/build.ht printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" >> $(obj)/build.ht - if git update-index -q --refresh >/dev/null; ! git diff-index --quiet HEAD; then \ + if git update-index -q --refresh >/dev/null; git diff-index --quiet HEAD; then \ printf "/* `LANG= TZ=UTC git log --date=local --pretty=format:%cd -1` UTC */\n" >> $(obj)/build.ht; \ printf "#define COREBOOT_VERSION_TIMESTAMP `LANG= git log --pretty=format:%ct -1`\n" >> $(obj)/build.ht; \ else \

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Patch set updated for coreboot: 9dd70ec lenovo: fix smi gpe + wakeup pin for t420s t520 t530 x220 x230
by Nicolas Reinecke 05 Mar '15

05 Mar '15

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8358 -gerrit commit 9dd70ec677612b62e13337ea9e96d1d9b136d655 Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sun Feb 1 02:53:35 2015 +0100 lenovo: fix smi gpe + wakeup pin for t420s t520 t530 x220 x230 Set correct gpio routing and enable bits for EC SMI gpio and EC WAKE gpio. Verified with schematics. Change-Id: Ie3b98c4456a870c881e7663b19eb8ca8e5564c5c Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/mainboard/lenovo/t420s/devicetree.cb | 2 +- src/mainboard/lenovo/t420s/smihandler.c | 19 +++++++++++-------- src/mainboard/lenovo/t520/devicetree.cb | 2 +- src/mainboard/lenovo/t520/smihandler.c | 19 +++++++++++-------- src/mainboard/lenovo/t530/devicetree.cb | 2 +- src/mainboard/lenovo/t530/smihandler.c | 19 +++++++++++-------- src/mainboard/lenovo/x220/devicetree.cb | 2 +- src/mainboard/lenovo/x220/smihandler.c | 19 +++++++++++-------- src/mainboard/lenovo/x230/devicetree.cb | 2 +- src/mainboard/lenovo/x230/smihandler.c | 19 +++++++++++-------- 10 files changed, 60 insertions(+), 45 deletions(-) diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 990b576..7fd6a53 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -54,7 +54,7 @@ chip northbridge/intel/sandybridge # 2 SCI (if corresponding GPIO_EN bit is also set) register "alt_gp_smi_en" = "0x0000" register "gpi1_routing" = "2" - register "gpi8_routing" = "2" + register "gpi13_routing" = "2" # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock) register "sata_port_map" = "0x17" diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c index 6c80573..27a33cf 100644 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ b/src/mainboard/lenovo/t420s/smihandler.c @@ -33,6 +33,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> +#define GPE_EC_SCI 1 +#define GPE_EC_WAKE 13 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -108,7 +111,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << 12)) + if (gpi_sts & (1 << GPE_EC_SCI)) mainboard_smi_handle_ec_sci(); } @@ -129,8 +132,8 @@ int mainboard_smi_apmc(u8 data) case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); - /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + /* route EC_SCI to SCI */ + outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02; @@ -142,8 +145,8 @@ int mainboard_smi_apmc(u8 data) /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't provide a EC query function */ ec_set_ports(0x66, 0x62); - /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, + /* route EC_SCI# to SMI */ + outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; @@ -183,11 +186,11 @@ void mainboard_smi_sleep(u8 slp_typ) u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); + outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN); gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << 26); - gpe_rout |= (2 << 26); + gpe_rout &= ~(3 << (GPE_EC_WAKE * 2)); + gpe_rout |= (2 << (GPE_EC_WAKE * 2)); pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); } } diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index d2a4d6b..bf575d8 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -50,7 +50,7 @@ chip northbridge/intel/sandybridge # 2 SCI (if corresponding GPIO_EN bit is also set) register "alt_gp_smi_en" = "0x0000" register "gpi1_routing" = "2" - register "gpi8_routing" = "2" + register "gpi13_routing" = "2" # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock) register "sata_port_map" = "0x1f" diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c index bb3ad78..479ce0a 100644 --- a/src/mainboard/lenovo/t520/smihandler.c +++ b/src/mainboard/lenovo/t520/smihandler.c @@ -33,6 +33,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> +#define GPE_EC_SCI 1 +#define GPE_EC_WAKE 13 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -103,7 +106,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << 12)) + if (gpi_sts & (1 << GPE_EC_SCI)) mainboard_smi_handle_ec_sci(); } @@ -124,8 +127,8 @@ int mainboard_smi_apmc(u8 data) case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); - /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + /* route EC_SCI to SCI */ + outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02; @@ -137,8 +140,8 @@ int mainboard_smi_apmc(u8 data) /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't provide a EC query function */ ec_set_ports(0x66, 0x62); - /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, + /* route EC_SCI# to SMI */ + outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; @@ -178,11 +181,11 @@ void mainboard_smi_sleep(u8 slp_typ) u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); + outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN); gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << 26); - gpe_rout |= (2 << 26); + gpe_rout &= ~(3 << (GPE_EC_WAKE * 2)); + gpe_rout |= (2 << (GPE_EC_WAKE * 2)); pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); } } diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index c44f927..6b769b0 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -50,7 +50,7 @@ chip northbridge/intel/sandybridge # 2 SCI (if corresponding GPIO_EN bit is also set) register "alt_gp_smi_en" = "0x0000" register "gpi1_routing" = "2" - register "gpi8_routing" = "2" + register "gpi13_routing" = "2" # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock) register "sata_port_map" = "0x3f" diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c index 6f6cca1..372f280 100644 --- a/src/mainboard/lenovo/t530/smihandler.c +++ b/src/mainboard/lenovo/t530/smihandler.c @@ -33,6 +33,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> +#define GPE_EC_SCI 1 +#define GPE_EC_WAKE 13 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -108,7 +111,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << 12)) + if (gpi_sts & (1 << GPE_EC_SCI)) mainboard_smi_handle_ec_sci(); } @@ -129,8 +132,8 @@ int mainboard_smi_apmc(u8 data) case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); - /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + /* route EC_SCI to SCI */ + outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02; @@ -142,8 +145,8 @@ int mainboard_smi_apmc(u8 data) /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't provide a EC query function */ ec_set_ports(0x66, 0x62); - /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, + /* route EC_SCI# to SMI */ + outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; @@ -183,11 +186,11 @@ void mainboard_smi_sleep(u8 slp_typ) u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); + outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN); gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << 26); - gpe_rout |= (2 << 26); + gpe_rout &= ~(3 << (GPE_EC_WAKE * 2)); + gpe_rout |= (2 << (GPE_EC_WAKE * 2)); pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); } } diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 982e30b..6eb3b15 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -54,7 +54,7 @@ chip northbridge/intel/sandybridge # 2 SCI (if corresponding GPIO_EN bit is also set) register "alt_gp_smi_en" = "0x0000" register "gpi1_routing" = "2" - register "gpi8_routing" = "2" + register "gpi13_routing" = "2" # Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata) register "sata_port_map" = "0x7" diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c index 6f6cca1..372f280 100644 --- a/src/mainboard/lenovo/x220/smihandler.c +++ b/src/mainboard/lenovo/x220/smihandler.c @@ -33,6 +33,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> +#define GPE_EC_SCI 1 +#define GPE_EC_WAKE 13 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -108,7 +111,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << 12)) + if (gpi_sts & (1 << GPE_EC_SCI)) mainboard_smi_handle_ec_sci(); } @@ -129,8 +132,8 @@ int mainboard_smi_apmc(u8 data) case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); - /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + /* route EC_SCI to SCI */ + outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02; @@ -142,8 +145,8 @@ int mainboard_smi_apmc(u8 data) /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't provide a EC query function */ ec_set_ports(0x66, 0x62); - /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, + /* route EC_SCI# to SMI */ + outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; @@ -183,11 +186,11 @@ void mainboard_smi_sleep(u8 slp_typ) u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); + outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN); gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << 26); - gpe_rout |= (2 << 26); + gpe_rout &= ~(3 << (GPE_EC_WAKE * 2)); + gpe_rout |= (2 << (GPE_EC_WAKE * 2)); pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); } } diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 3a05b5a..08c937f 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -54,7 +54,7 @@ chip northbridge/intel/sandybridge # 2 SCI (if corresponding GPIO_EN bit is also set) register "alt_gp_smi_en" = "0x0000" register "gpi1_routing" = "2" - register "gpi8_routing" = "2" + register "gpi13_routing" = "2" # Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata) register "sata_port_map" = "0x7" diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c index 6f6cca1..372f280 100644 --- a/src/mainboard/lenovo/x230/smihandler.c +++ b/src/mainboard/lenovo/x230/smihandler.c @@ -33,6 +33,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> +#define GPE_EC_SCI 1 +#define GPE_EC_WAKE 13 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -108,7 +111,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << 12)) + if (gpi_sts & (1 << GPE_EC_SCI)) mainboard_smi_handle_ec_sci(); } @@ -129,8 +132,8 @@ int mainboard_smi_apmc(u8 data) case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); - /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + /* route EC_SCI to SCI */ + outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02; @@ -142,8 +145,8 @@ int mainboard_smi_apmc(u8 data) /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't provide a EC query function */ ec_set_ports(0x66, 0x62); - /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, + /* route EC_SCI# to SMI */ + outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; @@ -183,11 +186,11 @@ void mainboard_smi_sleep(u8 slp_typ) u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); + outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN); gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << 26); - gpe_rout |= (2 << 26); + gpe_rout &= ~(3 << (GPE_EC_WAKE * 2)); + gpe_rout |= (2 << (GPE_EC_WAKE * 2)); pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); } }

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Patch merged into coreboot/master: aab66b1 AMD Fam10h: sanity check some CPU data
by gerrit＠coreboot.org 05 Mar '15

05 Mar '15

the following patch was just integrated into master: commit aab66b1dc7908366f35ed58b774bb2dbe214278c Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Feb 22 16:27:56 2015 +0100 AMD Fam10h: sanity check some CPU data If a certain register returns crap values, we determine core_power using an uninitialized variable. That doesn't sound healthy. Change-Id: I1e890b78bfcc3bf0255a3d4f6561a783134b1719 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/8508 Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8508 for details. -gerrit

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New patch to review for coreboot: 4238955 AMD Fam10h: Only create _PR scope if it is filled in
by Patrick Georgi 05 Mar '15

05 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8610 -gerrit commit 423895528715e721493b958845ecacd4de0f8ccc Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Mar 5 20:18:21 2015 +0100 AMD Fam10h: Only create _PR scope if it is filled in The former pstates_algorithm() function has two early exit points now, and so it might never get around to writing pstates data. Change-Id: I19ca937375c6d33b78bd5b1859fa5c25473be9b6 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/cpu/amd/model_10xxx/fidvid.c | 2 +- src/cpu/amd/model_10xxx/powernow_acpi.c | 13 ++++--------- 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index a3f3075..798d538 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -79,7 +79,7 @@ Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010 11.- finalPstateChange() from init_fidvid_Stage2 (BKDG says just "may", anyway) 12.- generate ACPI for p-states. - generated in powernow_acpi.c pstates_algorithm() + generated in powernow_acpi.c amd_generate_powernow() "must also be completed" diff --git a/src/cpu/amd/model_10xxx/powernow_acpi.c b/src/cpu/amd/model_10xxx/powernow_acpi.c index 09726a0..bf97099 100644 --- a/src/cpu/amd/model_10xxx/powernow_acpi.c +++ b/src/cpu/amd/model_10xxx/powernow_acpi.c @@ -79,7 +79,7 @@ static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u32 *pstate_p * processor combination is installed. If it does break please fix the * code in the proper locations! */ -static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) +void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) { u8 processor_brand[49]; u32 *v; @@ -260,17 +260,12 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) Pstate_latency[index]); } + char pscope[] = "\\_PR"; + + acpigen_write_scope(pscope); for (index = 0; index < cmp_cap; index++) write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_power, Pstate_latency, Pstate_control, Pstate_status, index, pcontrol_blk, plen, onlyBSP); -} - -void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) -{ - char pscope[] = "\\_PR"; - - acpigen_write_scope(pscope); - pstates_algorithm(pcontrol_blk, plen, onlyBSP); acpigen_pop_len(); }

1 0

Patch set updated for coreboot: 1319298 AMD Fam10h: sanity check some CPU data
by Patrick Georgi 05 Mar '15

05 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8508 -gerrit commit 131929828c6ee5c1b26de3ca3a81972a30b4387b Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Feb 22 16:27:56 2015 +0100 AMD Fam10h: sanity check some CPU data If a certain register returns crap values, we determine core_power using an uninitialized variable. That doesn't sound healthy. Change-Id: I1e890b78bfcc3bf0255a3d4f6561a783134b1719 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Found-by: Coverity Scan --- src/cpu/amd/model_10xxx/powernow_acpi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/cpu/amd/model_10xxx/powernow_acpi.c b/src/cpu/amd/model_10xxx/powernow_acpi.c index feb8f01..09726a0 100644 --- a/src/cpu/amd/model_10xxx/powernow_acpi.c +++ b/src/cpu/amd/model_10xxx/powernow_acpi.c @@ -223,6 +223,11 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) case 0x3: expanded_cpuidv = 1000; break; + default: + printk(BIOS_ERR, "%s:%s:%d: Invalid cpuidv, " + "not generating pstate tables.\n", + __FILE__, __func__, __LINE__); + return; } core_power = (core_voltage * cpuidd) / (expanded_cpuidv * 10);

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coreboot-gerrit March 2015