coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: google/chell: Turn on keyboard backlight in romstage
by gerrit＠coreboot.org 18 Nov '15

18 Nov '15

the following patch was just integrated into master: commit 3db94686e596bc87714f75077d609591c013c5ec Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Nov 12 16:39:36 2015 -0800 google/chell: Turn on keyboard backlight in romstage Use the keyboard backlight to provide indication that the system is booting. This is useful for determining that a system is in S0 and is running BIOS code. BUG=chrome-os-partner:47435 BRANCH=none TEST=boot on chell and see keyboard backlight come on early Change-Id: I43e699bcc2f34998d3d6ce33ce72c7b04b55c146 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a3a0147b6de681365a9c995175076d5f397016fb Original-Change-Id: I2441c28431e71b13b70e6533e175d29ccfd8d7e9 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312358 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/12448 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12448 for details. -gerrit

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Patch merged into coreboot/master: google/lars: Enable wake from touch pad
by gerrit＠coreboot.org 18 Nov '15

18 Nov '15

the following patch was just integrated into master: commit 2b7103cb0ff066e3fa1fac5a40fe361334dd6570 Author: david <david_wu(a)quantatw.com> Date: Tue Nov 10 15:00:18 2015 +0800 google/lars: Enable wake from touch pad This patch enables GPP_B5 as ACPI_SCI for wake. It also defines touchpad wake device in ACPI with GPE0_DW0_05 for _PRW. BUG=none BRANCH=none TEST=emerge-lars coreboot Change-Id: I2b65f6a37783ecdbdbc32ebe613243e042c865e9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ec5b629f920984564f12f2c09458ed300d031f69 Original-Change-Id: I9bd2b3595ae833fa5d07d97a7cda4a29041be837 Original-Signed-off-by: David Wu <David_Wu(a)quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311890 Original-Commit-Ready: David Wu <david_wu(a)quantatw.com> Original-Tested-by: David Wu <david_wu(a)quantatw.com> Original-Reviewed-by: Shawn N <shawnn(a)chromium.org> Reviewed-on: http://review.coreboot.org/12449 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12449 for details. -gerrit

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Patch merged into coreboot/master: google/lars: enable wakeup from S0ix using headset button
by gerrit＠coreboot.org 18 Nov '15

18 Nov '15

the following patch was just integrated into master: commit c494c7d68dceeeff007e6b2743669fdbdfbcf50a Author: david <david_wu(a)quantatw.com> Date: Thu Nov 12 12:52:20 2015 +0800 google/lars: enable wakeup from S0ix using headset button Kernel needs to set Audio IRQ as wake capable. BUG=None BRANCH=None TEST=emerge-lars coreboot Change-Id: Ib7f0fc52baa006d992a2f91a63417e3f76817634 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 32d82ac48c6f830fbb09b776d0adaf6b7a727416 Original-Change-Id: I3fd70ac99c623a99b07fa1a185ebace8c1fc3d69 Original-Signed-off-by: David Wu <David_Wu(a)quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/312172 Original-Commit-Ready: David Wu <david_wu(a)quantatw.com> Original-Tested-by: David Wu <david_wu(a)quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/12450 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12450 for details. -gerrit

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Patch merged into coreboot/master: google/veyron*: Pulse the i2c clock once if sda was low
by gerrit＠coreboot.org 18 Nov '15

18 Nov '15

the following patch was just integrated into master: commit 7760a47892bfec559d11e14c075770e79b1293e1 Author: Douglas Anderson <dianders(a)chromium.org> Date: Tue Oct 27 16:05:15 2015 -0700 google/veyron*: Pulse the i2c clock once if sda was low On one particular TV the TV was holding SDA low when it came up. It would release the SDA when the SCL went low the first time. Unfortunately the HDMI i2c port wouldn't transmit until the SDA was released. Let's detect this case and insert a bogus clock pulse to try to get the other side to release SDA. It's unclear why the kernel doesn't have this problem. BRANCH=none BUG=chrome-os-partner:46256 TEST=Insignia TV works now Change-Id: Ic9d27eb69bdc9c5fb11a68258e0c755cdc8b79d7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 356ee7503f04e741a41be37ad573b588067b7114 Original-Change-Id: I4b6361877e0576cc4ea2f643f073f1aab660e434 Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309258 Original-Reviewed-by: Agnes Cheng <agnescheng(a)google.com> Original-Commit-Queue: Agnes Cheng <agnescheng(a)google.com> Original-Trybot-Ready: Agnes Cheng <agnescheng(a)google.com> Original-Tested-by: Agnes Cheng <agnescheng(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309546 Original-Commit-Ready: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/12451 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12451 for details. -gerrit

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Patch merged into coreboot/master: google/veyron_emile: retrieve the MAC address from vpd
by gerrit＠coreboot.org 18 Nov '15

18 Nov '15

the following patch was just integrated into master: commit 71c0aa29fa83219e76af70dd452b6b2e97e4dfbb Author: ZhengShunQian <zhengsq(a)rock-chips.com> Date: Tue Nov 10 16:16:14 2015 +0800 google/veyron_emile: retrieve the MAC address from vpd Emile has a on board ethernet. BUG=chrome-os-partner:47465 TEST=vpd -s ethernet_mac0=001122334455 build and check the MAC address Change-Id: I90ed0ed1253c804568fcdd3dd212bb062a48c836 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 99b275c594196de0811f68380e66c226d2649927 Original-Change-Id: I1690a1f39090c57c64d4965092c80eef9070babf Original-Signed-off-by: ZhengShunQian <zhengsq(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311900 Original-Commit-Ready: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/12452 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12452 for details. -gerrit

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Patch merged into coreboot/master: google/chell: disable power rails in sleep path
by gerrit＠coreboot.org 18 Nov '15

18 Nov '15

the following patch was just integrated into master: commit d49d42f629e09a36e9ce498319d5ad2fb4744a32 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Nov 11 16:50:52 2015 -0600 google/chell: disable power rails in sleep path For the rails controllable by the host processor through gpios turn them off in the sleep paths. The result is that S3 and S5 will turn off those rails. BUG=chrome-os-partner:47228 BRANCH=None TEST=Built for chell. Change-Id: I5843f13be43a6ec143600585a5a0c47563e533dd Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ddd5860dc0cfee68ec2f77f4931665740bede08c Original-Change-Id: Ife0e2fb11373dd129e20b914b45cd5b56c3493f7 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312321 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/12446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12446 for details. -gerrit

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Patch merged into coreboot/master: google/glados: disable power rails in sleep path
by gerrit＠coreboot.org 18 Nov '15

18 Nov '15

the following patch was just integrated into master: commit ce6c35699b605dd097dd25642c480738b9738222 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Nov 11 16:46:27 2015 -0600 google/glados: disable power rails in sleep path For the rails controllable by the host processor through gpios turn them off in the sleep paths. The result is that S3 and S5 will turn off those rails. BUG=chrome-os-partner:47228 BRANCH=None TEST=Built and booted glados. Suspended and resumed. Change-Id: I6d45683b64ca5f7c3c47e11f95951bd2d9abf31e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ed432e2b5535da6f872a53b76886d983f00b4e8e Original-Change-Id: I94d7e0b00bf7e7da8dc59f299e41b72e8fcb64f4 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312320 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/12445 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12445 for details. -gerrit

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Patch set updated for coreboot: AMD/Bettong: add FCH's GPIO, UART & I2C support
by Zheng Bao 18 Nov '15

18 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11750 -gerrit commit dbf6a6d28f8d5d262dfcb3440e2c37b6ca7ea336 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Wed Nov 18 22:52:37 2015 +0800 AMD/Bettong: add FCH's GPIO, UART & I2C support Merlin Falcon's FCH has GPIO, UART and I2C. All of them are controlled by registers mapped at MMIO space. This ASL code is used for Windows drivers. TEST: 1. Boot Windows 8 or Windows 10. 2. Install AMD Catalyst driver. 3. AMD FPIO, UART and I2C can be found in device manager. 4. I2C passed Multi Interface Test Tool (MITT) test. Change-Id: I7ffe3fe0046d9a078cc38176c29a8e334646a5a3 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bettong/acpi/carrizo_fch.asl | 101 +++++++++++++++++++++++++ src/mainboard/amd/bettong/dsdt.asl | 3 + 2 files changed, 104 insertions(+) diff --git a/src/mainboard/amd/bettong/acpi/carrizo_fch.asl b/src/mainboard/amd/bettong/acpi/carrizo_fch.asl new file mode 100644 index 0000000..5bfb366 --- /dev/null +++ b/src/mainboard/amd/bettong/acpi/carrizo_fch.asl @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +Device(GPIO) { + Name (_HID, "AMD0030") + Name (_CID, "AMD0030") + Name(_UID, 0) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () { + // + // Interrupt resource. In this example, banks 0 & 1 share the same + // interrupt to the parent controller and similarly banks 2 & 3. + // + // N.B. The definition below is chosen for an arbitrary + // test platform. It needs to be changed to reflect the hardware + // configuration of the actual platform + // + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + + // + // Memory resource. The definition below is chosen for an arbitrary + // test platform. It needs to be changed to reflect the hardware + // configuration of the actual platform. + // + Memory32Fixed(ReadWrite, 0xFED81500, 0x300) + }) + + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) { + Return (0x0F) + } +} + +Device(FUR0) { + Name(_HID,"AMD0020") + Name(_UID,0x0) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {10} + Memory32Fixed(ReadWrite, 0xFEDC6000, 0x2000) + }) + Method (_STA, 0x0, NotSerialized) { + Return (0x0F) + } +} + +Device(FUR1) { + Name(_HID,"AMD0020") + Name(_UID,0x1) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {11} + Memory32Fixed(ReadWrite, 0xFEDC8000, 0x2000) + }) + Method (_STA, 0x0, NotSerialized) { + Return (0x0F) + } +} + +Device(I2CA) { + Name(_HID,"AMD0010") + Name(_UID,0x0) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {3} + Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000) + }) + + Method (_STA, 0x0, NotSerialized) { + Return (0x0F) + } +} + +Device(I2CB) +{ + Name(_HID,"AMD0010") + Name(_UID,0x1) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {15} + Memory32Fixed(ReadWrite, 0xFEDC3000, 0x1000) + }) + Method (_STA, 0x0, NotSerialized) { + Return (0x0F) + } +} diff --git a/src/mainboard/amd/bettong/dsdt.asl b/src/mainboard/amd/bettong/dsdt.asl index 888d5cd..2e6c96c 100644 --- a/src/mainboard/amd/bettong/dsdt.asl +++ b/src/mainboard/amd/bettong/dsdt.asl @@ -69,6 +69,9 @@ DefinitionBlock ( /* Describe PCI INT[A-H] for the Southbridge */ #include <southbridge/amd/pi/hudson/acpi/pci_int.asl> + /* Describe the devices in the Southbridge */ + #include "acpi/carrizo_fch.asl" + } /* End \_SB scope */ /* Describe SMBUS for the Southbridge */

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Patch merged into coreboot/master: mb/roda/rk9: Fix cbmem recovery on resume path
by gerrit＠coreboot.org 18 Nov '15

18 Nov '15

the following patch was just integrated into master: commit 8a44b0b18c8618189b6fb4522fce59582b3df43e Author: Nico Huber <nico.h(a)gmx.de> Date: Thu Nov 12 20:16:18 2015 +0100 mb/roda/rk9: Fix cbmem recovery on resume path By calling cbmem_recovery() with `0`, we rewrote the cbmem table even on the resume path. By that, we lost the OS' resume vector and ended up loading the payload. Change-Id: Ic24a12d4143d6924321b1d01f07a467c58c4e9ea Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: http://review.coreboot.org/12420 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12420 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/sandybridge: Fix PEG disablement
by gerrit＠coreboot.org 18 Nov '15

18 Nov '15

the following patch was just integrated into master: commit aad34cda4bc9c14ed10b00fe5da3f32233257913 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Wed Oct 21 18:05:01 2015 +0200 nb/intel/sandybridge: Fix PEG disablement Fix regression introduced by: 3660c0fc658e4e20ef079f762dfc7ad05c83544c "northbridge/intel/sandybridge: Enable PEG clock-gating on demand" Issue observed: GNU/Linux kernel crashes in earlyinit on systems without PEG devices. The crash occurs on every boot in different functions. There's no problem on systems with PEG enabled. Test system: * Lenovo T530 * Intel Core i5-3320M CPU * Fedora GNU/Linux 4.1 * PEG disabled in devicetree Problem description: Tests shows that modifing PEG chicken bit or device enable bits after setting BIOS_RESET_CPL causes random crashes in GNU/Linux. Problem solution: Disable PEG devices before setting BIOS_RESET_CPL. Final testing results: No more random kernel crashes. Change-Id: I4a967c2d00d7d1e4426cf5abdd5f616c21557da7 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: http://review.coreboot.org/12112 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See http://review.coreboot.org/12112 for details. -gerrit

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coreboot-gerrit November 2015