coreboot-gerrit November 2015

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Patch set updated for coreboot: amd/amdmct/mct_ddr3: Fix poor performance on Family 15h CPUs
by Timothy Pearson 18 Nov '15

18 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12029 -gerrit commit 0bdf3f617ec835203dcc671af96122f2732cbaf3 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Aug 7 19:05:29 2015 -0500 amd/amdmct/mct_ddr3: Fix poor performance on Family 15h CPUs Change-Id: Ib6bc197e43e40ba2b923b1eb1229bacafc8be360 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 370 +++++++++++++++++++++---- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 1 + src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 65 ++++- src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 49 +++- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 195 ++++++++++++- src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 4 + 6 files changed, 604 insertions(+), 80 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 283d897..b80918c 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -32,6 +32,8 @@ * supported. */ +// #define DEBUG_DIMM_SPD 1 + static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void DQSTiming_D(struct MCTStatStruc *pMCTstat, @@ -168,7 +170,8 @@ static u32 mct_MR1Odt_RDimm(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel); static u32 mct_DramTermDyn_RDimm(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dimm); -static u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, u8 dct, u32 misc2); +static u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, + uint8_t dct, uint32_t misc2, uint32_t DramControl); static void mct_BeforeDQSTrainSamp(struct DCTStatStruc *pDCTstat); static void mct_WriteLevelization_HW(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, uint8_t Pass); @@ -1366,6 +1369,8 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc static void set_2t_configuration(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { + printk(BIOS_DEBUG, "%s: Start\n", __func__); + uint32_t dev; uint32_t reg; uint32_t dword; @@ -1388,6 +1393,8 @@ static void set_2t_configuration(struct MCTStatStruc *pMCTstat, else dword &= ~(0x1 << 20); /* Clear 2T CMD mode */ Set_NB32_DCT(dev, dct, reg, dword); + + printk(BIOS_DEBUG, "%s: Done\n", __func__); } static void precise_ndelay_fam15(struct MCTStatStruc *pMCTstat, uint32_t nanoseconds) { @@ -2009,6 +2016,7 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, /* Disable training mode */ uint8_t lane; uint8_t dimm; + uint16_t sword; uint8_t receiver; uint8_t max_lane; uint8_t ecc_enabled; @@ -2023,21 +2031,37 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, uint16_t twrwrdd; uint16_t cdd_twrwrdd; uint16_t twrrd; + uint16_t cdd_twrrd; + uint16_t cdd_trwtto; uint16_t trwtto; uint8_t first_dimm; uint16_t delay; uint16_t delay2; + uint8_t min_value; + uint8_t write_early; uint8_t read_odt_delay; uint8_t write_odt_delay; + uint8_t buffer_data_delay; + int16_t latency_difference; uint16_t difference; uint16_t current_total_delay_1[MAX_BYTE_LANES]; uint16_t current_total_delay_2[MAX_BYTE_LANES]; + uint8_t ddr_voltage_index; + uint8_t max_dimms_installable; /* FIXME * This should be platform configurable */ uint8_t dimm_event_l_pin_support = 0; + if (pDCTstat->DIMMValidDCT[dct] == 0) + ddr_voltage_index = 1; + else + ddr_voltage_index = dct_ddr_voltage_index(pDCTstat, dct); + + ddr_voltage_index = dct_ddr_voltage_index(pDCTstat, dct); + max_dimms_installable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); + ecc_enabled = !!(pMCTstat->GStatus & 1 << GSB_ECCDIMMs); if (ecc_enabled) max_lane = 9; @@ -2071,6 +2095,24 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, else write_odt_delay = 0; + dword = (Get_NB32_DCT(dev, dct, 0xa8) >> 24) & 0x3; + write_early = dword / 2; + + latency_difference = Get_NB32_DCT(dev, dct, 0x200) & 0x1f; + dword = Get_NB32_DCT(dev, dct, 0x20c) & 0x1f; + latency_difference -= dword; + + if (pDCTstat->Status & (1 << SB_LoadReduced)) { + /* LRDIMM */ + + /* TODO + * Implement LRDIMM support + * See Fam15h BKDG Rev. 3.14 section 2.10.5.5 + */ + } else { + buffer_data_delay = 0; + } + /* TODO: * Adjust trdrdsddc if four-rank DIMMs are installed per * section 2.10.5.5.1 of the Family 15h BKDG. @@ -2106,7 +2148,7 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, } /* Convert the difference to MEMCLKs */ - cdd_trdrddd = (((cdd_trdrddd >> 5) & 0x1f) + 1) / 2; + cdd_trdrddd = (((cdd_trdrddd + (1 << 6) - 1) >> 6) & 0xf); /* Calculate Trdrddd */ delay = (read_odt_delay + 3) * 2; @@ -2152,7 +2194,7 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, } /* Convert the difference to MEMCLKs */ - cdd_twrwrdd = (((cdd_twrwrdd >> 5) & 0x1f) + 1) / 2; + cdd_twrwrdd = (((cdd_twrwrdd + (1 << 6) - 1) >> 6) & 0xf); /* Calculate Twrwrdd */ delay = (write_odt_delay + 3) * 2; @@ -2171,6 +2213,107 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, dword &= ~(0x1 << 18); /* DisAutoRefresh = 0 */ Set_NB32_DCT(dev, dct, 0x8c, dword); /* DRAM Timing High */ + /* Configure power saving options */ + dword = Get_NB32_DCT(dev, dct, 0xa8); /* Dram Miscellaneous 2 */ + dword |= (0x1 << 22); /* PrtlChPDEnhEn = 0x1 */ + dword |= (0x1 << 21); /* AggrPDEn = 0x1 */ + Set_NB32_DCT(dev, dct, 0xa8, dword); /* Dram Miscellaneous 2 */ + + /* Configure partial power down delay */ + dword = Get_NB32(dev, 0x244); /* DRAM Controller Miscellaneous 3 */ + dword &= ~0xf; /* PrtlChPDDynDly = 0x2 */ + dword |= 0x2; + Set_NB32(dev, 0x244, dword); /* DRAM Controller Miscellaneous 3 */ + + /* Configure power save delays */ + delay = 0xa; + delay2 = 0x3; + + /* Family 15h BKDG Table 214 */ + if ((pDCTstat->Status & (1 << SB_Registered)) + || (pDCTstat->Status & (1 << SB_LoadReduced))) { + if (memclk_index <= 0x6) { + if (ddr_voltage_index < 0x4) + /* 1.5 or 1.35V */ + delay2 = 0x3; + else + /* 1.25V */ + delay2 = 0x4; + } + else if ((memclk_index == 0xa) + || (memclk_index == 0xe)) + delay2 = 0x4; + else if (memclk_index == 0x12) + delay2 = 0x5; + else if (memclk_index == 0x16) + delay2 = 0x6; + } else { + if (memclk_index <= 0x6) + delay2 = 0x3; + else if ((memclk_index == 0xa) + || (memclk_index == 0xe)) + delay2 = 0x4; + else if (memclk_index == 0x12) + delay2 = 0x5; + else if (memclk_index == 0x16) + delay2 = 0x6; + } + + /* Family 15h BKDG Table 215 */ + if (memclk_index <= 0x6) + delay = 0xa; + else if (memclk_index == 0xa) + delay = 0xd; + else if (memclk_index == 0xe) + delay = 0x10; + else if (memclk_index == 0x12) + delay = 0x14; + else if (memclk_index == 0x16) + delay = 0x17; + + dword = Get_NB32_DCT(dev, dct, 0x248); /* Dram Power Management 0 */ + dword &= ~(0x3f << 24); /* AggrPDDelay = 0x0 */ + dword &= ~(0x3f << 16); /* PchgPDEnDelay = 0x1 */ + dword |= (0x1 << 16); + dword &= ~(0x1f << 8); /* Txpdll = delay */ + dword |= ((delay & 0x1f) << 8); + dword &= ~0xf; /* Txp = delay2 */ + dword |= delay2 & 0xf; + Set_NB32_DCT(dev, dct, 0x248, dword); /* Dram Power Management 0 */ + + /* Family 15h BKDG Table 216 */ + if (memclk_index <= 0x6) { + delay = 0x5; + delay2 = 0x3; + } + else if (memclk_index == 0xa) { + delay = 0x6; + delay2 = 0x3; + } + else if (memclk_index == 0xe) { + delay = 0x7; + delay2 = 0x4; + } + else if (memclk_index == 0x12) { + delay = 0x8; + delay2 = 0x4; + } + else if (memclk_index == 0x16) { + delay = 0xa; + delay2 = 0x5; + } + + dword = Get_NB32_DCT(dev, dct, 0x24c); /* Dram Power Management 1 */ + dword &= ~(0x3f << 24); /* Tcksrx = delay */ + dword |= ((delay & 0x3f) << 24); + dword &= ~(0x3f << 16); /* Tcksre = delay */ + dword |= ((delay & 0x3f) << 16); + dword &= ~(0x3f << 8); /* Tckesr = delay2 + 1 */ + dword |= (((delay2 + 1) & 0x3f) << 8); + dword &= ~0xf; /* Tpd = delay2 */ + dword |= delay2 & 0xf; + Set_NB32_DCT(dev, dct, 0x24c, dword); /* Dram Power Management 1 */ + dword = Get_NB32_DCT(dev, dct, 0x94); /* DRAM Configuration High */ dword |= (0xf << 24); /* DcqBypassMax = 0xf */ dword |= (0x1 << 22); /* BankSwizzleMode = 1 */ @@ -2223,15 +2366,98 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, } } - /* TODO - * Calculate Twrrd per section 2.10.5.5.3 of the Family 15h BKDG - */ - twrrd = 0xb; + /* Calculate the Critical Delay Difference for Twrrd */ + cdd_twrrd = 0; + for (receiver = 0; receiver < 8; receiver += 2) { + dimm = (receiver >> 1); - /* TODO - * Calculate TrwtTO per section 2.10.5.5.4 of the Family 15h BKDG - */ - trwtto = 0x16; + if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, dct, receiver)) + continue; + + read_dqs_write_timing_control_registers(current_total_delay_1, dev, dct, dimm, index_reg); + read_dqs_receiver_enable_control_registers(current_total_delay_2, dev, dct, dimm, index_reg); + + for (lane = 0; lane < max_lane; lane++) { + if (current_total_delay_1[lane] > current_total_delay_2[lane]) + difference = current_total_delay_1[lane] - current_total_delay_2[lane]; + else + difference = current_total_delay_2[lane] - current_total_delay_1[lane]; + + if (difference > cdd_twrrd) + cdd_twrrd = difference; + } + } + + /* Convert the difference to MEMCLKs */ + cdd_twrrd = (((cdd_twrrd + (1 << 6) - 1) >> 6) & 0xf); + + /* Fam15h BKDG section 2.10.5.5.3 */ + if (pDCTstat->Status & (1 << SB_LoadReduced)) { + /* LRDIMM */ + + /* TODO + * Implement LRDIMM support + * See Fam15h BKDG Rev. 3.14 section 2.10.5.5 + */ + twrrd = 0xb; + } else { + sword = (((int16_t)cdd_twrrd + 1 - ((int16_t)write_early * 2)) + 1) / 2; + if (sword < 0) + sword = 0; + if (((uint16_t)sword) > write_odt_delay) + dword = sword; + else + dword = write_odt_delay; + dword += 3; + if (latency_difference < dword) { + dword -= latency_difference; + if (dword < 1) + twrrd = 1; + else + twrrd = dword; + } else { + twrrd = 1; + } + } + + /* Calculate the Critical Delay Difference for TrwtTO */ + cdd_trwtto = 0; + for (receiver = 0; receiver < 8; receiver += 2) { + dimm = (receiver >> 1); + + if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, dct, receiver)) + continue; + + read_dqs_receiver_enable_control_registers(current_total_delay_1, dev, dct, dimm, index_reg); + read_dqs_write_timing_control_registers(current_total_delay_2, dev, dct, dimm, index_reg); + + for (lane = 0; lane < max_lane; lane++) { + if (current_total_delay_1[lane] > current_total_delay_2[lane]) + difference = current_total_delay_1[lane] - current_total_delay_2[lane]; + else + difference = current_total_delay_2[lane] - current_total_delay_1[lane]; + + if (difference > cdd_trwtto) + cdd_trwtto = difference; + } + } + + /* Convert the difference to MEMCLKs */ + cdd_trwtto = (((cdd_trwtto + (1 << 6) - 1) >> 6) & 0xf); + + /* Fam15h BKDG section 2.10.5.5.4 */ + if (max_dimms_installable == 1) + min_value = 0; + else + min_value = read_odt_delay + buffer_data_delay; + sword = (((int16_t)cdd_trwtto - 1 + ((int16_t)write_early * 2)) + 1) / 2; + sword += latency_difference + 3; + if (sword < 0) + sword = 0; + if (((uint16_t)sword) > min_value) + trwtto = (uint16_t)sword; + else + trwtto = min_value; dword = Get_NB32_DCT(dev, dct, 0xa4); /* DRAM Controller Temperature Throttle */ dword &= ~(0x1 << 11); /* BwCapEn = 0 */ @@ -2242,6 +2468,7 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, dword = Get_NB32_DCT(dev, dct, 0x110); /* DRAM Controller Select Low */ dword &= ~(0x1 << 2); /* DctSelIntLvEn = interleave_channels */ dword |= (interleave_channels & 0x1) << 2; + dword |= (0x3 << 6); /* DctSelIntLvAddr = 0x3 */ Set_NB32_DCT(dev, dct, 0x110, dword); /* DRAM Controller Select Low */ /* NOTE @@ -2249,22 +2476,6 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, * otherwise semi-random lockups will occur due to misconfigured scrubbing hardware! */ - /* FIXME - * The BKDG-recommended settings cause memory corruption on the ASUS KGPE-D16. - * Investigate and fix... - */ -#if 0 - /* Fam15h BKDG section 2.10.5.5.1 */ - dword = Get_NB32_DCT(dev, dct, 0x218); /* DRAM Timing 5 */ - dword &= ~(0xf << 24); /* TrdrdSdSc = 0x1 */ - dword |= (0x1 << 24); - dword &= ~(0xf << 16); /* TrdrdSdDc = trdrdsddc */ - dword |= ((trdrdsddc & 0xf) << 16); - dword &= ~(0xf); /* TrdrdDd = trdrddd */ - dword |= (trdrddd & 0xf); - Set_NB32_DCT(dev, dct, 0x218, dword); /* DRAM Timing 5 */ -#endif - /* Fam15h BKDG section 2.10.5.5.2 */ dword = Get_NB32_DCT(dev, dct, 0x214); /* DRAM Timing 4 */ dword &= ~(0xf << 16); /* TwrwrSdSc = 0x1 */ @@ -2277,8 +2488,14 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, /* Fam15h BKDG section 2.10.5.5.3 */ dword = Get_NB32_DCT(dev, dct, 0x218); /* DRAM Timing 5 */ + dword &= ~(0xf << 24); /* TrdrdSdSc = 0x1 */ + dword |= (0x1 << 24); + dword &= ~(0xf << 16); /* TrdrdSdDc = trdrdsddc */ + dword |= ((trdrdsddc & 0xf) << 16); dword &= ~(0xf << 8); /* Twrrd = twrrd */ dword |= ((twrrd & 0xf) << 8); + dword &= ~(0xf); /* TrdrdDd = trdrddd */ + dword |= (trdrddd & 0xf); Set_NB32_DCT(dev, dct, 0x218, dword); /* DRAM Timing 5 */ /* Fam15h BKDG section 2.10.5.5.4 */ @@ -2289,12 +2506,6 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, dword |= ((((dword >> 8) & 0x1f) + 1) << 16); Set_NB32_DCT(dev, dct, 0x21c, dword); /* DRAM Timing 6 */ - /* Configure partial power down delay */ - dword = Get_NB32(dev, 0x244); /* DRAM Controller Miscellaneous 3 */ - dword &= ~0xf; /* PrtlChPDDynDly = 0x2 */ - dword |= 0x2; - Set_NB32(dev, 0x244, dword); /* DRAM Controller Miscellaneous 3 */ - /* Enable prefetchers */ dword = Get_NB32(dev, 0x11c); /* Memory Controller Configuration High */ dword &= ~(0x1 << 13); /* PrefIoDis = 0 */ @@ -2383,6 +2594,8 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, mct_TrainDQSPos_D(pMCTstat, pDCTstatA); + TrainMaxRdLatency_En_D(pMCTstat, pDCTstatA); + if (is_fam15h()) exit_training_mode_fam15(pMCTstat, pDCTstatA); else @@ -2961,6 +3174,13 @@ static void ClearDCT_D(struct MCTStatStruc *pMCTstat, } while(reg < reg_end) { + if ((reg & 0xFF) == 0x84) { + if (is_fam15h()) { + val = Get_NB32_DCT(dev, dct, reg); + val &= ~(0x1 << 23); /* Clear PchgPDModeSel */ + val &= ~0x3; /* Clear BurstCtrl */ + } + } if ((reg & 0xFF) == 0x90) { if (pDCTstat->LogicalCPUID & AMD_DR_Dx) { val = Get_NB32_DCT(dev, dct, reg); /* get DRAMConfigLow */ @@ -3079,14 +3299,30 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, /* Convert DRAM CycleTiming values and store into DCT structure */ byte = pDCTstat->DIMMAutoSpeed; - if (byte == 7) - tCK16x = 20; - else if (byte == 6) - tCK16x = 24; - else if (byte == 5) - tCK16x = 30; - else - tCK16x = 40; + if (is_fam15h()) { + if (byte == 0x16) + tCK16x = 17; + else if (byte == 0x12) + tCK16x = 20; + else if (byte == 0xe) + tCK16x = 24; + else if (byte == 0xa) + tCK16x = 30; + else if (byte == 0x6) + tCK16x = 40; + else + tCK16x = 48; + } + else { + if (byte == 7) + tCK16x = 20; + else if (byte == 6) + tCK16x = 24; + else if (byte == 5) + tCK16x = 30; + else + tCK16x = 40; + } /* Notes: 1. All secondary time values given in SPDs are in binary with units of ns. @@ -3119,7 +3355,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, val = Max_TrpT; pDCTstat->Trp = val; - /*Trrd*/ + /* Trrd */ pDCTstat->DIMMTrrd = Trrd; val = Trrd / tCK16x; if (Trrd % tCK16x) { /* round up number of busclocks */ @@ -3237,21 +3473,31 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, dword = Get_NB32_DCT(dev, dct, 0x200); /* DRAM Timing 0 */ dword &= ~(0x3f1f1f1f); - dword |= ((pDCTstat->Tras + 0xf) & 0x3f) << 24; /* Tras */ - dword |= ((pDCTstat->Trp + 0x5) & 0x1f) << 16; /* Trp */ - dword |= ((pDCTstat->Trcd + 0x5) & 0x1f) << 8; /* Trcd */ + dword |= (pDCTstat->Tras & 0x3f) << 24; /* Tras */ + val = pDCTstat->Trp; + val = mct_AdjustSPDTimings(pMCTstat, pDCTstat, val); + dword |= (val & 0x1f) << 16; /* Trp */ + dword |= (pDCTstat->Trcd & 0x1f) << 8; /* Trcd */ dword |= (pDCTstat->CASL & 0x1f); /* Tcl */ Set_NB32_DCT(dev, dct, 0x200, dword); /* DRAM Timing 0 */ dword = Get_NB32_DCT(dev, dct, 0x204); /* DRAM Timing 1 */ dword &= ~(0x0f3f0f3f); - dword |= ((pDCTstat->Trtp + 0x4) & 0xf) << 24; /* Trtp */ - if (pDCTstat->Tfaw != 0) - dword |= ((((pDCTstat->Tfaw - 0x1) * 2) + 0x10) & 0x3f) << 16; /* FourActWindow */ - dword |= ((pDCTstat->Trrd + 0x4) & 0xf) << 8; /* Trrd */ - dword |= ((pDCTstat->Trc + 0xb) & 0x3f); /* Trc */ + dword |= (pDCTstat->Trtp & 0xf) << 24; /* Trtp */ + if (pDCTstat->Tfaw != 0) { + val = pDCTstat->Tfaw; + val = mct_AdjustSPDTimings(pMCTstat, pDCTstat, val); + if ((val > 0x5) && (val < 0x2b)) + dword |= (val & 0x3f) << 16; /* FourActWindow */ + } + dword |= (pDCTstat->Trrd & 0xf) << 8; /* Trrd */ + dword |= (pDCTstat->Trc & 0x3f); /* Trc */ Set_NB32_DCT(dev, dct, 0x204, dword); /* DRAM Timing 1 */ + /* Trfc0-Trfc3 */ + for (i=0; i<4; i++) + if (pDCTstat->Trfc[i] == 0x0) + pDCTstat->Trfc[i] = 0x4; dword = Get_NB32_DCT(dev, dct, 0x208); /* DRAM Timing 2 */ dword &= ~(0x07070707); dword |= (pDCTstat->Trfc[3] & 0x7) << 24; /* Trfc3 */ @@ -3262,14 +3508,14 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, dword = Get_NB32_DCT(dev, dct, 0x20c); /* DRAM Timing 3 */ dword &= ~(0x00000f00); - dword |= ((pDCTstat->Twtr + 0x4) & 0xf) << 8; /* Twtr */ + dword |= (pDCTstat->Twtr & 0xf) << 8; /* Twtr */ dword &= ~(0x0000001f); dword |= (Tcwl & 0x1f); /* Tcwl */ Set_NB32_DCT(dev, dct, 0x20c, dword); /* DRAM Timing 3 */ dword = Get_NB32_DCT(dev, dct, 0x22c); /* DRAM Timing 10 */ dword &= ~(0x0000001f); - dword |= ((pDCTstat->Twr + 0x4) & 0x1f); /* Twr */ + dword |= (pDCTstat->Twr & 0x1f); /* Twr */ Set_NB32_DCT(dev, dct, 0x22c, dword); /* DRAM Timing 10 */ if (pDCTstat->Speed > mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) { @@ -3865,6 +4111,8 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, } } + DramConfigMisc2 = mct_SetDramConfigMisc2(pDCTstat, dct, DramConfigMisc2, DramControl); + printk(BIOS_DEBUG, "AutoConfig_D: DramControl: %08x\n", DramControl); printk(BIOS_DEBUG, "AutoConfig_D: DramTimingLo: %08x\n", DramTimingLo); printk(BIOS_DEBUG, "AutoConfig_D: DramConfigMisc: %08x\n", DramConfigMisc); @@ -3876,7 +4124,6 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, Set_NB32_DCT(dev, dct, 0x78, DramControl); Set_NB32_DCT(dev, dct, 0x88, DramTimingLo); Set_NB32_DCT(dev, dct, 0xa0, DramConfigMisc); - DramConfigMisc2 = mct_SetDramConfigMisc2(pDCTstat, dct, DramConfigMisc2); Set_NB32_DCT(dev, dct, 0xa8, DramConfigMisc2); Set_NB32_DCT(dev, dct, 0x90, DramConfigLo); ProgDramMRSReg_D(pMCTstat, pDCTstat, dct); @@ -5247,6 +5494,16 @@ static void mct_PhyController_Config(struct MCTStatStruc *pMCTstat, u32 dev = pDCTstat->dev_dct; if (pDCTstat->LogicalCPUID & (AMD_DR_DAC2_OR_C3 | AMD_RB_C3 | AMD_FAM15_ALL)) { + if (is_fam15h()) { + /* Set F2x[1, 0]98_x0D0F0F13 DllDisEarlyU and DllDisEarlyL to save power */ + for (index = 0; index < 0x9; index++) { + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0013 | (index << 8)); + dword |= (0x1 << 1); /* DllDisEarlyU = 1 */ + dword |= 0x1; /* DllDisEarlyL = 1 */ + Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0013 | (index << 8), dword); + } + } + if (pDCTstat->Dimmx4Present == 0) { /* Set bit7 RxDqsUDllPowerDown to register F2x[1, 0]98_x0D0F0F13 for * additional power saving when x4 DIMMs are not present. @@ -5291,8 +5548,9 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, mct_ExtMCTConfig_Dx(pDCTstat); } else { /* Family 15h CPUs */ - val = 0x0ce00f00 | 0x1 << 29; /* FlushWrOnStpGnt */ - val |= 0x10 << 2; /* MctWrLimit = 16 */ + val = 0x0ce00f00; /* FlushWrOnStpGnt = 0x0 */ + val |= 0x10 << 2; /* MctWrLimit = 0x10 */ + val |= 0x1; /* DctWrLimit = 0x1 */ Set_NB32(pDCTstat->dev_dct, 0x11c, val); val = Get_NB32(pDCTstat->dev_dct, 0x1b0); @@ -6532,8 +6790,8 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat, dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x84); if (is_fam15h()) { - dword |= DramMRS; dword &= ~0x00800003; + dword |= DramMRS; } else { dword &= ~0x00fc2f8f; dword |= DramMRS; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index eb4c74e..b72b9da 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -984,6 +984,7 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat uint64_t mctGetLogicalCPUID(u32 Node); u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void TrainReceiverEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u8 Pass); +void TrainMaxRdLatency_En_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void mct_TrainDQSPos_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void TrainMaxReadLatency_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 3615616..06597e2 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -20,6 +20,9 @@ static void write_dqs_receiver_enable_control_registers(uint16_t* current_total_ static void read_read_dqs_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); +static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat); + static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u16 like, u8 scale, u8 ChipSel); @@ -214,6 +217,27 @@ void TrainReceiverEn_D(struct MCTStatStruc *pMCTstat, } } +void TrainMaxRdLatency_En_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstatA) +{ + uint8_t node; + struct DCTStatStruc *pDCTstat; + + for (node = 0; node < MAX_NODES_SUPPORTED; node++) { + pDCTstat = pDCTstatA + node; + + if (pDCTstat->DCTSysLimit) { + if (is_fam15h()) { + dqsTrainMaxRdLatency_SW_Fam15(pMCTstat, pDCTstat); + } else { + /* FIXME + * Implement Family 10h MaxRdLatency training + */ + } + } + } +} + static void SetEccDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 ChipSel) { @@ -894,7 +918,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, * Algorithm detailed in the Fam15h BKDG Rev. 3.14 section 2.10.5.8.5 */ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct) + struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t calc_min) { uint8_t dimm; uint8_t lane; @@ -938,7 +962,8 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, p += (9 - dword); /* 2.10.5.8.5 (4) */ - p += 5; + if (!calc_min) + p += 5; /* 2.10.5.8.5 (5) */ dword = Get_NB32_DCT(dev, dct, 0xa8); @@ -965,7 +990,8 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, p += (max_delay >> 5); /* 2.10.5.8.5 (8) */ - p += 5; + if (!calc_min) + p += 5; /* 2.10.5.8.5 (9) */ t += 800; @@ -976,13 +1002,16 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, n = (((((uint64_t)p * 1000000000000ULL)/(((uint64_t)fam15h_freq_tab[mem_clk] * 1000000ULL) * 2)) + ((uint64_t)t)) * ((uint64_t)nb_clk * 1000)) / 1000000000ULL; /* 2.10.5.8.5 (11) */ - n -= 1; + if (!calc_min) + n -= 1; /* 2.10.5.8.5 (12) */ - dword = Get_NB32_DCT_NBPstate(dev, dct, nb_pstate, 0x210); - dword &= ~(0x3ff << 22); - dword |= (((n - 1) & 0x3ff) << 22); - Set_NB32_DCT_NBPstate(dev, dct, nb_pstate, 0x210, dword); + if (!calc_min) { + dword = Get_NB32_DCT_NBPstate(dev, dct, nb_pstate, 0x210); + dword &= ~(0x3ff << 22); + dword |= (((n - 1) & 0x3ff) << 22); + Set_NB32_DCT_NBPstate(dev, dct, nb_pstate, 0x210, dword); + } /* Save result for later use */ pDCTstat->CH_MaxRdLat[dct] = n - 1; @@ -1103,6 +1132,9 @@ static void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, } else if (lane < 8) { Set_NB32_DCT(dev, dct, 0x274, ~0x0); Set_NB32_DCT(dev, dct, 0x278, ~(0xff << (lane * 8))); + } else if (lane == 0xff) { + Set_NB32_DCT(dev, dct, 0x274, ~0xffffffff); + Set_NB32_DCT(dev, dct, 0x278, ~0xffffffff); } else { Set_NB32_DCT(dev, dct, 0x274, ~0x0); Set_NB32_DCT(dev, dct, 0x278, ~0x0); @@ -1110,8 +1142,9 @@ static void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, dword = Get_NB32_DCT(dev, dct, 0x27c); dword &= ~(0xff); /* EccMask = 0 */ - if ((lane != 8) || (pDCTstat->DimmECCPresent == 0)) - dword |= 0xff; /* EccMask = 0xff */ + if (lane != 0xff) + if ((lane != 8) || (pDCTstat->DimmECCPresent == 0)) + dword |= 0xff; /* EccMask = 0xff */ Set_NB32_DCT(dev, dct, 0x27c, dword); dword = Get_NB32_DCT(dev, dct, 0x270); @@ -1180,6 +1213,9 @@ static void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, } else if (lane < 8) { Set_NB32_DCT(dev, dct, 0x274, ~0x0); Set_NB32_DCT(dev, dct, 0x278, ~(0xff << (lane * 8))); + } else if (lane == 0xff) { + Set_NB32_DCT(dev, dct, 0x274, ~0xffffffff); + Set_NB32_DCT(dev, dct, 0x278, ~0xffffffff); } else { Set_NB32_DCT(dev, dct, 0x274, ~0x0); Set_NB32_DCT(dev, dct, 0x278, ~0x0); @@ -1187,8 +1223,9 @@ static void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, dword = Get_NB32_DCT(dev, dct, 0x27c); dword &= ~(0xff); /* EccMask = 0 */ - if ((lane != 8) || (pDCTstat->DimmECCPresent == 0)) - dword |= 0xff; /* EccMask = 0xff */ + if (lane != 0xff) + if ((lane != 8) || (pDCTstat->DimmECCPresent == 0)) + dword |= 0xff; /* EccMask = 0xff */ Set_NB32_DCT(dev, dct, 0x27c, dword); dword = Get_NB32_DCT(dev, dct, 0x270); @@ -1274,7 +1311,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, uint32_t dev = pDCTstat->dev_dct; /* Calculate and program MaxRdLatency */ - Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, dct); + Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, dct, 0); Errors = 0; dual_rank = 0; @@ -1632,7 +1669,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, write_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg); /* Calculate and program MaxRdLatency */ - Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, dct); + Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, dct, 0); /* 2.10.5.8.3 (4 B) */ dqs_results_array[current_phy_phase_delay[lane]] = TrainDQSRdWrPos_D_Fam15(pMCTstat, pDCTstat, dct, Receiver, Receiver + 2, lane, lane + 1); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c index 0922193..cf13b40 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c @@ -15,7 +15,8 @@ */ /* mct_SetDramConfigMisc2_Cx & mct_SetDramConfigMisc2_Dx */ -u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, u8 dct, u32 misc2) +u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, + uint8_t dct, uint32_t misc2, uint32_t DramControl) { u32 val; @@ -24,17 +25,47 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, u8 dct, u32 misc2) if (pDCTstat->LogicalCPUID & AMD_FAM15_ALL) { uint8_t cs_mux_45; uint8_t cs_mux_67; + uint32_t f2x80; - /* BKDG v3.14 Table 200 / Table 201 */ - if (MaxDimmsInstallable < 3) { - cs_mux_45 = 1; - cs_mux_67 = 1; - } else { + misc2 &= ~(0x1 << 28); /* FastSelfRefEntryDis = 0x0 */ + if (MaxDimmsInstallable == 3) { + /* FIXME 3 DIMMS per channel unimplemented */ cs_mux_45 = 0; + } else { + uint32_t f2x60 = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x60); + f2x80 = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x80); + if ((((f2x80 & 0xf) == 0x7) || ((f2x80 & 0xf) == 0x9)) + && ((f2x60 & 0x3) == 0x3)) + cs_mux_45 = 1; + else if ((((f2x80 & 0xa) == 0x7) || ((f2x80 & 0xb) == 0x9)) + && ((f2x60 & 0x3) > 0x1)) + cs_mux_45 = 1; + else + cs_mux_45 = 0; + } + + if (MaxDimmsInstallable == 1) { + cs_mux_67 = 0; + } else if (MaxDimmsInstallable == 2) { + uint32_t f2x64 = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x64); + f2x80 = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x80); + if (((((f2x80 >> 4) & 0xf) == 0x7) || (((f2x80 >> 4) & 0xf) == 0x9)) + && ((f2x64 & 0x3) == 0x3)) + cs_mux_67 = 1; + else if (((((f2x80 >> 4) & 0xa) == 0x7) || (((f2x80 >> 4) & 0xb) == 0x9)) + && ((f2x64 & 0x3) > 0x1)) + cs_mux_67 = 1; + else + cs_mux_67 = 0; + } else { + /* FIXME 3 DIMMS per channel unimplemented */ cs_mux_67 = 0; } - misc2 |= (cs_mux_45 & 0x1) << 26; - misc2 |= (cs_mux_67 & 0x1) << 27; + + misc2 &= ~(0x1 << 27); /* CsMux67 = cs_mux_67 */ + misc2 |= ((cs_mux_67 & 0x1) << 27); + misc2 &= ~(0x1 << 26); /* CsMux45 = cs_mux_45 */ + misc2 |= ((cs_mux_45 & 0x1) << 26); } else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) { if (pDCTstat->Status & (1 << SB_Registered)) { misc2 |= 1 << SubMemclkRegDly; @@ -46,8 +77,8 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, u8 dct, u32 misc2) if (pDCTstat->LogicalCPUID & AMD_DR_Cx) misc2 |= 1 << OdtSwizzle; - val = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x78); + val = DramControl; val &= 7; val = ((~val) & 0xff) + 1; val += 6; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 19b1b8f..d69a1ee 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -1420,7 +1420,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, } /* Calculate and program MaxRdLatency */ - Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, Channel); + Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, Channel, 0); if(_DisableDramECC) { mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); @@ -1483,6 +1483,199 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainRcvrEn: Done\n\n"); } +static void write_max_read_latency_to_registers(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, uint8_t dct, uint16_t latency) +{ + uint32_t dword; + uint8_t nb_pstate; + + for (nb_pstate = 0; nb_pstate < 2; nb_pstate++) { + dword = Get_NB32_DCT_NBPstate(pDCTstat->dev_dct, dct, nb_pstate, 0x210); + dword &= ~(0x3ff << 22); + dword |= ((latency & 0x3ff) << 22); + Set_NB32_DCT_NBPstate(pDCTstat->dev_dct, dct, nb_pstate, 0x210, dword); + } +} + +/* DQS MaxRdLatency Training (Family 15h) + * Algorithm detailed in: + * The Fam15h BKDG Rev. 3.14 section 2.10.5.8.5.1 + * This algorithm runs at the highest supported MEMCLK. + */ +static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat) +{ + u8 Channel; + u8 Addl_Index = 0; + u8 Receiver; + u8 _DisableDramECC = 0, _Wrap32Dis = 0, _SSE2 = 0; + u32 Errors; + + u32 dev; + u32 index_reg; + u32 ch_start, ch_end; + u32 msr; + u32 cr4; + u32 lo, hi; + + uint32_t dword; + uint8_t dimm; + uint8_t lane; + uint8_t mem_clk; + uint32_t nb_clk; + uint8_t nb_pstate; + uint16_t current_total_delay[MAX_BYTE_LANES]; + uint16_t current_rdqs_total_delay[MAX_BYTE_LANES]; + uint8_t current_worst_case_total_delay_dimm; + uint16_t current_worst_case_total_delay_value; + + uint16_t fam15h_freq_tab[] = {0, 0, 0, 0, 333, 0, 400, 0, 0, 0, 533, 0, 0, 0, 667, 0, 0, 0, 800, 0, 0, 0, 933}; + + print_debug_dqs("\nTrainMaxRdLatency: Node", pDCTstat->Node_ID, 0); + + dev = pDCTstat->dev_dct; + index_reg = 0x98; + ch_start = 0; + ch_end = 2; + + cr4 = read_cr4(); + if(cr4 & ( 1 << 9)) { /* save the old value */ + _SSE2 = 1; + } + cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ + write_cr4(cr4); + + msr = HWCR; + _RDMSR(msr, &lo, &hi); + /* FIXME: Why use SSEDIS */ + if(lo & (1 << 17)) { /* save the old value */ + _Wrap32Dis = 1; + } + lo |= (1 << 17); /* HWCR.wrap32dis */ + lo &= ~(1 << 15); /* SSEDIS */ + _WRMSR(msr, lo, hi); /* Setting wrap32dis allows 64-bit memory references in real mode */ + + _DisableDramECC = mct_DisableDimmEccEn_D(pMCTstat, pDCTstat); + + Errors = 0; + dev = pDCTstat->dev_dct; + + for (Channel = 0; Channel < 2; Channel++) { + print_debug_dqs("\tTrainMaxRdLatency51: Node ", pDCTstat->Node_ID, 1); + print_debug_dqs("\tTrainMaxRdLatency51: Channel ", Channel, 1); + pDCTstat->Channel = Channel; + + if (pDCTstat->DIMMValidDCT[Channel] == 0) + continue; + + mem_clk = Get_NB32_DCT(dev, Channel, 0x94) & 0x1f; + + Receiver = mct_InitReceiver_D(pDCTstat, Channel); + + /* Find DIMM with worst case receiver enable delays */ + current_worst_case_total_delay_dimm = 0; + current_worst_case_total_delay_value = 0; + + /* There are four receiver pairs, loosely associated with chipselects. + * This is essentially looping over each DIMM. + */ + for (; Receiver < 8; Receiver += 2) { + Addl_Index = (Receiver >> 1) * 3 + 0x10; + dimm = (Receiver >> 1); + + print_debug_dqs("\t\tTrainMaxRdLatency52: index ", Addl_Index, 2); + + if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver)) { + continue; + } + + /* Retrieve the total delay values from pass 1 of DQS receiver enable training */ + read_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); + read_read_dqs_timing_control_registers(current_rdqs_total_delay, dev, Channel, dimm, index_reg); + + for (lane = 0; lane < 8; lane++) { + current_total_delay[lane] += current_rdqs_total_delay[lane]; + if (current_total_delay[lane] > current_worst_case_total_delay_value) { + current_worst_case_total_delay_dimm = dimm; + current_worst_case_total_delay_value = current_total_delay[lane]; + } + } + +#if DQS_TRAIN_DEBUG > 0 + for (lane = 0; lane < 8; lane++) + print_debug_dqs_pair("\t\tTrainMaxRdLatency56: Lane ", lane, " current_total_delay ", current_total_delay[lane], 2); +#endif + } + + /* 2.10.5.8.5.1.1 */ + Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, Channel, 1); + + /* 2.10.5.8.5.1.[2,3] + * Write the DRAM training pattern to the test address + */ + write_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, Channel, current_worst_case_total_delay_dimm << 1, 0xff); + + /* 2.10.5.8.5.1.4 + * Incrementally test each MaxRdLatency candidate + */ + for (; pDCTstat->CH_MaxRdLat[Channel] < 0x3ff; pDCTstat->CH_MaxRdLat[Channel]++) { + write_max_read_latency_to_registers(pMCTstat, pDCTstat, Channel, pDCTstat->CH_MaxRdLat[Channel]); + read_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, Channel, current_worst_case_total_delay_dimm << 1, 0xff); + dword = Get_NB32_DCT(dev, Channel, 0x268) & 0x3ffff; + if (!dword) + break; + Set_NB32_index_wait_DCT(dev, Channel, index_reg, 0x00000050, 0x13131313); + } + + /* 2.10.5.8.5.1.5 */ + nb_pstate = 0; + mem_clk = Get_NB32_DCT(dev, Channel, 0x94) & 0x1f; + if (fam15h_freq_tab[mem_clk] == 0) { + return; + } + dword = Get_NB32(pDCTstat->dev_nbctl, (0x160 + (nb_pstate * 4))); /* Retrieve NbDid, NbFid */ + nb_clk = (200 * (((dword >> 1) & 0x1f) + 0x4)) / (((dword >> 7) & 0x1)?2:1); + + pDCTstat->CH_MaxRdLat[Channel]++; + pDCTstat->CH_MaxRdLat[Channel] += ((((uint64_t)15 * 100000000000ULL) / ((uint64_t)fam15h_freq_tab[mem_clk] * 1000000ULL)) + * ((uint64_t)nb_clk * 1000)) / 1000000000ULL; + + write_max_read_latency_to_registers(pMCTstat, pDCTstat, Channel, pDCTstat->CH_MaxRdLat[Channel]); + } + + if(_DisableDramECC) { + mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); + } + + if(!_Wrap32Dis) { + msr = HWCR; + _RDMSR(msr, &lo, &hi); + lo &= ~(1<<17); /* restore HWCR.wrap32dis */ + _WRMSR(msr, lo, hi); + } + if(!_SSE2){ + cr4 = read_cr4(); + cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ + write_cr4(cr4); + } + +#if DQS_TRAIN_DEBUG > 0 + { + u8 ChannelDTD; + printk(BIOS_DEBUG, "TrainMaxRdLatency: CH_MaxRdLat:\n"); + for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { + printk(BIOS_DEBUG, "Channel:%x: %x\n", + ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD]); + } + } +#endif + + printk(BIOS_DEBUG, "TrainMaxRdLatency: Status %x\n", pDCTstat->Status); + printk(BIOS_DEBUG, "TrainMaxRdLatency: ErrStatus %x\n", pDCTstat->ErrStatus); + printk(BIOS_DEBUG, "TrainMaxRdLatency: ErrCode %x\n", pDCTstat->ErrCode); + printk(BIOS_DEBUG, "TrainMaxRdLatency: Done\n\n"); +} + u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct) { if (pDCTstat->DIMMValidDCT[dct] == 0 ) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c index 4bfcc40..b354d92 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c @@ -168,6 +168,8 @@ static void EnterSelfRefresh(struct MCTStatStruc *pMCTstat, static void ChangeMemClk(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { + printk(BIOS_DEBUG, "%s: Start\n", __func__); + uint8_t DCT0Present; uint8_t DCT1Present; uint32_t dword; @@ -309,6 +311,8 @@ static void ChangeMemClk(struct MCTStatStruc *pMCTstat, mct_Wait(15000); /* Wait for 750us */ } } + + printk(BIOS_DEBUG, "%s: Done\n", __func__); } /*

1 0

Patch set updated for coreboot: amd/family_10h-family_15h: Fix poor performance on Family 15h CPUs
by Timothy Pearson 18 Nov '15

18 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12028 -gerrit commit d63f54d17e800767cadaaa323e9b71640b107875 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Aug 7 19:04:49 2015 -0500 amd/family_10h-family_15h: Fix poor performance on Family 15h CPUs Change-Id: Ieb1f1fb5653651c98764de79636669802578d5f9 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/defaults.h | 13 ++++++-- src/cpu/amd/family_10h-family_15h/init_cpus.c | 45 +++++++++++++++++++++++++-- 2 files changed, 52 insertions(+), 6 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index 3e9ec09..901b8ce 100644 --- a/src/cpu/amd/family_10h-family_15h/defaults.h +++ b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -518,15 +518,15 @@ static const struct { { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00800756, 0x00F3FFFF }, - { 3, 0x140, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00a11755, 0x00f3ffff }, - { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x00C37756, 0x00F3FFFF }, { 3, 0x144, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x00000036, 0x000000FF }, + { 3, 0x140, AMD_FAM15_ALL, AMD_PTYPE_ALL, + 0x00a11755, 0x00f3ffff }, + /* Errata 281 Workaround */ { 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1), AMD_PTYPE_SVR, 0x00000001, 0x0000000F }, @@ -538,6 +538,13 @@ static const struct { { 3, 0x148, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x8000052A, 0xD5FFFFFF }, + /* Core Interface Buffer Count */ + { 3, 0x1a0, AMD_FAM15_ALL, AMD_PTYPE_ALL, + 0x00034004, 0x00037007 }, /* CpuToNbFreeBufCnt = 0x3, + L3ToSriReqCBC = 0x4, + L3FreeListCBC = default, + CpuCmdBufCnt = 0x4 */ + /* ACPI Power State Control Reg1 */ { 3, 0x80, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0xE6002200, 0xFFFFFFFF }, diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 8bc0b6f..0df77b0 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -843,8 +843,9 @@ static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset) */ static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff) { - u32 val; - u32 linktype = 0; + uint32_t val; + uint32_t val2; + uint32_t linktype = 0; /* Check connect, init and coherency */ val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x18); @@ -859,8 +860,13 @@ static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff) if (linktype) { /* Check gen3 */ val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x08); + val = (val >> 8) & 0xf; + if (is_gt_rev_d()) { + val2 = pci_read_config32(NODE_PCI(node, 0), regoff + 0x1c); + val |= (val2 & 0x1) << 4; + } - if (((val >> 8) & 0x0F) > 6) + if (val > 6) linktype |= HTPHY_LINKTYPE_HT3; else linktype |= HTPHY_LINKTYPE_HT1; @@ -1147,6 +1153,39 @@ static void cpuSetAMDPCI(u8 node) pci_write_config32(NODE_PCI(node, 3), 0xd4, dword); } + if (revision & AMD_FAM15_ALL) { + uint32_t f5x80; + uint8_t cu_enabled; + uint8_t compute_unit_count = 0; + uint8_t compute_unit_buffer_count; + + /* Determine the number of active compute units on this node */ + f5x80 = pci_read_config32(NODE_PCI(node, 5), 0x80); + cu_enabled = f5x80 & 0xf; + if (cu_enabled == 0x1) + compute_unit_count = 1; + if (cu_enabled == 0x3) + compute_unit_count = 2; + if (cu_enabled == 0x7) + compute_unit_count = 3; + if (cu_enabled == 0xf) + compute_unit_count = 4; + + if (compute_unit_count == 1) + compute_unit_buffer_count = 0x1c; + else if (compute_unit_count == 2) + compute_unit_buffer_count = 0x18; + else if (compute_unit_count == 3) + compute_unit_buffer_count = 0x14; + else + compute_unit_buffer_count = 0x10; + + dword = pci_read_config32(NODE_PCI(node, 3), 0x1a0); + dword &= ~(0x1f << 4); /* L3FreeListCBC = compute_unit_buffer_count */ + dword |= (compute_unit_buffer_count << 4); + pci_write_config32(NODE_PCI(node, 3), 0x1a0, dword); + } + printk(BIOS_DEBUG, " done\n"); }

1 0

Patch set updated for coreboot: northbridge/amd/amdht: Add support for HT3 2.8GHz and up link frequencies
by Timothy Pearson 18 Nov '15

18 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12027 -gerrit commit 48fcb0c2718067cdf422dcb2096cab0c2e6c40b1 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 2 21:36:24 2015 -0500 northbridge/amd/amdht: Add support for HT3 2.8GHz and up link frequencies Change-Id: Ifa1592d26ba7deb034046fd3f2a15149117d9a76 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/defaults.h | 8 ++- src/mainboard/asus/kgpe-d16/cmos.layout | 30 ++++----- src/northbridge/amd/amdht/h3ffeat.h | 6 +- src/northbridge/amd/amdht/h3finit.c | 93 +++++++++++++++++----------- src/northbridge/amd/amdht/h3finit.h | 18 ++++-- src/northbridge/amd/amdht/h3ncmn.c | 82 +++++++++++++++++------- src/northbridge/amd/amdht/h3ncmn.h | 3 +- 7 files changed, 155 insertions(+), 85 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index a3c7b1f..3e9ec09 100644 --- a/src/cpu/amd/family_10h-family_15h/defaults.h +++ b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -273,7 +273,13 @@ static const struct { /* Link Global Retry Control Register */ { 0, 0x150, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 0x00073900, 0x00073F00 }, + 0x00073900, 0x00073f70 }, /* TotalRetryAttempts = 0x7, + HtRetryCrcDatInsDynEn = 0x1, + HtRetryCrcCmdPackDynEn = 0x1, + HtRetryCrcDatIns = 0x4, + HtRetryCrcCmdPack = 0x1, + ForceErrType = 0x0, + MultRetryErr = 0x0 */ /* Errata 351 * System software should program the Link Extended Control Registers[LS2En] diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 21765e3..e17fec6 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -120,21 +120,21 @@ enumerations 10 21 42ms 10 22 84ms 11 0 Auto -11 1 2.6GHz -11 2 2.4GHz -11 3 2.2GHz -11 4 2.0GHz -11 5 1.8GHz -11 6 1.6GHz -11 7 1.4GHz -11 8 1.2GHz -11 9 1.0GHz -11 10 800MHz -11 11 600MHz -11 12 500MHz -11 13 400MHz -11 14 300MHz -11 15 200MHz +11 1 3.2GHz +11 2 3.0GHz +11 3 2.8GHz +11 4 2.6GHz +11 5 2.4GHz +11 6 2.2GHz +11 7 2.0GHz +11 8 1.8GHz +11 9 1.6GHz +11 10 1.4GHz +11 11 1.2GHz +11 12 1.0GHz +11 13 800MHz +11 14 600MHz +11 15 500MHz 12 0 1.5V 12 1 1.35V 12 2 1.25V diff --git a/src/northbridge/amd/amdht/h3ffeat.h b/src/northbridge/amd/amdht/h3ffeat.h index 52c4def..628b86e 100644 --- a/src/northbridge/amd/amdht/h3ffeat.h +++ b/src/northbridge/amd/amdht/h3ffeat.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -58,6 +59,7 @@ #define HTHOST_LINK_CAPABILITY_REG 0x00 #define HTHOST_LINK_CONTROL_REG 0x04 #define HTHOST_FREQ_REV_REG 0x08 +#define HTHOST_FREQ_REV_REG_2 0x1c #define HT_HOST_REV_REV3 0x60 #define HTHOST_FEATURE_CAP_REG 0x0C #define HTHOST_BUFFER_COUNT_REG 0x10 @@ -123,10 +125,10 @@ typedef struct /* This section is for keeping track of capabilities and possible configurations */ BOOL RegangCap; - u16 PrvFrequencyCap; + uint32_t PrvFrequencyCap; u8 PrvWidthInCap; u8 PrvWidthOutCap; - u16 CompositeFrequencyCap; + uint32_t CompositeFrequencyCap; } sPortDescriptor; diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index bcdcfa2..e4ce768 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -48,28 +48,32 @@ #define APIC_Base_BSP 8 #define APIC_Base 0x1b -#define NVRAM_LIMIT_HT_SPEED_200 0xf -#define NVRAM_LIMIT_HT_SPEED_300 0xe -#define NVRAM_LIMIT_HT_SPEED_400 0xd -#define NVRAM_LIMIT_HT_SPEED_500 0xc -#define NVRAM_LIMIT_HT_SPEED_600 0xb -#define NVRAM_LIMIT_HT_SPEED_800 0xa -#define NVRAM_LIMIT_HT_SPEED_1000 0x9 -#define NVRAM_LIMIT_HT_SPEED_1200 0x8 -#define NVRAM_LIMIT_HT_SPEED_1400 0x7 -#define NVRAM_LIMIT_HT_SPEED_1600 0x6 -#define NVRAM_LIMIT_HT_SPEED_1800 0x5 -#define NVRAM_LIMIT_HT_SPEED_2000 0x4 -#define NVRAM_LIMIT_HT_SPEED_2200 0x3 -#define NVRAM_LIMIT_HT_SPEED_2400 0x2 -#define NVRAM_LIMIT_HT_SPEED_2600 0x1 +#define NVRAM_LIMIT_HT_SPEED_200 0x12 +#define NVRAM_LIMIT_HT_SPEED_300 0x11 +#define NVRAM_LIMIT_HT_SPEED_400 0x10 +#define NVRAM_LIMIT_HT_SPEED_500 0xf +#define NVRAM_LIMIT_HT_SPEED_600 0xe +#define NVRAM_LIMIT_HT_SPEED_800 0xd +#define NVRAM_LIMIT_HT_SPEED_1000 0xc +#define NVRAM_LIMIT_HT_SPEED_1200 0xb +#define NVRAM_LIMIT_HT_SPEED_1400 0xa +#define NVRAM_LIMIT_HT_SPEED_1600 0x9 +#define NVRAM_LIMIT_HT_SPEED_1800 0x8 +#define NVRAM_LIMIT_HT_SPEED_2000 0x7 +#define NVRAM_LIMIT_HT_SPEED_2200 0x6 +#define NVRAM_LIMIT_HT_SPEED_2400 0x5 +#define NVRAM_LIMIT_HT_SPEED_2600 0x4 +#define NVRAM_LIMIT_HT_SPEED_2800 0x3 +#define NVRAM_LIMIT_HT_SPEED_3000 0x2 +#define NVRAM_LIMIT_HT_SPEED_3200 0x1 #define NVRAM_LIMIT_HT_SPEED_AUTO 0x0 -static const uint16_t ht_speed_limit[16] = - {0xFFFF, 0x7FFF, 0x3FFF, 0x1FFF, - 0x0FFF, 0x07FF, 0x03FF, 0x01FF, - 0x00FF, 0x007F, 0x003F, 0x001F, - 0x000F, 0x0007, 0x0003, 0x0001}; +static const uint32_t ht_speed_limit[20] = + {0xFFFFF, 0xFFFFF, 0x7FFFF, 0x3FFFF, + 0x0FFFF, 0x07FFF, 0x03FFF, 0x01FFF, + 0x00FFF, 0x007FF, 0x003FF, 0x001FF, + 0x000FF, 0x0007F, 0x0003F, 0x0001F, + 0x0000F, 0x00007, 0x00003, 0x00001}; static const struct ht_speed_limit_map_t { uint16_t mhz; @@ -91,9 +95,12 @@ static const struct ht_speed_limit_map_t { {2200, NVRAM_LIMIT_HT_SPEED_2200}, {2400, NVRAM_LIMIT_HT_SPEED_2400}, {2600, NVRAM_LIMIT_HT_SPEED_2600}, + {2800, NVRAM_LIMIT_HT_SPEED_2800}, + {3000, NVRAM_LIMIT_HT_SPEED_3000}, + {3200, NVRAM_LIMIT_HT_SPEED_3200}, }; -static const uint16_t ht_speed_mhz_to_hw(uint16_t mhz) +static const uint32_t ht_speed_mhz_to_hw(uint16_t mhz) { size_t i; for (i = 0; i < ARRAY_SIZE(ht_speed_limit_map); i++) @@ -452,7 +459,7 @@ static void htDiscoveryFloodFill(sMainData *pDat) /* Set currentNode's NodeID field to currentNode */ pDat->nb->writeNodeID(currentNode, currentNode, pDat->nb); - /* Enable routing tables on currentNode*/ + /* Enable routing tables on currentNode */ pDat->nb->enableRoutingTables(currentNode, pDat->nb); for (currentLinkID = 0; currentLinkID < pDat->nb->maxLinks; currentLinkID++) @@ -1427,19 +1434,30 @@ static void regangLinks(sMainData *pDat) static void selectOptimalWidthAndFrequency(sMainData *pDat) { u8 i, j; - u32 temp; - u16 cbPCBFreqLimit; - u16 cbPCBFreqLimit_NVRAM; + uint32_t temp; + uint32_t cbPCBFreqLimit; + uint32_t cbPCBFreqLimit_NVRAM; u8 cbPCBABDownstreamWidth; u8 cbPCBBAUpstreamWidth; - cbPCBFreqLimit_NVRAM = 0xFFFF; + cbPCBFreqLimit_NVRAM = 0xfffff; if (get_option(&temp, "hypertransport_speed_limit") == CB_SUCCESS) cbPCBFreqLimit_NVRAM = ht_speed_limit[temp & 0xf]; + if (!is_fam15h()) { + /* FIXME + * By default limit frequency to 2.6 GHz as there are residual + * problems with HT v3.1 implementation on at least some Socket G34 + * mainboards / Fam10h CPUs. + * Debug the issues and reenable this... + */ + if (cbPCBFreqLimit_NVRAM > 0xffff) + cbPCBFreqLimit_NVRAM = 0xffff; + } + for (i = 0; i < pDat->TotalLinks*2; i += 2) { - cbPCBFreqLimit = 0xFFFF; // Maximum allowed by autoconfiguration + cbPCBFreqLimit = 0xfffff; // Maximum allowed by autoconfiguration if (pDat->HtBlock->ht_link_configuration) cbPCBFreqLimit = ht_speed_mhz_to_hw(pDat->HtBlock->ht_link_configuration->ht_speed_limit); cbPCBFreqLimit = min(cbPCBFreqLimit, cbPCBFreqLimit_NVRAM); @@ -1484,17 +1502,18 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat) } } - temp = pDat->PortList[i].PrvFrequencyCap; temp &= pDat->PortList[i+1].PrvFrequencyCap; temp &= cbPCBFreqLimit; - pDat->PortList[i].CompositeFrequencyCap = (u16)temp; - pDat->PortList[i+1].CompositeFrequencyCap = (u16)temp; + pDat->PortList[i].CompositeFrequencyCap = temp; + pDat->PortList[i+1].CompositeFrequencyCap = temp; ASSERT (temp != 0); - for (j = 15; ; j--) + for (j = 19; ; j--) { - if (temp & ((u32)1 << j)) + if ((j == 16) || (j == 15)) + continue; + if (temp & ((uint32_t)1 << j)) break; } @@ -1638,12 +1657,14 @@ static void hammerSublinkFixup(sMainData *pDat) /* Remove hiFreq from the list of valid frequencies */ temp = temp & ~((uint32)1 << hiFreq); ASSERT (temp != 0); - pDat->PortList[hiIndex].CompositeFrequencyCap = (uint16)temp; - pDat->PortList[hiIndex+1].CompositeFrequencyCap = (uint16)temp; + pDat->PortList[hiIndex].CompositeFrequencyCap = temp; + pDat->PortList[hiIndex+1].CompositeFrequencyCap = temp; - for (k = 15; ; k--) + for (k = 19; ; k--) { - if (temp & ((u32)1 << k)) + if ((j == 16) || (j == 15)) + continue; + if (temp & ((uint32_t)1 << k)) break; } diff --git a/src/northbridge/amd/amdht/h3finit.h b/src/northbridge/amd/amdht/h3finit.h index f6ab010..1bd8616 100644 --- a/src/northbridge/amd/amdht/h3finit.h +++ b/src/northbridge/amd/amdht/h3finit.h @@ -49,6 +49,9 @@ #define HT_FREQUENCY_2200M 12 #define HT_FREQUENCY_2400M 13 #define HT_FREQUENCY_2600M 14 +#define HT_FREQUENCY_2800M 17 +#define HT_FREQUENCY_3000M 18 +#define HT_FREQUENCY_3200M 19 /* Frequency Limit equates for call backs which take a frequency supported mask. */ #define HT_FREQUENCY_LIMIT_200M 1 @@ -65,6 +68,9 @@ #define HT_FREQUENCY_LIMIT_2200M 0x1FFF #define HT_FREQUENCY_LIMIT_2400M 0x3FFF #define HT_FREQUENCY_LIMIT_2600M 0x7FFF +#define HT_FREQUENCY_LIMIT_2800M 0x3FFFF +#define HT_FREQUENCY_LIMIT_3000M 0x7FFFF +#define HT_FREQUENCY_LIMIT_3200M 0xFFFFF /* * Event Notify definitions @@ -220,7 +226,7 @@ typedef struct { * @param[in] u8 Link = The Device's link number (0 or 1) * @param[in,out] u8* LinkWidthIn = modify to change the Link Witdh In * @param[in,out] u8* LinkWidthOut = modify to change the Link Witdh Out - * @param[in,out] u16* FreqCap = modify to change the link's frequency capability + * @param[in,out] u32* FreqCap = modify to change the link's frequency capability * * --------------------------------------------------------------------------------------- */ @@ -235,7 +241,7 @@ typedef struct { u8 Link, u8 *LinkWidthIn, u8 *LinkWidthOut, - u16 *FreqCap + u32 *FreqCap ); /**---------------------------------------------------------------------------------------- @@ -258,7 +264,7 @@ typedef struct { * @param[in] u8 linkB = The link on that node * @param[in,out] u8* ABLinkWidthLimit = modify to change the Link Witdh In * @param[in,out] u8* BALinkWidthLimit = modify to change the Link Witdh Out - * @param[in,out] u16* PCBFreqCap = modify to change the link's frequency capability + * @param[in,out] u32* PCBFreqCap = modify to change the link's frequency capability * * --------------------------------------------------------------------------------------- */ @@ -269,7 +275,7 @@ typedef struct { u8 LinkB, u8 *ABLinkWidthLimit, u8 *BALinkWidthLimit, - u16 *PCBFreqCap + u32 *PCBFreqCap ); /**---------------------------------------------------------------------------------------- @@ -291,7 +297,7 @@ typedef struct { * @param[in] u8 Depth = The depth in the I/O chain from the Host * @param[in,out] u8* DownstreamLinkWidthLimit = modify to change the Link Witdh In * @param[in,out] u8* UpstreamLinkWidthLimit = modify to change the Link Witdh Out - * @param[in,out] u16* PCBFreqCap = modify to change the link's frequency capability + * @param[in,out] u32* PCBFreqCap = modify to change the link's frequency capability * * --------------------------------------------------------------------------------------- */ @@ -301,7 +307,7 @@ typedef struct { u8 Depth, u8 *DownstreamLinkWidthLimit, u8 *UpstreamLinkWidthLimit, - u16 *PCBFreqCap + u32 *PCBFreqCap ); /**---------------------------------------------------------------------------------------- diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index 8ee929d..29524af 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -1310,7 +1310,7 @@ static u8 convertWidthToBits(u8 value, cNorthBridge *nb) * @return Frequency mask * ******************************************************************************/ -static u16 ht1NorthBridgeFreqMask(u8 node, cNorthBridge *nb) +static uint32_t ht1NorthBridgeFreqMask(u8 node, cNorthBridge *nb) { /* only up to HT1 speeds */ return (HT_FREQUENCY_LIMIT_HT1_ONLY); @@ -1331,26 +1331,43 @@ static u16 ht1NorthBridgeFreqMask(u8 node, cNorthBridge *nb) * @return = Frequency mask * ******************************************************************************/ -static u16 fam10NorthBridgeFreqMask(u8 node, cNorthBridge *nb) +static uint32_t fam10NorthBridgeFreqMask(u8 node, cNorthBridge *nb) { u8 nbCOF; - u16 supported; + uint32_t supported; nbCOF = getMinNbCOF(); /* * nbCOF is minimum northbridge speed in hundreds of MHz. * HT can not go faster than the minimum speed of the northbridge. */ - if ((nbCOF >= 6) && (nbCOF <= 26)) + if ((nbCOF >= 6) && (nbCOF < 10)) { + /* Generation 1 HT link frequency */ /* Convert frequency to bit and all less significant bits, * by setting next power of 2 and subtracting 1. */ - supported = ((u16)1 << ((nbCOF >> 1) + 2)) - 1; + supported = ((uint32_t)1 << ((nbCOF >> 1) + 2)) - 1; } - else if (nbCOF > 26) + else if ((nbCOF >= 10) && (nbCOF <= 32)) { - supported = HT_FREQUENCY_LIMIT_2600M; + /* Generation 3 HT link frequency + * Assume error retry is enabled on all Gen 3 links + */ + if (is_gt_rev_d()) { + nbCOF *= 2; + if (nbCOF > 32) + nbCOF = 32; + } + + /* Convert frequency to bit and all less significant bits, + * by setting next power of 2 and subtracting 1. + */ + supported = ((uint32_t)1 << ((nbCOF >> 1) + 2)) - 1; + } + else if (nbCOF > 32) + { + supported = HT_FREQUENCY_LIMIT_3200M; } /* unlikely cases, but include as a defensive measure, also avoid trick above */ else if (nbCOF == 4) @@ -1405,8 +1422,13 @@ static void gatherLinkData(sMainData *pDat, cNorthBridge *nb) pDat->PortList[i].PrvWidthInCap = convertBitsToWidth((u8)temp, pDat->nb); AmdPCIReadBits(linkBase + HTHOST_FREQ_REV_REG, 31, 16, &temp); - pDat->PortList[i].PrvFrequencyCap = (u16)temp & 0x7FFF - & nb->northBridgeFreqMask(pDat->PortList[i].NodeID, pDat->nb); /* Mask off bit 15, reserved value */ + pDat->PortList[i].PrvFrequencyCap = temp & 0x7FFF /* Mask off bit 15, reserved value */ + & nb->northBridgeFreqMask(pDat->PortList[i].NodeID, pDat->nb); + if (is_gt_rev_d()) { + AmdPCIReadBits(linkBase + HTHOST_FREQ_REV_REG_2, 15, 1, &temp); + temp &= 0x7; /* Mask off reserved values */ + pDat->PortList[i].PrvFrequencyCap |= (temp << 17); + } } else { @@ -1463,7 +1485,7 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) { u8 i; SBDFO linkBase; - u32 temp, widthin, widthout, bits; + u32 temp, temp2, frequency_index, widthin, widthout, bits; for (i = 0; i < pDat->TotalLinks*2; i++) { @@ -1524,10 +1546,19 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) temp = pDat->PortList[i].SelFrequency; if (pDat->PortList[i].Type == PORTLIST_TYPE_CPU) { - ASSERT((temp >= HT_FREQUENCY_600M && temp <= HT_FREQUENCY_2600M) + ASSERT((temp >= HT_FREQUENCY_600M && temp <= HT_FREQUENCY_3200M) || (temp == HT_FREQUENCY_200M) || (temp == HT_FREQUENCY_400M)); + frequency_index = temp; + if (temp > 0xf) { + temp2 = (temp >> 4) & 0x1; + temp &= 0xf; + } else { + temp2 = 0x0; + } + if (is_gt_rev_d()) + AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG_2, 0, 0, &temp2); AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG, 11, 8, &temp); - if (temp > HT_FREQUENCY_1000M) /* Gen1 = 200MHz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz */ + if (frequency_index > HT_FREQUENCY_1000M) /* Gen1 = 200MHz -> 1000MHz, Gen3 = 1200MHz -> 3200MHz */ { /* Enable for Gen3 frequencies */ temp = 1; @@ -1537,27 +1568,27 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) /* Disable for Gen1 frequencies */ temp = 0; } - /* HT3 retry mode enable / disable */ - AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(pDat->PortList[i].NodeID), - makePCIBusFromNode(pDat->PortList[i].NodeID), - makePCIDeviceFromNode(pDat->PortList[i].NodeID), - CPU_HTNB_FUNC_00, - REG_HT_LINK_RETRY0_0X130 + 4*pDat->PortList[i].Link), - 0, 0, &temp); - /* and Scrambling enable / disable */ - AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(pDat->PortList[i].NodeID), + /* HT3 retry mode enable / disable */ + AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(pDat->PortList[i].NodeID), makePCIBusFromNode(pDat->PortList[i].NodeID), makePCIDeviceFromNode(pDat->PortList[i].NodeID), CPU_HTNB_FUNC_00, - REG_HT_LINK_EXT_CONTROL0_0X170 + 4*pDat->PortList[i].Link), - 3, 3, &temp); + REG_HT_LINK_RETRY0_0X130 + 4*pDat->PortList[i].Link), + 0, 0, &temp); + /* and Scrambling enable / disable */ + AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(pDat->PortList[i].NodeID), + makePCIBusFromNode(pDat->PortList[i].NodeID), + makePCIDeviceFromNode(pDat->PortList[i].NodeID), + CPU_HTNB_FUNC_00, + REG_HT_LINK_EXT_CONTROL0_0X170 + 4*pDat->PortList[i].Link), + 3, 3, &temp); } else { SBDFO currentPtr; BOOL isFound; - ASSERT(temp <= HT_FREQUENCY_2600M); + ASSERT(temp <= HT_FREQUENCY_3200M); /* Write the frequency setting */ AmdPCIWriteBits(linkBase + HTSLAVE_FREQ_REV_0_REG, 11, 8, &temp); @@ -1718,6 +1749,9 @@ static void fam0fWriteHTLinkCmdBufferAlloc(u8 node, u8 link, u8 req, u8 preq, u8 /* Probe Command Buffers */ temp = prb; AmdPCIWriteBits(currentPtr, 15, 12, &temp); + /* LockBc */ + temp = 1; + AmdPCIWriteBits(currentPtr, 31, 31, &temp); } #endif /* HT_BUILD_NC_ONLY */ diff --git a/src/northbridge/amd/amdht/h3ncmn.h b/src/northbridge/amd/amdht/h3ncmn.h index 328d909..3c8a346 100644 --- a/src/northbridge/amd/amdht/h3ncmn.h +++ b/src/northbridge/amd/amdht/h3ncmn.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -103,7 +104,7 @@ struct cNorthBridge /* Public Interfaces for northbridge clients, Optimization */ u8 (*convertBitsToWidth)(u8 value, cNorthBridge *nb); u8 (*convertWidthToBits)(u8 value, cNorthBridge *nb); - u16 (*northBridgeFreqMask)(u8 node, cNorthBridge *nb); + uint32_t (*northBridgeFreqMask)(u8 node, cNorthBridge *nb); void (*gatherLinkData)(sMainData *pDat, cNorthBridge *nb); void (*setLinkData)(sMainData *pDat, cNorthBridge *nb);

1 0

Patch set updated for coreboot: cpu/amd/family_10h-family_15h: Fix incorrect revision detection
by Timothy Pearson 18 Nov '15

18 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12026 -gerrit commit b11f6b902764a761f9aa67067194e374bee47527 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 2 21:31:48 2015 -0500 cpu/amd/family_10h-family_15h: Fix incorrect revision detection Change-Id: I7a881a94d62ed455415f9dfc887fd698ac919429 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/fidvid.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 8a006cb..66bb3a2 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -371,7 +371,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) pci_write_config32(dev, 0xd8, dtemp); } -static u32 nb_clk_did(int node, u32 cpuRev,u8 procPkg) { +static u32 nb_clk_did(int node, uint64_t cpuRev, uint8_t procPkg) { u8 link0isGen3 = 0; u8 offset; if (AMD_CpuFindCapability(node, 0, &offset)) { @@ -442,7 +442,7 @@ static u32 power_up_down(int node, u8 procPkg) { return dword; } -static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { +static void config_clk_power_ctrl_reg0(int node, uint64_t cpuRev, uint8_t procPkg) { device_t dev = NODE_PCI(node, 3); /* Program fields in Clock Power/Control register0 (F3xD4) */ @@ -467,7 +467,7 @@ static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { } -static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { +static void config_power_ctrl_misc_reg(device_t dev, uint64_t cpuRev, uint8_t procPkg) { /* check PVI/SVI */ u32 dword = pci_read_config32(dev, 0xa0); @@ -500,7 +500,7 @@ static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { pci_write_config32(dev, 0xa0, dword); } -static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { +static void config_nb_syn_ptr_adj(device_t dev, uint64_t cpuRev) { /* Note the following settings are additional from the ported * function setFidVidRegs() */ @@ -522,7 +522,7 @@ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { pci_write_config32(dev, 0xdc, dword); } -static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) { +static void config_acpi_pwr_state_ctrl_regs(device_t dev, uint64_t cpuRev, uint8_t procPkg) { if (is_fam15h()) { /* Family 15h BKDG Rev. 3.14 D18F3x80 recommended settings */ pci_write_config32(dev, 0x80, 0xe20be281);

1 0

Patch set updated for coreboot: cpu/amd/fam10h-fam15h: Set northbridge throttle values
by Timothy Pearson 18 Nov '15

18 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12025 -gerrit commit 00cea68ab9d4d2d8eba965c04b74330a36511310 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 2 21:31:17 2015 -0500 cpu/amd/fam10h-fam15h: Set northbridge throttle values The existing code did not set the northbridge throttle values on Family 15h, leading to sporadic and random deadlocks in the crossbar per AMD notes. Properly set the northbridge throttle values on Family 15h. Change-Id: I6304b63708c65fedb9c2d46b8c862b7f0adf1102 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 21 +---------- .../amd/family_10h-family_15h/model_10xxx_init.c | 44 ++++++++++++++++++++++ 2 files changed, 45 insertions(+), 20 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index a6d8dc4..8bc0b6f 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -873,6 +873,7 @@ static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff) else linktype |= HTPHY_LINKTYPE_UNGANGED; } + return linktype; } @@ -967,26 +968,6 @@ void cpuSetAMDMSR(uint8_t node_id) } AMD_Errata298(); - if (revision & AMD_FAM15_ALL) { - uint32_t f5x80; - uint8_t enabled; - uint8_t compute_unit_count = 0; - f5x80 = pci_read_config32(NODE_PCI(node_id, 5), 0x80); - enabled = f5x80 & 0xf; - if (enabled == 0x1) - compute_unit_count = 1; - if (enabled == 0x3) - compute_unit_count = 2; - if (enabled == 0x7) - compute_unit_count = 3; - if (enabled == 0xf) - compute_unit_count = 4; - msr = rdmsr(BU_CFG2); - msr.lo &= ~(0x3 << 6); /* ThrottleNbInterface[1:0] */ - msr.lo |= (((compute_unit_count - 1) & 0x3) << 6); - wrmsr(BU_CFG2, msr); - } - /* Revision C0 and above */ if (revision & AMD_OR_C0) { uint32_t f3x1fc = pci_read_config32(NODE_PCI(node_id, 3), 0x1fc); diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index 4ccf79d..fe9fb9c 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -154,6 +154,50 @@ static void model_10xxx_init(device_t dev) printk(BIOS_DEBUG, "siblings = %02d, ", siblings); #endif + /* Set bus unit configuration */ + if (is_fam15h()) { + uint32_t f5x80; + uint8_t enabled; + uint8_t compute_unit_count = 0; + f5x80 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 5)), 0x80); + enabled = f5x80 & 0xf; + if (enabled == 0x1) + compute_unit_count = 1; + if (enabled == 0x3) + compute_unit_count = 2; + if (enabled == 0x7) + compute_unit_count = 3; + if (enabled == 0xf) + compute_unit_count = 4; + msr = rdmsr(BU_CFG2_MSR); + msr.lo &= ~(0x3 << 6); /* ThrottleNbInterface[1:0] */ + msr.lo |= (((compute_unit_count - 1) & 0x3) << 6); + wrmsr(BU_CFG2_MSR, msr); + } else { + uint32_t f0x60; + uint32_t f0x160; + uint8_t core_count = 0; + uint8_t node_count = 0; + f0x60 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x60); + core_count = (f0x60 >> 16) & 0x1f; + node_count = ((f0x60 >> 4) & 0x7) + 1; + if (is_gt_rev_d()) { + f0x160 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x160); + core_count |= ((f0x160 >> 16) & 0x7) << 5; + } + core_count++; + core_count /= node_count; + msr = rdmsr(BU_CFG2_MSR); + if (is_gt_rev_d()) { + msr.hi &= ~(0x3 << (36 - 32)); /* ThrottleNbInterface[3:2] */ + msr.hi |= ((((core_count - 1) >> 2) & 0x3) << (36 - 32)); + } + msr.lo &= ~(0x3 << 6); /* ThrottleNbInterface[1:0] */ + msr.lo |= (((core_count - 1) & 0x3) << 6); + msr.lo &= ~(0x1 << 24); /* WcPlusDis = 0 */ + wrmsr(BU_CFG2_MSR, msr); + } + /* Disable Cf8ExtCfg */ msr = rdmsr(NB_CFG_MSR); msr.hi &= ~(1 << (46 - 32));

1 0

Patch set updated for coreboot: mainboard/asus/kgpe-d16: Fix I/O link detection
by Timothy Pearson 18 Nov '15

18 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12024 -gerrit commit 226cc542ffb7bdfda0dc3401029efd464794dd58 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 2 21:28:31 2015 -0500 mainboard/asus/kgpe-d16: Fix I/O link detection Change-Id: Ibefc9dc2e1e0267389eb8d716408bae6026ce084 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/romstage.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index be91eaa..6503b90 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -551,7 +551,8 @@ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { /* Force BUID to 0 */ static const u8 swaplist[] = {0, 0, 0xFF, 0, 0xFF}; - if ((node == 0) && (link == 1)) { /* BSP SB link */ + if ((is_fam15h() && (node == 0) && (link == 1)) /* Family 15h BSP SB link */ + || (!is_fam15h() && (node == 0) && (link == 3))) { /* Family 10h BSP SB link */ *List = swaplist; return 1; }

1 0

Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Move K10D configuration into separate file
by Timothy Pearson 18 Nov '15

18 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12023 -gerrit commit f97afbe92fde47117e2fbd1d4a448b2096b75967 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 2 21:23:02 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Move K10D configuration into separate file Change-Id: Id45888f266fac7810a63fef43b8d7a0ee40cbf70 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/raminit_amdmct.c | 1 + src/northbridge/amd/amdmct/amddefs.h | 5 +- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 131 +++++++++++-------------- src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c | 4 +- src/northbridge/amd/amdmct/mct_ddr3/mctprod.c | 65 ++++++++++++ 5 files changed, 130 insertions(+), 76 deletions(-) diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index d8023f8..a40c5a1 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -373,6 +373,7 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8 #include "../amdmct/mct_ddr3/mctdqs_d.c" #include "../amdmct/mct_ddr3/mctsrc.c" #include "../amdmct/mct_ddr3/mctsdi.c" +#include "../amdmct/mct_ddr3/mctprod.c" #include "../amdmct/mct_ddr3/mctproc.c" #include "../amdmct/mct_ddr3/mctprob.c" #include "../amdmct/mct_ddr3/mcthwl.c" diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index d2dfbcc..10a50d9 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -111,7 +112,7 @@ /* * CPU HT PHY REGISTERS, FIELDS, AND MASKS */ -#define HTPHY_OFFSET_MASK 0xE00001FF +#define HTPHY_OFFSET_MASK 0xE000FFFF #define HTPHY_WRITE_CMD 0x40000000 #define HTPHY_IS_COMPLETE_MASK 0x80000000 #define HTPHY_DIRECT_MAP 0x20000000 @@ -160,4 +161,4 @@ #define AMD_PKGTYPE_S1gX 2 #define AMD_PKGTYPE_G34 3 #define AMD_PKGTYPE_ASB2 4 -#define AMD_PKGTYPE_C32 5 \ No newline at end of file +#define AMD_PKGTYPE_C32 5 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index bfe7515..283d897 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -178,6 +178,7 @@ static void SyncSetting(struct DCTStatStruc *pDCTstat); static uint8_t crcCheck(struct DCTStatStruc *pDCTstat, uint8_t dimm); static void mct_ExtMCTConfig_Bx(struct DCTStatStruc *pDCTstat); static void mct_ExtMCTConfig_Cx(struct DCTStatStruc *pDCTstat); +static void mct_ExtMCTConfig_Dx(struct DCTStatStruc *pDCTstat); static void read_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); @@ -2687,13 +2688,11 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { pDCTstat = pDCTstatA + Node; - /* Configure and enable prefetchers */ - if (is_fam15h()) - dword = 0x0ce00f41; /* BKDG recommended */ - else - dword = 0x0fe40fc0; /* BKDG recommended */ - dword |= MCCH_FlushWrOnStpGnt; /* Set for S3 */ - Set_NB32(pDCTstat->dev_dct, 0x11c, dword); + /* Enable prefetchers */ + dword = Get_NB32(pDCTstat->dev_dct, 0x11c); /* Memory Controller Configuration High */ + dword &= ~(0x1 << 13); /* PrefIoDis = 0 */ + dword &= ~(0x1 << 12); /* PrefCpuDis = 0 */ + Set_NB32(pDCTstat->dev_dct, 0x11c, dword); /* Memory Controller Configuration High */ } } @@ -4935,31 +4934,33 @@ static void Set_OtherTiming(struct MCTStatStruc *pMCTstat, Get_TrwtTO(pMCTstat, pDCTstat, dct); Get_TrwtWB(pMCTstat, pDCTstat); - reg = 0x8C; /* Dram Timing Hi */ - val = Get_NB32_DCT(dev, dct, reg); - val &= 0xffff0300; - dword = pDCTstat->TrwtTO; - val |= dword << 4; - dword = pDCTstat->Twrrd & 3; - val |= dword << 10; - dword = pDCTstat->Twrwr & 3; - val |= dword << 12; - dword = pDCTstat->Trdrd & 3; - val |= dword << 14; - dword = pDCTstat->TrwtWB; - val |= dword; - Set_NB32_DCT(dev, dct, reg, val); - - reg = 0x78; - val = Get_NB32_DCT(dev, dct, reg); - val &= 0xFFFFC0FF; - dword = pDCTstat->Twrrd >> 2; - val |= dword << 8; - dword = pDCTstat->Twrwr >> 2; - val |= dword << 10; - dword = pDCTstat->Trdrd >> 2; - val |= dword << 12; - Set_NB32_DCT(dev, dct, reg, val); + if (!is_fam15h()) { + reg = 0x8c; /* Dram Timing Hi */ + val = Get_NB32_DCT(dev, dct, reg); + val &= 0xffff0300; + dword = pDCTstat->TrwtTO; + val |= dword << 4; + dword = pDCTstat->Twrrd & 3; + val |= dword << 10; + dword = pDCTstat->Twrwr & 3; + val |= dword << 12; + dword = (pDCTstat->Trdrd - 0x3) & 3; + val |= dword << 14; + dword = pDCTstat->TrwtWB; + val |= dword; + Set_NB32_DCT(dev, dct, reg, val); + + reg = 0x78; + val = Get_NB32_DCT(dev, dct, reg); + val &= 0xffffc0ff; + dword = pDCTstat->Twrrd >> 2; + val |= dword << 8; + dword = pDCTstat->Twrwr >> 2; + val |= dword << 10; + dword = (pDCTstat->Trdrd - 0x3) >> 2; + val |= dword << 12; + Set_NB32_DCT(dev, dct, reg, val); + } } static void Get_Trdrd(struct MCTStatStruc *pMCTstat, @@ -4970,6 +4971,8 @@ static void Get_Trdrd(struct MCTStatStruc *pMCTstat, Trdrd = ((int8_t)(pDCTstat->DqsRcvEnGrossMax - pDCTstat->DqsRcvEnGrossMin) >> 1) + 1; if (Trdrd > 8) Trdrd = 8; + if (Trdrd < 3) + Trdrd = 3; pDCTstat->Trdrd = Trdrd; } @@ -5280,47 +5283,31 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, if (pDCTstat->NodePresent) { mct_PhyController_Config(pMCTstat, pDCTstat, 0); mct_PhyController_Config(pMCTstat, pDCTstat, 1); - } - if (!(pDCTstat->LogicalCPUID & AMD_DR_Dx)) { /* mct_checkForDxSupport */ - mct_ExtMCTConfig_Cx(pDCTstat); - mct_ExtMCTConfig_Bx(pDCTstat); - } else { /* For Dx CPU */ - val = 0x0CE00F00 | 1 << 29/* FlushWrOnStpGnt */; - if (!(pDCTstat->GangedMode)) - val |= 0x20; /* MctWrLimit = 8 for Unganged mode */ - else - val |= 0x40; /* MctWrLimit = 16 for ganged mode */ - Set_NB32(pDCTstat->dev_dct, 0x11C, val); - - val = Get_NB32(pDCTstat->dev_dct, 0x1B0); - val &= 0xFFFFF8C0; - val |= 0x101; /* BKDG recommended settings */ - val |= 0x0FC00000; /* Agesa V5 */ - if (!(pDCTstat->GangedMode)) - val |= 1 << 12; - else - val &= ~(1 << 12); - val &= 0x0FFFFFFF; if (!is_fam15h()) { - switch (pDCTstat->Speed) { - case 4: - val |= 0x50000000; /* 5 for DDR800 */ - break; - case 5: - val |= 0x60000000; /* 6 for DDR1066 */ - break; - case 6: - val |= 0x80000000; /* 8 for DDR800 */ - break; - default: - val |= 0x90000000; /* 9 for DDR1600 */ - break; - } - } - Set_NB32(pDCTstat->dev_dct, 0x1B0, val); + /* Family 10h CPUs */ + mct_ExtMCTConfig_Cx(pDCTstat); + mct_ExtMCTConfig_Bx(pDCTstat); + mct_ExtMCTConfig_Dx(pDCTstat); + } else { + /* Family 15h CPUs */ + val = 0x0ce00f00 | 0x1 << 29; /* FlushWrOnStpGnt */ + val |= 0x10 << 2; /* MctWrLimit = 16 */ + Set_NB32(pDCTstat->dev_dct, 0x11c, val); + + val = Get_NB32(pDCTstat->dev_dct, 0x1b0); + val &= ~0x3; /* AdapPrefMissRatio = 0x1 */ + val |= 0x1; + val &= ~(0x3 << 2); /* AdapPrefPositiveStep = 0x0 */ + val &= ~(0x3 << 4); /* AdapPrefNegativeStep = 0x0 */ + val &= ~(0x7 << 8); /* CohPrefPrbLmt = 0x1 */ + val |= (0x1 << 8); + val |= (0x1 << 12); /* EnSplitDctLimits = 0x1 */ + val |= (0x7 << 22); /* PrefFourConf = 0x7 */ + val |= (0x7 << 25); /* PrefFiveConf = 0x7 */ + val &= ~(0xf << 28); /* DcqBwThrotWm = 0x0 */ + Set_NB32(pDCTstat->dev_dct, 0x1b0, val); - if (is_fam15h()) { uint8_t wm1; uint8_t wm2; @@ -5351,11 +5338,11 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, break; } - val = Get_NB32(pDCTstat->dev_dct, 0x1B4); + val = Get_NB32(pDCTstat->dev_dct, 0x1b4); val &= ~(0x3ff); val |= ((wm2 & 0x1f) << 5); val |= (wm1 & 0x1f); - Set_NB32(pDCTstat->dev_dct, 0x1B4, val); + Set_NB32(pDCTstat->dev_dct, 0x1b4, val); } } } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c index 253a89f..da7ce16 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c @@ -98,7 +98,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, BitDelta = bsf(AddrHiMask) - bsf(AddrLoMask); for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel++) { - reg = 0x40+(ChipSel<<2); /*Dram CS Base 0 */ + reg = 0x40 + (ChipSel<<2); /* Dram CS Base 0 */ val = Get_NB32_DCT(dev, dct, reg); if (val & 3) { val_lo = val & AddrLoMask; @@ -114,7 +114,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, if(ChipSel & 1) continue; - reg = 0x60 + ((ChipSel>>1)<<2); /*Dram CS Mask 0 */ + reg = 0x60 + ((ChipSel>>1)<<2); /* Dram CS Mask 0 */ val = Get_NB32_DCT(dev, dct, reg); val_lo = val & AddrLoMask; val_hi = val & AddrHiMask; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctprod.c b/src/northbridge/amd/amdmct/mct_ddr3/mctprod.c new file mode 100644 index 0000000..2b62d4c --- /dev/null +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctprod.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +void mct_ExtMCTConfig_Dx(struct DCTStatStruc *pDCTstat) +{ + uint32_t dword; + + if (pDCTstat->LogicalCPUID & AMD_DR_Dx) { + dword = 0x0ce00f00 | 0x1 << 29; /* FlushWrOnStpGnt */ + if (!(pDCTstat->GangedMode)) + dword |= 0x18 << 2; /* MctWrLimit = 0x18 for unganged mode */ + else + dword |= 0x10 << 2; /* MctWrLimit = 0x10 for ganged mode */ + Set_NB32(pDCTstat->dev_dct, 0x11c, dword); + + dword = Get_NB32(pDCTstat->dev_dct, 0x1b0); + dword &= ~0x3; /* AdapPrefMissRatio = 0x1 */ + dword |= 0x1; + dword &= ~(0x3 << 2); /* AdapPrefPositiveStep = 0x0 */ + dword &= ~(0x3 << 4); /* AdapPrefNegativeStep = 0x0 */ + dword &= ~(0x7 << 8); /* CohPrefPrbLmt = 0x1 */ + dword |= (0x1 << 8); + dword |= (0x7 << 22); /* PrefFourConf = 0x7 */ + dword |= (0x7 << 25); /* PrefFiveConf = 0x7 */ + + if (!(pDCTstat->GangedMode)) + dword |= (0x1 << 12); /* EnSplitDctLimits = 0x1 */ + else + dword &= ~(0x1 << 12); /* EnSplitDctLimits = 0x0 */ + + dword &= ~(0xf << 28); /* DcqBwThrotWm = ... */ + switch (pDCTstat->Speed) { + case 4: + dword |= (0x5 << 28); /* ...5 for DDR800 */ + break; + case 5: + dword |= (0x6 << 28); /* ...6 for DDR1066 */ + break; + case 6: + dword |= (0x8 << 28); /* ...8 for DDR800 */ + break; + default: + dword |= (0x9 << 28); /* ...9 for DDR1600 */ + break; + } + Set_NB32(pDCTstat->dev_dct, 0x1b0, dword); + } +}

1 0

New patch to review for coreboot: braswell/skylake: Add FspUpdVpd.h to fix compilation
by Stefan Reinauer 18 Nov '15

18 Nov '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12467 -gerrit commit cb2902eea1577adf491b89848173295bc09fac63 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:32:27 2015 -0800 braswell/skylake: Add FspUpdVpd.h to fix compilation Intel folks, you need to run "make gitconfig" before handling coreboot code. checkpath.pl says: total: 9 errors, 344 warnings, 1247 lines checked Change-Id: Ib88ac9b37d2f86d323b9a04cb17a5a490c61ff5b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/soc/intel/braswell/include/FspUpdVpd.h | 507 ++++++++++++++++++++ src/soc/intel/skylake/include/FspUpdVpd.h | 740 +++++++++++++++++++++++++++++ 2 files changed, 1247 insertions(+) diff --git a/src/soc/intel/braswell/include/FspUpdVpd.h b/src/soc/intel/braswell/include/FspUpdVpd.h new file mode 100644 index 0000000..fe0f849 --- /dev/null +++ b/src/soc/intel/braswell/include/FspUpdVpd.h @@ -0,0 +1,507 @@ +/** @file + +Copyright (c) 2015, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPDVPD_H__ +#define __FSPUPDVPD_H__ + +#pragma pack(1) + + +#define MAX_CHANNELS_NUM 2 +#define MAX_DIMMS_NUM 2 + +typedef struct { + UINT32 VendorDeviceId; + UINT16 SubSystemId; + UINT8 RevisionId; /// 0xFF applies to all steppings + UINT8 FrontPanelSupport; + UINT16 NumberOfRearJacks; + UINT16 NumberOfFrontJacks; +} BL_PCH_AZALIA_VERB_TABLE_HEADER; + +typedef struct { + BL_PCH_AZALIA_VERB_TABLE_HEADER VerbTableHeader; + UINT32 *VerbTableData; +} BL_PCH_AZALIA_VERB_TABLE; + +typedef struct { + UINT8 Pme : 1; /// 0: Disable; 1: Enable + UINT8 DS : 1; /// 0: Docking is not supported; 1:Docking is supported + UINT8 DA : 1; /// 0: Docking is not attached; 1:Docking is attached + UINT8 HdmiCodec : 1; /// 0: Disable; 1: Enable + UINT8 AzaliaVCi : 1; /// 0: Disable; 1: Enable + UINT8 Rsvdbits : 3; + UINT8 AzaliaVerbTableNum; /// Number of verb tables provided by platform + BL_PCH_AZALIA_VERB_TABLE *AzaliaVerbTable; /// Pointer to the actual verb table(s) + UINT16 ResetWaitTimer; /// The delay timer after Azalia reset, the value is number of microseconds +} BL_PCH_AZALIA_CONFIG; + +typedef struct { + UINT32 Confg; + UINT32 ConfgChanges; + UINT32 Misc; + UINT32 MmioAddr; + CHAR16 *Name; +} BL_GPIO_FAMILY_INIT; + +typedef struct { + UINT32 Confg0; + UINT32 Confg0Changes; + UINT32 Confg1; + UINT32 Confg1Changes; + UINT32 Community; + UINT32 MmioAddr; + CHAR16 *Name; + UINT32 Misc; +} BL_GPIO_PAD_INIT; + +typedef struct { + UINT8 DimmId; + UINT32 SizeInMb; + UINT16 MfgId; + /** Module part number for DRR3 is 18 bytes + but DRR4 is 20 bytes as per JEDEC Spec, so + reserving 20 bytes **/ + UINT8 ModulePartNum[20]; +} DIMM_INFO; + +typedef struct { + UINT8 ChannelId; + UINT8 DimmCount; + DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; +} CHANNEL_INFO; + +typedef struct { + UINT8 Revision; + UINT8 DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; + UINT16 MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + UINT8 ChannelCount; + CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; +} FSP_SMBIOS_MEMORY_INFO; + + + +typedef struct { +/** Offset 0x0020 +**/ + UINT64 Signature; +/** Offset 0x0028 +**/ + UINT8 Revision; +/** Offset 0x0029 +**/ + UINT8 UnusedUpdSpace2[7]; +/** Offset 0x0030 + Tseg Size + Size of SMRAM memory reserved. +**/ + UINT16 PcdMrcInitTsegSize; +/** Offset 0x0032 + MMIO Size + Size of memory address space reserved for MMIO (Memory Mapped I/O). +**/ + UINT16 PcdMrcInitMmioSize; +/** Offset 0x0034 + DIMM 0 SPD SMBus Address + SPD Address of DIMM. +**/ + UINT8 PcdMrcInitSpdAddr1; +/** Offset 0x0035 + DIMM 1 SPD SMBus Address + SPD Address of DIMM. +**/ + UINT8 PcdMrcInitSpdAddr2; +/** Offset 0x0036 +**/ + UINT8 PcdMemChannel0Config; +/** Offset 0x0037 +**/ + UINT8 PcdMemChannel1Config; +/** Offset 0x0038 +**/ + UINT32 PcdMemorySpdPtr; +/** Offset 0x003C + Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics +**/ + UINT8 PcdIgdDvmt50PreAlloc; +/** Offset 0x003D + Aperture Size + Select the Aperture Size. +**/ + UINT8 PcdApertureSize; +/** Offset 0x003E + GTT Size + Select the GTT Size. +**/ + UINT8 PcdGttSize; +/** Offset 0x003F + Enable Legacy E/F segments decoding to ROM + If disabled, E0000h-FFFFFh decoding will be routed to DRAM. +**/ + UINT8 PcdLegacySegDecode; +/** Offset 0x0040 + Enable DVFS + Enable/disable DVFS. +**/ + UINT8 PcdDvfsEnable; +/** Offset 0x0041 + MemoryType + To Configure Memory Type +**/ + UINT8 PcdMemoryTypeEnable; +/** Offset 0x0042 +**/ + UINT8 ReservedMemoryInitUpd[190]; +} MEMORY_INIT_UPD; + +typedef struct { +/** Offset 0x0100 +**/ + UINT64 Signature; +/** Offset 0x0108 +**/ + UINT8 Revision; +/** Offset 0x0109 +**/ + UINT8 UnusedUpdSpace3[7]; +/** Offset 0x0110 + SD Card Mode + SD Card Mode +**/ + UINT8 PcdSdcardMode; +/** Offset 0x0111 + Enable HSUART0 + Enable/disable HSUART0. +**/ + UINT8 PcdEnableHsuart0; +/** Offset 0x0112 + Enable HSUART1 + Enable/disable HSUART1. +**/ + UINT8 PcdEnableHsuart1; +/** Offset 0x0113 + Enable Azalia + Enable/disable Azalia controller. +**/ + UINT8 PcdEnableAzalia; +/** Offset 0x0114 +**/ + BL_PCH_AZALIA_CONFIG* AzaliaConfigPtr; +/** Offset 0x0118 + Enable SATA + Enable/disable SATA controller. +**/ + UINT8 PcdEnableSata; +/** Offset 0x0119 + Enable XHCI + Enable/disable XHCI controller. +**/ + UINT8 PcdEnableXhci; +/** Offset 0x011A + Enable LPE + Choose LPE Mode. +**/ + UINT8 PcdEnableLpe; +/** Offset 0x011B + Enable DMA0 + Enable/disable DMA0. +**/ + UINT8 PcdEnableDma0; +/** Offset 0x011C + Enable DMA1 + Enable/disable DMA1. +**/ + UINT8 PcdEnableDma1; +/** Offset 0x011D + Enable I2C0 + Enable/disable I2C0. +**/ + UINT8 PcdEnableI2C0; +/** Offset 0x011E + Enable I2C1 + Enable/disable I2C1. +**/ + UINT8 PcdEnableI2C1; +/** Offset 0x011F + Enable I2C2 + Enable/disable I2C2. +**/ + UINT8 PcdEnableI2C2; +/** Offset 0x0120 + Enable I2C3 + Enable/disable I2C3. +**/ + UINT8 PcdEnableI2C3; +/** Offset 0x0121 + Enable I2C4 + Enable/disable I2C4. +**/ + UINT8 PcdEnableI2C4; +/** Offset 0x0122 + Enable I2C5 + Enable/disable I2C5. +**/ + UINT8 PcdEnableI2C5; +/** Offset 0x0123 + Enable I2C6 + Enable/disable I2C6. +**/ + UINT8 PcdEnableI2C6; +/** Offset 0x0124 +**/ + UINT32 GraphicsConfigPtr; +/** Offset 0x0128 +**/ + BL_GPIO_FAMILY_INIT* GpioFamilyInitTablePtr; +/** Offset 0x012C +**/ + BL_GPIO_PAD_INIT* GpioPadInitTablePtr; +/** Offset 0x0130 +**/ + UINT8 PunitPwrConfigDisable; +/** Offset 0x0131 +**/ + UINT8 ChvSvidConfig; +/** Offset 0x0132 +**/ + UINT8 DptfDisable; +/** Offset 0x0133 + eMMC Mode + EMMC Mode +**/ + UINT8 PcdEmmcMode; +/** Offset 0x0134 +**/ + UINT8 PcdUsb3ClkSsc; +/** Offset 0x0135 +**/ + UINT8 PcdDispClkSsc; +/** Offset 0x0136 +**/ + UINT8 PcdSataClkSsc; +/** Offset 0x0137 +**/ + UINT8 Usb2Port0PerPortPeTxiSet; +/** Offset 0x0138 +**/ + UINT8 Usb2Port0PerPortTxiSet; +/** Offset 0x0139 +**/ + UINT8 Usb2Port0IUsbTxEmphasisEn; +/** Offset 0x013A +**/ + UINT8 Usb2Port0PerPortTxPeHalf; +/** Offset 0x013B +**/ + UINT8 Usb2Port1PerPortPeTxiSet; +/** Offset 0x013C +**/ + UINT8 Usb2Port1PerPortTxiSet; +/** Offset 0x013D +**/ + UINT8 Usb2Port1IUsbTxEmphasisEn; +/** Offset 0x013E +**/ + UINT8 Usb2Port1PerPortTxPeHalf; +/** Offset 0x013F +**/ + UINT8 Usb2Port2PerPortPeTxiSet; +/** Offset 0x0140 +**/ + UINT8 Usb2Port2PerPortTxiSet; +/** Offset 0x0141 +**/ + UINT8 Usb2Port2IUsbTxEmphasisEn; +/** Offset 0x0142 +**/ + UINT8 Usb2Port2PerPortTxPeHalf; +/** Offset 0x0143 +**/ + UINT8 Usb2Port3PerPortPeTxiSet; +/** Offset 0x0144 +**/ + UINT8 Usb2Port3PerPortTxiSet; +/** Offset 0x0145 +**/ + UINT8 Usb2Port3IUsbTxEmphasisEn; +/** Offset 0x0146 +**/ + UINT8 Usb2Port3PerPortTxPeHalf; +/** Offset 0x0147 +**/ + UINT8 Usb2Port4PerPortPeTxiSet; +/** Offset 0x0148 +**/ + UINT8 Usb2Port4PerPortTxiSet; +/** Offset 0x0149 +**/ + UINT8 Usb2Port4IUsbTxEmphasisEn; +/** Offset 0x014A +**/ + UINT8 Usb2Port4PerPortTxPeHalf; +/** Offset 0x014B +**/ + UINT8 Usb3Lane0Ow2tapgen2deemph3p5; +/** Offset 0x014C +**/ + UINT8 Usb3Lane1Ow2tapgen2deemph3p5; +/** Offset 0x014D +**/ + UINT8 Usb3Lane2Ow2tapgen2deemph3p5; +/** Offset 0x014E +**/ + UINT8 Usb3Lane3Ow2tapgen2deemph3p5; +/** Offset 0x014F + SATA Interface Speed + Select SATA controller Interface Speed. +**/ + UINT8 PcdSataInterfaceSpeed; +/** Offset 0x0150 +**/ + UINT8 PcdPchUsbSsicPort; +/** Offset 0x0151 +**/ + UINT8 PcdPchUsbHsicPort; +/** Offset 0x0152 +**/ + UINT8 PcdPcieRootPortSpeed; +/** Offset 0x0153 +**/ + UINT8 PcdPchSsicEnable; +/** Offset 0x0154 +**/ + UINT32 PcdLogoPtr; +/** Offset 0x0158 +**/ + UINT32 PcdLogoSize; +/** Offset 0x015C +**/ + UINT8 PcdRtcLock; +/** Offset 0x015D + PMIC I2c Bus Number + I2c Bus Number to communicate with PMIC +**/ + UINT8 PMIC_I2CBus; +/** Offset 0x015E + Enable ISP + Enable/disable ISP. +**/ + UINT8 ISPEnable; +/** Offset 0x015F + Select ISP Device Number + Select ISP PCI Device Configuration +**/ + UINT8 ISPPciDevConfig; +/** Offset 0x0160 + Processor Turbo Mode + Enable/disable Processor Turbo Mode. +**/ + UINT8 PcdTurboMode; +/** Offset 0x0161 +**/ + UINT8 ReservedSiliconInitUpd[413]; +} SILICON_INIT_UPD; + +#define FSP_UPD_SIGNATURE 0x2444505557534224 /* '$BSWUPD$' */ +#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ +#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ + +typedef struct _UPD_DATA_REGION { +/** Offset 0x0000 +**/ + UINT64 Signature; +/** Offset 0x0008 +**/ + UINT8 Revision; +/** Offset 0x0009 +**/ + UINT8 UnusedUpdSpace0[7]; +/** Offset 0x0010 +**/ + UINT32 MemoryInitUpdOffset; +/** Offset 0x0014 +**/ + UINT32 SiliconInitUpdOffset; +/** Offset 0x0018 +**/ + UINT64 UnusedUpdSpace1; +/** Offset 0x0020 +**/ + MEMORY_INIT_UPD MemoryInitUpd; +/** Offset 0x0100 +**/ + SILICON_INIT_UPD SiliconInitUpd; +/** Offset 0x02FE +**/ + UINT16 PcdRegionTerminator; +/** Offset 0x0300 +**/ + UINT8 UnusedUpdSpace4[2123]; +/** Offset 0x0B4B +**/ + UINT8 PcdPaddingSpace; +} UPD_DATA_REGION; + +#define FSP_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */ +#define FSP_IMAGE_REV 0x01010100 + +typedef struct _VPD_DATA_REGION { +/** Offset 0x0000 +**/ + UINT64 PcdVpdRegionSign; +/** Offset 0x0008 + PcdImageRevision +**/ + UINT32 PcdImageRevision; +/** Offset 0x000C +**/ + UINT32 PcdUpdRegionOffset; +/** Offset 0x0010 +**/ + UINT8 UnusedVpdSpace0[20]; +/** Offset 0x0024 +**/ + UINT8 PcdEnableSecureBoot; +} VPD_DATA_REGION; + +#pragma pack() + +#endif diff --git a/src/soc/intel/skylake/include/FspUpdVpd.h b/src/soc/intel/skylake/include/FspUpdVpd.h new file mode 100644 index 0000000..dca5db2 --- /dev/null +++ b/src/soc/intel/skylake/include/FspUpdVpd.h @@ -0,0 +1,740 @@ +/** @file + +Copyright (c) 2015, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPDVPD_H__ +#define __FSPUPDVPD_H__ + +#pragma pack(push, 1) + + +#define MRC_MAX_RCOMP 3 +#define MRC_MAX_RCOMP_TARGETS 5 +#define MAX_CHANNELS_NUM 2 +#define MAX_DIMMS_NUM 2 + +typedef struct { + UINT16 RcompResistor[MRC_MAX_RCOMP]; ///< Offset 0: Reference RCOMP resistors on motherboard + UINT16 RcompTarget[MRC_MAX_RCOMP_TARGETS]; ///< Offset 6: RCOMP target values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv +} MEMORY_RCOMP; + + +typedef struct { + UINT32 VendorDeviceId; /* Vendor ID/Device ID */ + UINT16 SubSystemId; /* SubSystem ID */ + UINT8 RevisionId; /* Revision ID. 0xFF applies to all steppings */ + UINT8 FrontPanelSupport; /* Front panel support (1=yes, 2=no) */ + UINT16 NumberOfRearJacks; /* Number of Rear Jacks */ + UINT16 NumberOfFrontJacks; /* Number of Front Jacks */ +} SA_HDA_HEADER; + +typedef struct { + UINT16 VendorId; /* Codec Vendor ID */ + UINT16 DeviceId; /* Codec Device ID */ + UINT8 RevisionId; /* Revision ID of the codec. 0xFF matches any revision. */ + UINT8 SdiNo; /* SDI number, 0xFF matches any SDI. */ + UINT16 DataDwords; /* Number of data DWORDs pointed by the codec data buffer. */ + UINT32 Reserved; /* Reserved for future use. Must be set to 0. */ +} AZALIA_HEADER; + +typedef struct { + AZALIA_HEADER Header; /* AZALIA PCH header */ + UINT32 *Data; /* Pointer to the data buffer. Its length is specified in the header */ +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + +typedef struct { + UINT8 DimmId; + UINT32 SizeInMb; + UINT16 MfgId; + UINT8 ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */ +} DIMM_INFO; + +typedef struct { + UINT8 ChannelId; + UINT8 DimmCount; + DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; +} CHANNEL_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; + UINT16 MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + UINT8 ChannelCount; + CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; +} FSP_SMBIOS_MEMORY_INFO; + + + +/** UPD data structure for FspMemoryInitApi +**/ +typedef struct { + +/** Offset 0x0020 +**/ + UINT64 Signature; + +/** Offset 0x0028 - Revision + Revision version of the MemoryInitUpd Region +**/ + UINT8 Revision; + +/** Offset 0x0029 +**/ + UINT8 UnusedUpdSpace0[7]; + +/** Offset 0x0030 - Platform Reserved Memory Size + The minimum platform memory size required to pass control into DXE + 0x400000 : 0x400000 +**/ + UINT64 PlatformMemorySize; + +/** Offset 0x0038 - Memory SPD Pointer Channel 0 Dimm 0 + Pointer to SPD data in Memory. Default: 0 for empty channel +**/ + UINT32 MemorySpdPtr00; + +/** Offset 0x003C - Memory SPD Pointer Channel 0 Dimm 1 + Pointer to SPD data in Memory. Default: 0 for empty channel +**/ + UINT32 MemorySpdPtr01; + +/** Offset 0x0040 - Memory SPD Pointer Channel 1 Dimm 0 + Pointer to SPD data in Memory. Default: 0 for empty channel +**/ + UINT32 MemorySpdPtr10; + +/** Offset 0x0044 - Memory SPD Pointer Channel 1 Dimm 1 + Pointer to SPD data in Memory. Default: 0 for empty channel +**/ + UINT32 MemorySpdPtr11; + +/** Offset 0x0048 - SPD Data Length + Length of SPD Data + 0x100:256 Bytes, 0x200:512 Bytes +**/ + UINT16 MemorySpdDataLen; + +/** Offset 0x004A - Dq Byte Map CH0 + Dq byte mapping between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqByteMapCh0[12]; + +/** Offset 0x0056 - Dq Byte Map CH1 + Dq byte mapping between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqByteMapCh1[12]; + +/** Offset 0x0062 - Dqs Map CPU to DRAM CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramCh0[8]; + +/** Offset 0x006A - Dqs Map CPU to DRAM CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramCh1[8]; + +/** Offset 0x0072 - RcompResister settings + Indicates RcompReister settings: Board-dependent +**/ + UINT16 RcompResistor[3]; + +/** Offset 0x0078 - RcompTarget settings + RcompTarget settings: board-dependent +**/ + UINT16 RcompTarget[5]; + +/** Offset 0x0082 - Dqs Pins Interleaved Setting + Indicates DqPinsInterleaved setting: board-dependent + $EN_DIS +**/ + UINT8 DqPinsInterleaved; + +/** Offset 0x0083 - VREF_CA + CA Vref routing: board-dependent + 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, 2:VREF_CA to CH_A and VREF_DQ_B to CH_B +**/ + UINT8 CaVrefConfig; + +/** Offset 0x0084 - Smram Mask + The SMM Regions AB-SEG and/or H-SEG reserved + 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both +**/ + UINT8 SmramMask; + +/** Offset 0x0085 - MRC Fast Boot + Enables/Disable the MRC fast path thru the MRC + $EN_DIS +**/ + UINT8 MrcFastBoot; + +/** Offset 0x0086 +**/ + UINT16 UnusedUpdSpace1; + +/** Offset 0x0088 - Intel Enhanced Debug + Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied + 0 : Disable, 0x400000 : Enable +**/ + UINT32 IedSize; + +/** Offset 0x008C - Tseg Size + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build + 0x0400000:4MB, 0x01000000:16MB +**/ + UINT32 TsegSize; + +/** Offset 0x0090 - MMIO Size + Size of memory address space reserved for MMIO (Memory Mapped I/O) in MB. + 0x0600 : 0x0600 +**/ + UINT16 MmioSize; + +/** Offset 0x0092 - Probeless Trace + Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. This also requires IED to be enabled. + $EN_DIS +**/ + UINT8 ProbelessTrace; + +/** Offset 0x0093 - Enable LAN + Enable/disable LAN controller. + $EN_DIS +**/ + UINT8 EnableLan; + +/** Offset 0x0094 +**/ + UINT16 UnusedUpdSpace2; + +/** Offset 0x0096 - Enable Trace Hub + Enable/disable Trace Hub function. + $EN_DIS +**/ + UINT8 EnableTraceHub; + +/** Offset 0x0097 - Enable PCIE RP + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + UINT8 PcieRpEnable[20]; + +/** Offset 0x00AB - Enable PCIE RP CLKREQ Support + Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + UINT8 PcieRpClkReqSupport[20]; + +/** Offset 0x00BF - Configure CLKREQ Number + Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + UINT8 PcieRpClkReqNumber[20]; + +/** Offset 0x00D3 - Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics. + 0x00:0 MB, 0x01:32 MB, 0x02:64 MB, 0x03:128 MB, 0x04:256 MB, 0x05:512 MB +**/ + UINT8 IgdDvmt50PreAlloc; + +/** Offset 0x00D4 - Internal Graphics + Enable/disable internal graphics. + $EN_DIS +**/ + UINT8 InternalGfx; + +/** Offset 0x00D5 - Aperture Size + Select the Aperture Size. + 0:128 MB, 1:256 MB, 2:512 MB +**/ + UINT8 ApertureSize; + +/** Offset 0x00D6 - SA GV + System Agent dynamic frequency support and when enabled memory will be training at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, 2=FixedHigh, and 3=Enabled. + 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled +**/ + UINT8 SaGv; + +/** Offset 0x00D7 - Rank Margin Tool + Enable/disable Rank Margin Tool. + $EN_DIS +**/ + UINT8 RMT; + +/** Offset 0x00D8 - DDR Frequency Limit + Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, 2400 and 0 for Auto. + 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 0:Auto +**/ + UINT16 DdrFreqLimit; + +/** Offset 0x00DA - Board Type + MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server + 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server +**/ + UINT8 UserBd; + +/** Offset 0x00DB +**/ + UINT8 UnusedUpdSpace3[105]; + +/** Offset 0x0144 - MMA Test Content Pointer + Pointer to MMA Test Content in Memory +**/ + UINT32 MmaTestContentPtr; + +/** Offset 0x0148 - MMA Test Content Size + Size of MMA Test Content in Memory +**/ + UINT32 MmaTestContentSize; + +/** Offset 0x014C - MMA Test Config Pointer + Pointer to MMA Test Config in Memory +**/ + UINT32 MmaTestConfigPtr; + +/** Offset 0x0150 - MMA Test Config Size + Size of MMA Test Config in Memory +**/ + UINT32 MmaTestConfigSize; + +/** Offset 0x0154 - Enable CIO2 Controller + Enable/disable SKYCAM CIO2 Controller. + $EN_DIS +**/ + UINT8 Cio2Enable; + +/** Offset 0x0155 +**/ + UINT8 ReservedMemoryInitUpd[171]; +} MEMORY_INIT_UPD; + +/** UPD data structure for FspSiliconInitApi +**/ +typedef struct { + +/** Offset 0x0200 +**/ + UINT64 Signature; + +/** Offset 0x0208 - Revision + Revision version of the SiliconInitUpd Region +**/ + UINT8 Revision; + +/** Offset 0x0209 +**/ + UINT8 UnusedUpdSpace4[7]; + +/** Offset 0x0210 - Logo Pointer + Points to PEI Display Logo Image + 0 : 0 +**/ + UINT32 LogoPtr; + +/** Offset 0x0214 - Logo Size + Size of PEI Display Logo Image + 0 : 0 +**/ + UINT32 LogoSize; + +/** Offset 0x0218 - Graphics Configuration Ptr + Points to VBT + 0 : 0 +**/ + UINT32 GraphicsConfigPtr; + +/** Offset 0x021C - Enable Device 4 + Enable/disable Device 4 + $EN_DIS +**/ + UINT8 Device4Enable; + +/** Offset 0x021D - Enable Azalia + Enable/disable Azalia controller. + $EN_DIS +**/ + UINT8 EnableAzalia; + +/** Offset 0x021E - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + UINT8 DspEnable; + +/** Offset 0x021F - Select HDAudio IoBuffer Ownership + Indicates the ownership of the I/O buffer between Intel HD Audio link vs I2S0 / I2S port. 0: Intel HD-Audio link owns all the I/O buffers. 1: Intel HD-Audio link owns 4 of the I/O buffers for 1 HD-Audio codec connection, and I2S1 port owns 4 of the I/O buffers for 1 I2S codec connection. 2: Reserved. 3: I2S0 and I2S1 ports own all the I/O buffers. + 0:HD-A Link, 1:Shared HD-A Link and I2S Port, 3:I2S Ports +**/ + UINT8 IoBufferOwnership; + +/** Offset 0x0220 +**/ + UINT8 UnusedUpdSpace5; + +/** Offset 0x0221 - Enable eMMC Controller + Enable/disable eMMC Controller. + $EN_DIS +**/ + UINT8 ScsEmmcEnabled; + +/** Offset 0x0222 - Enable eMMC HS400 Mode + Enable eMMC HS400 Mode. + $EN_DIS +**/ + UINT8 ScsEmmcHs400Enabled; + +/** Offset 0x0223 - Enable SdCard Controller + Enable/disable SD Card Controller. + $EN_DIS +**/ + UINT8 ScsSdCardEnabled; + +/** Offset 0x0224 - Enable ISH Controller + Enable/disable ISH Controller. + $EN_DIS +**/ + UINT8 IshEnable; + +/** Offset 0x0225 - Show SPI controller + Enable/disable to show SPI controller. + $EN_DIS +**/ + UINT8 ShowSpiController; + +/** Offset 0x0226 - HSIO HECI Messaging + Enable/Disable. 0: Disable, prevent the HSIO version check and HSIO init messages from being sent, 1: enable + $EN_DIS +**/ + UINT8 HsioMessaging; + +/** Offset 0x0227 - HECI3 state + The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 Heci3Enabled; + +/** Offset 0x0228 - MicrocodeRegionBase + Memory Base of Microcode Updates +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x022C - MicrocodeRegionSize + Size of Microcode Updates +**/ + UINT32 MicrocodeRegionSize; + +/** Offset 0x0230 - Turbo Mode + Enable/Disable Turbo mode. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 TurboMode; + +/** Offset 0x0231 - Enable SATA SALP Support + Enable/disable SATA Aggressive Link Power Management. + $EN_DIS +**/ + UINT8 SataSalpSupport; + +/** Offset 0x0232 - Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsEnable[8]; + +/** Offset 0x023A - Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlp[8]; + +/** Offset 0x0242 - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 PortUsb20Enable[16]; + +/** Offset 0x0252 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 PortUsb30Enable[10]; + +/** Offset 0x025C - Enable xDCI controller + Enable/disable to xDCI controller. + $EN_DIS +**/ + UINT8 XdciEnable; + +/** Offset 0x025D - Enable XHCI SSIC Eanble + Enable/disable XHCI SSIC port. + $EN_DIS +**/ + UINT8 SsicPortEnable; + +/** Offset 0x025E - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + UINT8 SmbusEnable; + +/** Offset 0x025F - Enable SerialIo Device Mode + 0:Disabled, 1:ACPI Mode, 2:PCI Mode, 3:Hidden mode, 4:Legacy UART mode - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,UART0,UART1,UART2 device mode respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. +**/ + UINT8 SerialIoDevMode[11]; + +/** Offset 0x026A - Address of PCH_DEVICE_INTERRUPT_CONFIG table. + The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. +**/ + UINT32 DevIntConfigPtr; + +/** Offset 0x026E - Number of DevIntConfig Entry + Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL. +**/ + UINT8 NumOfDevIntConfig; + +/** Offset 0x026F - PIRQx to IRQx Map Config + PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode. +**/ + UINT8 PxRcConfig[8]; + +/** Offset 0x0277 - Select GPIO IRQ Route + GPIO IRQ Select. The valid value is 14 or 15. + 0 : 0xFF +**/ + UINT8 GpioIrqRoute; + +/** Offset 0x0278 - Select SciIrqSelect + SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. + 0 : 0xFF +**/ + UINT8 SciIrqSelect; + +/** Offset 0x0279 - Select TcoIrqSelect + TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. + 0 : 0xFF +**/ + UINT8 TcoIrqSelect; + +/** Offset 0x027A - Enable/Disable Tco IRQ + Enable/disable TCO IRQ + $EN_DIS +**/ + UINT8 TcoIrqEnable; + +/** Offset 0x027B - AzaliaVerbTableNumEntries + Number of Entries in Azalia Verb Table +**/ + UINT8 AzaliaVerbTableNumEntries; + +/** Offset 0x027C - AzaliaVerbTablePtr + Pointer to Array of pointers to Codec Table. +**/ + UINT32 AzaliaVerbTablePtr; + +/** Offset 0x0280 - RTC CMOS RAM LOCK + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. + $EN_DIS +**/ + UINT8 RtcLock; + +/** Offset 0x0281 - Enable SATA + Enable/disable SATA controller. + $EN_DIS +**/ + UINT8 EnableSata; + +/** Offset 0x0282 - SATA Mode + Select SATA controller working mode. + 0:AHCI, 1:RAID +**/ + UINT8 SataMode; + +/** Offset 0x0283 - USB Per Port HS Preemphasis Bias + USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. +**/ + UINT8 Usb2AfePetxiset[16]; + +/** Offset 0x0293 - USB Per Port HS Transmitter Bias + USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. +**/ + UINT8 Usb2AfeTxiset[16]; + +/** Offset 0x02A3 - USB Per Port HS Transmitter Emphasis + USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. +**/ + UINT8 Usb2AfePredeemp[16]; + +/** Offset 0x02B3 - USB Per Port Half Bit Pre-emphasis + USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port. +**/ + UINT8 Usb2AfePehalfbit[16]; + +/** Offset 0x02C3 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment + Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmphEnable[10]; + +/** Offset 0x02CD - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmph[10]; + +/** Offset 0x02D7 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment + Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmpEnable[10]; + +/** Offset 0x02E1 - USB 3.0 TX Output Downscale Amplitude Adjustment + USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmp[10]; + +/** Offset 0x02EB +**/ + UINT8 ReservedSiliconInitUpd[271]; +} SILICON_INIT_UPD; + +#define FSP_UPD_SIGNATURE 0x244450554C4B5324 /* '$SKLUPD$' */ +#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ +#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ + +/** UPD data structure. The UPD_DATA_REGION may contain some reserved or unused fields in the data structure. These fields are required to use the default values provided in the FSP binary. Intel always recommends copying the whole UPD_DATA_REGION from the flash to a local structure in the stack before overriding any field. +**/ +typedef struct { + +/** Offset 0x0000 +**/ + UINT64 Signature; + +/** Offset 0x0008 - This field is not an option and is a Revision of the UPD_DATA_REGION. It can be used by the boot loader to validate the UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package. + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build +**/ + UINT8 Revision; + +/** Offset 0x0009 +**/ + UINT8 ReservedUpd0[7]; + +/** Offset 0x0010 - MemoryInitUpdOffset + This field contains the offset of the MemoryInitUpd structure relative to UPD_DATA_REGION +**/ + UINT32 MemoryInitUpdOffset; + +/** Offset 0x0014 - SiliconInitUpdOffset + This field contains the offset of the SiliconInitUpd structure relative to UPD_DATA_REGION +**/ + UINT32 SiliconInitUpdOffset; + +/** Offset 0x0018 +**/ + UINT64 ReservedUpd1; + +/** Offset 0x0020 +**/ + MEMORY_INIT_UPD MemoryInitUpd; + +/** Offset 0x0200 +**/ + SILICON_INIT_UPD SiliconInitUpd; + +/** Offset 0x03FA - RegionTerminator + This field is not an option and is a termination field at the end of the data structure. This field is will have a value 0x55AA indicating the end of UPD data.The boot loader should never override this field. +**/ + UINT16 RegionTerminator; +} UPD_DATA_REGION; + +#define FSP_IMAGE_ID 0x245053464C4B5324 /* '$SKLFSP$' */ +#define FSP_IMAGE_REV 0x01070000 + +/** VPD data structure +**/ +typedef struct { + +/** Offset 0x0000 +**/ + UINT64 PcdVpdRegionSign; + +/** Offset 0x0008 - PcdImageRevision + This field is not an option and is a revision ID for the FSP release. It can be used by the boot loader to validate the VPD/UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION/VPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package. This should match the ImageRevision in FSP_INFO_HEADER. +**/ + UINT32 PcdImageRevision; + +/** Offset 0x000C - PcdUpdRegionOffset + This field is not an option and contains the offset of the UPD data region within the FSP release image. The boot loader can use it to find the location of UPD_DATA_REGION. +**/ + UINT32 PcdUpdRegionOffset; + +/** Offset 0x0010 +**/ + UINT8 UnusedVpdSpace0[32]; + +/** Offset 0x0030 - PcdSerialIoUartDebugEnable + Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. + 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing +**/ + UINT8 PcdSerialIoUartDebugEnable; + +/** Offset 0x0031 - PcdSerialIoUartNumber + Select SerialIo Uart Controller for debug. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 PcdSerialIoUartNumber; + +/** Offset 0x0032 +**/ + UINT32 PcdSerialIoUartInputClock; +} VPD_DATA_REGION; + +#pragma pack(pop) + +#endif

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New patch to review for coreboot: intel/skylake: Fix flash_controller.c compilation
by Stefan Reinauer 18 Nov '15

18 Nov '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12466 -gerrit commit 782fa5f17e43b184d26877278911b9c39e139253 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:31:15 2015 -0800 intel/skylake: Fix flash_controller.c compilation Change-Id: Ib8a0e1ebc76b7dca3dd785b09398b73abad46366 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/soc/intel/skylake/flash_controller.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c index a68c1e9..5ba2d4e 100644 --- a/src/soc/intel/skylake/flash_controller.c +++ b/src/soc/intel/skylake/flash_controller.c @@ -53,7 +53,7 @@ static inline uint32_t spi_read_faddr(pch_spi_regs * const regs) static int wait_for_completion(pch_spi_regs * const regs, int timeout_ms, size_t len) { - uint16_t hsfs; + uint16_t hsfs = 0; uint16_t hsfc; uint32_t addr; struct stopwatch sw; @@ -72,7 +72,7 @@ static int wait_for_completion(pch_spi_regs * const regs, int timeout_ms, addr = spi_read_faddr(regs); hsfc = spi_read_hsfc(regs); printk(BIOS_ERR, "%ld ms Transaction timeout between offset " - "0x%08x and 0x%08x (= 0x%08x + %zd) HSFC=%x HSFS=%x!\n", + "0x%08x and 0x%08zx (= 0x%08x + %zd) HSFC=%x HSFS=%x!\n", stopwatch_duration_msecs(&sw), addr, addr + len - 1, addr, len - 1, hsfc, hsfs); return 1; @@ -82,7 +82,7 @@ static int wait_for_completion(pch_spi_regs * const regs, int timeout_ms, addr = spi_read_faddr(regs); hsfc = spi_read_hsfc(regs); printk(BIOS_ERR, "Transaction error between offset 0x%08x and " - "0x%08x (= 0x%08x + %zd) HSFC=%x HSFS=%x!\n", + "0x%08zx (= 0x%08x + %zd) HSFC=%x HSFS=%x!\n", addr, addr + len - 1, addr, len - 1, hsfc, hsfs); return 1;

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New patch to review for coreboot: fsp1_1: Don't hide build related options behind HAVE_FSP_BIN
by Stefan Reinauer 18 Nov '15

18 Nov '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12465 -gerrit commit 9fb6abb36eb5e29a865bb12f7a5dec56145b6696 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:28:19 2015 -0800 fsp1_1: Don't hide build related options behind HAVE_FSP_BIN The right thing to do is to hide them behind PLATFORM_USES_FSP1_1. The only things that should depend on HAVE_FSP_BIN is the code that actually adds the file to CBFS, and the path to the file in Kconfig. Change-Id: I9b6c3ed0cdfb0e02421d7b98c488a66e39add947 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/drivers/intel/fsp1_1/Kconfig | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 4ae3727..ed37820 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -40,8 +40,6 @@ config HAVE_FSP_BIN Note: Without this binary, coreboot builds relying on the FSP will not boot -if HAVE_FSP_BIN - config CPU_MICROCODE_CBFS_LEN hex "Microcode update region length in bytes" default 0 @@ -62,23 +60,19 @@ config FSP_FILE config FSP_IMAGE_ID_STRING string "8 byte platform string identifying the FSP platform" + default "FSPROCKS" help 8 ASCII character byte signature string that will help match the FSP binary to a supported hardware configuration. -config FSP_INCLUDE_PATH - string "Path for FSP specific include files" - help - The path and filename of the Intel FSP binary for this platform. - config FSP_LOC hex "Intel FSP Binary location in CBFS" + default 0xfe0000 help The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool). -endif #HAVE_FSP_BIN config DISPLAY_FAST_BOOT_DATA bool "Display fast boot data"

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coreboot-gerrit November 2015