coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: Don't include files from blobs directory
by Stefan Reinauer 18 Nov '15

18 Nov '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12464 -gerrit commit 724d9f49037c5f882974ca6dbd7a2298c2f0dc6e Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:26:07 2015 -0800 Don't include files from blobs directory coreboot's binary policy forbids to store include files required to build the host binaries in the blobs directory. Hence remove the infrastructure to do so. Change-Id: I66d57f84cbc392bbfc1f951d13424742d2cff978 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/drivers/intel/fsp1_1/Makefile.inc | 2 -- src/drivers/intel/fsp1_1/include/fsp/soc_binding.h | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index a296b53..f101cc4 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -36,8 +36,6 @@ ramstage-y += stage_cache.c ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include -# Where FspUpdVpd.h can be picked up from. -CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH) cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc diff --git a/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h b/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h index 04b01e9..affb43f 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h +++ b/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h @@ -27,7 +27,7 @@ #pragma pack(push) /* - * This file is found by way of the Kconfig FSP_INCLUDE_PATH option. It is + * This file is found in the soc / chipset directory. It is * a per implementation specific header. i.e. different FSP implementations * for different chipsets. */

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New patch to review for coreboot: Drop abuild.disabled files for Braswell / Skylake boards
by Stefan Reinauer 18 Nov '15

18 Nov '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12463 -gerrit commit 34b8f5408e842fdc6f8e216392bae8198aa0d6f4 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:21:34 2015 -0800 Drop abuild.disabled files for Braswell / Skylake boards This needs to go to the end of the patch stack, but it in the beginning to get more information from jenkins about what's broken. Change-Id: I479ad473c260fc914d224cb58f4be1837aff2502 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/google/chell/abuild.disabled | 2 -- src/mainboard/google/cyan/abuild.disabled | 2 -- src/mainboard/google/glados/abuild.disabled | 2 -- src/mainboard/google/lars/abuild.disabled | 2 -- src/mainboard/intel/kunimitsu/abuild.disabled | 2 -- src/mainboard/intel/sklrvp/abuild.disabled | 2 -- src/mainboard/intel/strago/abuild.disabled | 2 -- 7 files changed, 14 deletions(-) diff --git a/src/mainboard/google/chell/abuild.disabled b/src/mainboard/google/chell/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/chell/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/google/cyan/abuild.disabled b/src/mainboard/google/cyan/abuild.disabled deleted file mode 100644 index 025ebea..0000000 --- a/src/mainboard/google/cyan/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Braswell FSP binary and header -files along with the Braswell microcode files from Intel. diff --git a/src/mainboard/google/glados/abuild.disabled b/src/mainboard/google/glados/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/glados/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/google/lars/abuild.disabled b/src/mainboard/google/lars/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/lars/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/intel/kunimitsu/abuild.disabled b/src/mainboard/intel/kunimitsu/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/intel/kunimitsu/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/intel/sklrvp/abuild.disabled b/src/mainboard/intel/sklrvp/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/intel/sklrvp/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/intel/strago/abuild.disabled b/src/mainboard/intel/strago/abuild.disabled deleted file mode 100644 index 025ebea..0000000 --- a/src/mainboard/intel/strago/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Braswell FSP binary and header -files along with the Braswell microcode files from Intel.

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Patch set updated for coreboot: cpu/amd/fam10h-fam15h: Bring HT register configuration in line with BKDG
by Timothy Pearson 18 Nov '15

18 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12022 -gerrit commit f5100a3fd44d66470afc917c918728cc3986027f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 2 21:18:29 2015 -0500 cpu/amd/fam10h-fam15h: Bring HT register configuration in line with BKDG The existing HyperTransport register configuration values were incorrect in many spots. Apply the correct values from the BKDG on Family 10h and Family 15h processors. Change-Id: I009b6f478340e2dbfcda2b4534473d4397f9ecef Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/defaults.h | 168 +++++++++++++++++++++------ 1 file changed, 133 insertions(+), 35 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index b6c9bc4..a3c7b1f 100644 --- a/src/cpu/amd/family_10h-family_15h/defaults.h +++ b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -371,44 +371,140 @@ static const struct { [2] SyncOnUcEccEn = 1 */ /* XBAR buffer settings */ - { 3, 0x6c, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00018052, 0x700780f7 }, + { 3, 0x6c, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL, + 0x00018052, 0x700780f7 }, /* IsocRspDBC = 0x0, + UpRspDBC = 0x1, + DatBuf24 = 0x1, + DnRspDBC = 0x1, + DnReqDBC = 0x1, + UpReqDBC = 0x2 */ + + /* XBAR buffer settings */ + { 3, 0x6c, AMD_DR_Dx, AMD_PTYPE_ALL, + 0x00028052, 0x700780f7 }, /* IsocRspDBC = 0x0, + UpRspDBC = 0x2, + DatBuf24 = 0x1, + DnRspDBC = 0x1, + DnReqDBC = 0x1, + UpReqDBC = 0x2 */ /* XBAR buffer settings */ { 3, 0x6c, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x10010052, 0x700700f7 }, + 0x10010052, 0x700700f7 }, /* IsocRspDBC = 0x1, + UpRspDBC = 0x1, + DnRspDBC = 0x1, + DnReqDBC = 0x1, + UpReqDBC = 0x2 */ /* Errata 281 Workaround */ - { 3, 0x6C, ( AMD_DR_B0 | AMD_DR_B1), + { 3, 0x6c, (AMD_DR_B0 | AMD_DR_B1), AMD_PTYPE_SVR, 0x00010094, 0x700780F7 }, - { 3, 0x6C, AMD_FAM10_ALL, AMD_PTYPE_UMA, + { 3, 0x6c, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x60018051, 0x700780F7 }, - { 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00041153, 0x777777F7 }, + { 3, 0x70, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL, + 0x00041153, 0x777777f7 }, /* IsocRspCBC = 0x0, + IsocPreqCBC = 0x0, + IsocReqCBC = 0x0, + UpRspCBC = 0x4, + DnPreqCBC = 0x1, + UpPreqCBC = 0x1, + DnRspCBC = 0x1, + DnReqCBC = 0x1, + UpReqCBC = 0x3 */ + + { 3, 0x70, AMD_DR_Dx, AMD_PTYPE_ALL, + 0x00051153, 0x777777f7 }, /* IsocRspCBC = 0x0, + IsocPreqCBC = 0x0, + IsocReqCBC = 0x0, + UpRspCBC = 0x5, + DnPreqCBC = 0x1, + UpPreqCBC = 0x1, + DnRspCBC = 0x1, + DnReqCBC = 0x1, + UpReqCBC = 0x3 */ { 3, 0x70, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x10171155, 0x777777f7 }, + 0x10171155, 0x777777f7 }, /* IsocRspCBC = 0x1, + IsocPreqCBC = 0x0, + IsocReqCBC = 0x1, + UpRspCBC = 0x7, + DnPreqCBC = 0x1, + UpPreqCBC = 0x1, + DnRspCBC = 0x1, + DnReqCBC = 0x1, + UpReqCBC = 0x5 */ { 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_UMA, - 0x61221151, 0x777777F7 }, + 0x61221151, 0x777777f7 }, /* IsocRspCBC = 0x6, + IsocPreqCBC = 0x1, + IsocReqCBC = 0x2, + UpRspCBC = 0x2, + DnPreqCBC = 0x1, + UpPreqCBC = 0x1, + DnRspCBC = 0x1, + DnReqCBC = 0x1, + UpReqCBC = 0x1 */ + + { 3, 0x74, AMD_FAM10_ALL, ~AMD_PTYPE_UMA, + 0x00081111, 0xf7ff7777 }, /* DRReqCBC = 0x0, + IsocPreqCBC = 0x0, + IsocReqCBC = 0x0, + ProbeCBC = 0x8, + DnPreqCBC = 0x1, + UpPreqCBC = 0x1, + DnReqCBC = 0x1, + UpReqCBC = 0x1 */ { 3, 0x74, AMD_FAM10_ALL, AMD_PTYPE_UMA, - 0x00080101, 0x000F7777 }, + 0x00480101, 0xf7ff7777 }, /* DRReqCBC = 0x0, + IsocPreqCBC = 0x0, + IsocReqCBC = 0x4, + ProbeCBC = 0x8, + DnPreqCBC = 0x0, + UpPreqCBC = 0x1, + DnReqCBC = 0x0, + UpReqCBC = 0x1 */ { 3, 0x74, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00172111, 0x77ff7777 }, - - { 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00090914, 0x707FFF1F }, + 0x00172111, 0xf7ff7777 }, /* DRReqCBC = 0x0, + IsocPreqCBC = 0x0, + IsocReqCBC = 0x1, + ProbeCBC = 0x7, + DnPreqCBC = 0x2, + UpPreqCBC = 0x1, + DnReqCBC = 0x1, + UpReqCBC = 0x1 */ + + { 3, 0x7c, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL, + 0x00090914, 0x707fff1f }, /* XBar2SriFreeListCBInc = 0x0, + Sri2XbarFreeRspDBC = 0x0, + Sri2XbarFreeXreqDBC = 0x9, + Sri2XbarFreeRspCBC = 0x0, + Sri2XbarFreeXreqCBC = 0x9, + Xbar2SriFreeListCBC = 0x14 */ + + { 3, 0x7c, AMD_DR_Dx, AMD_PTYPE_ALL, + 0x00090a18, 0x707fff1f }, /* XBar2SriFreeListCBInc = 0x0, + Sri2XbarFreeRspDBC = 0x0, + Sri2XbarFreeXreqDBC = 0x9, + Sri2XbarFreeRspCBC = 0x0, + Sri2XbarFreeXreqCBC = 0x9, + Xbar2SriFreeListCBC = 0x14 */ /* Errata 281 Workaround */ { 3, 0x7C, ( AMD_DR_B0 | AMD_DR_B1), AMD_PTYPE_SVR, 0x00144514, 0x707FFF1F }, - { 3, 0x7C, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x040d0f16, 0x07ffff1f }, + { 3, 0x7c, AMD_FAM15_ALL, AMD_PTYPE_ALL, + 0x040d0f16, 0x77ffff1f }, /* XBar2SriFreeListCBInc = 0x0, + SrqExtFreeListBC = 0x8, + Sri2XbarFreeRspDBC = 0x0, + Sri2XbarFreeXreqDBC = 0xd, + Sri2XbarFreeRspCBC = 0x0, + Sri2XbarFreeXreqCBC = 0xf, + Xbar2SriFreeListCBC = 0x16 */ { 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x00070814, 0x007FFF1F }, @@ -630,18 +726,16 @@ static const struct { 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */ { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x00000000, 0x000000FF }, /* Provide clear setting for logical - completeness */ + 0x0000005a, 0x000000ff }, /* Use common "safe" setting for K10 */ { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x00000000, 0x000000FF }, /* Provide clear setting for logical - completeness */ + 0x0000005a, 0x000000ff }, /* Use common "safe" setting for K10 */ { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ + 0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ + 0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ /* Link Phy Receiver Loop Filter Registers */ { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, @@ -664,24 +758,29 @@ static const struct { 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h, [20:16] RttIndex = 04h */ -/* FIXME - * Causes lockups for some reason when more than one package is installed - * Debug and reactivate! - */ -// #if 0 { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x00000000, 0x000000FF }, /* Provide clear setting for logical - completeness */ + 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa, + P0XmtRdPtr = 0x2 + P1RcvRdPtr = 0xa + P1XmtRdPtr = 0x0 */ { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x00000000, 0x000000FF }, /* Provide clear setting for logical - completeness */ + 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa, + P0XmtRdPtr = 0x2 + P1RcvRdPtr = 0xa + P1XmtRdPtr = 0x0 */ { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ + 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd, + P0XmtRdPtr = 0x4 + P1RcvRdPtr = 0xd + P1XmtRdPtr = 0x0 */ { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ + 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd, + P0XmtRdPtr = 0x4 + P1RcvRdPtr = 0xd + P1XmtRdPtr = 0x0 */ /* Link Phy Receiver Loop Filter Registers */ { 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, @@ -702,6 +801,5 @@ static const struct { { 0xC0, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h, - [20:16] RttIndex = 04h */ -// #endif + [20:16] RttIndex = 04h */ };

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Patch set updated for coreboot: northbridge/amd/amdfam10: Add probe filter support
by Timothy Pearson 18 Nov '15

18 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12021 -gerrit commit d67755270920f6389d8f0a4eb94b56f959efa1e8 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 2 21:06:39 2015 -0500 northbridge/amd/amdfam10: Add probe filter support All modern Opteron processors support the HT probe filter, which helps to increase coherent fabric performance by reducing the number of HT transactions per cache probe. AMD recommends that the probe filter be enabled on all systems with more than two nodes, and it does not hurt to enable it on systems with 2 nodes. Change-Id: I00a27a828260be8685ae622cfa5a4995add95a8e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 13 ++ .../amd/family_10h-family_15h/model_10xxx_init.c | 22 ++++ src/northbridge/amd/amdfam10/northbridge.c | 144 ++++++++++++++++++++- src/northbridge/amd/amdht/h3ncmn.c | 22 ++++ 4 files changed, 200 insertions(+), 1 deletion(-) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index a421bfcc..a6d8dc4 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -441,6 +441,19 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) cpuSetAMDMSR(id.nodeid); + /* Set up probe filter support */ + if (is_gt_rev_d()) { + uint8_t node_count; + node_count = (pci_read_config32(NODE_PCI(id.nodeid, 0), 0x60) >> 4) & 0x7; + node_count++; + + if (node_count > 1) { + msr_t msr = rdmsr(BU_CFG2_MSR); + msr.hi |= 1 << (42 - 32); + wrmsr(BU_CFG2_MSR, msr); + } + } + #if CONFIG_SET_FIDVID #if CONFIG_LOGICAL_CPUS && CONFIG_SET_FIDVID_CORE0_ONLY // Run on all AP for proper FID/VID setup. diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index 0a86966..4ccf79d 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -50,6 +50,28 @@ static inline uint8_t is_fam15h(void) return fam15h; } +static inline uint8_t is_gt_rev_d(void) +{ + uint8_t fam15h = 0; + uint8_t rev_gte_d = 0; + uint32_t family; + uint32_t model; + + family = model = cpuid_eax(0x80000001); + model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + if ((model >= 0x8) || fam15h) + /* Revision D or later */ + rev_gte_d = 1; + + return rev_gte_d; +} + static volatile uint8_t fam15h_startup_flags[MAX_NODES_SUPPORTED][MAX_CORES_SUPPORTED] = {{ 0 }}; static void model_10xxx_init(device_t dev) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index a922496..8651ad0 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -26,10 +26,13 @@ #include <lib.h> #include <smbios.h> #include <cpu/cpu.h> +#include <delay.h> #include <cpu/x86/lapic.h> +#include <cpu/x86/cache.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> +#include <cpu/amd/model_10xxx_msr.h> #include <cpu/amd/family_10h-family_15h/ram_calc.h> #if CONFIG_LOGICAL_CPUS @@ -1523,7 +1526,7 @@ static void cpu_bus_scan(device_t dev) if(i>=32) { busn--; devn-=32; - pbus = pci_domain->link_list->next); + pbus = pci_domain->link_list->next; } #endif @@ -1643,8 +1646,147 @@ static void cpu_bus_scan(device_t dev) } } +static void detect_and_enable_probe_filter(device_t dev) +{ + uint32_t dword; + + uint8_t fam15h = 0; + uint8_t rev_gte_d = 0; + uint8_t dual_node = 0; + unsigned nb_cfg_54; + uint32_t f3xe8; + uint32_t family; + uint32_t model; + + family = model = cpuid_eax(0x80000001); + model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); + + if (is_fam15h()) { + /* Family 15h or later */ + fam15h = 1; + nb_cfg_54 = 1; + } + + if ((model >= 0x8) || fam15h) + /* Revision D or later */ + rev_gte_d = 1; + + if (rev_gte_d) + /* Check for dual node capability */ + if (f3xe8 & 0x20000000) + dual_node = 1; + + if (rev_gte_d && (sysconf.nodes > 1)) { + /* Enable the probe filter */ + uint8_t i; + uint8_t pfmode = 0x0; + + uint32_t f3x58[MAX_NODES_SUPPORTED]; + uint32_t f3x5c[MAX_NODES_SUPPORTED]; + + printk(BIOS_DEBUG, "Enabling probe filter\n"); + + /* Disable L3 and DRAM scrubbers and configure system for probe filter support */ + for (i = 0; i < sysconf.nodes; i++) { + device_t f2x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 2)); + device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); + + f3x58[i] = pci_read_config32(f3x_dev, 0x58); + f3x5c[i] = pci_read_config32(f3x_dev, 0x5c); + pci_write_config32(f3x_dev, 0x58, f3x58[i] & ~((0x1f << 24) | 0x1f)); + pci_write_config32(f3x_dev, 0x5c, f3x5c[i] & ~0x1); + + dword = pci_read_config32(f2x_dev, 0x1b0); + dword &= ~(0x7 << 8); /* CohPrefPrbLmt = 0x0 */ + pci_write_config32(f2x_dev, 0x1b0, dword); + + msr_t msr = rdmsr_amd(BU_CFG2_MSR); + msr.hi |= 1 << (42 - 32); + wrmsr_amd(BU_CFG2_MSR, msr); + + if (is_fam15h()) { + uint8_t subcache_size = 0x0; + uint8_t pref_so_repl = 0x0; + uint32_t f3x1c4 = pci_read_config32(f3x_dev, 0x1c4); + if ((f3x1c4 & 0xffff) == 0xcccc) { + subcache_size = 0x1; + pref_so_repl = 0x2; + pfmode = 0x3; + } else { + pfmode = 0x2; + } + + dword = pci_read_config32(f3x_dev, 0x1d4); + dword |= 0x1 << 29; /* PFLoIndexHashEn = 0x1 */ + dword &= ~(0x3 << 20); /* PFPreferredSORepl = pref_so_repl */ + dword |= (pref_so_repl & 0x3) << 20; + dword |= 0x1 << 17; /* PFWayHashEn = 0x1 */ + dword |= 0xf << 12; /* PFSubCacheEn = 0xf */ + dword &= ~(0x3 << 10); /* PFSubCacheSize3 = subcache_size */ + dword |= (subcache_size & 0x3) << 10; + dword &= ~(0x3 << 8); /* PFSubCacheSize2 = subcache_size */ + dword |= (subcache_size & 0x3) << 8; + dword &= ~(0x3 << 6); /* PFSubCacheSize1 = subcache_size */ + dword |= (subcache_size & 0x3) << 6; + dword &= ~(0x3 << 4); /* PFSubCacheSize0 = subcache_size */ + dword |= (subcache_size & 0x3) << 4; + dword &= ~(0x3 << 2); /* PFWayNum = 0x2 */ + dword |= 0x2 << 2; + pci_write_config32(f3x_dev, 0x1d4, dword); + } else { + pfmode = 0x2; + + dword = pci_read_config32(f3x_dev, 0x1d4); + dword |= 0x1 << 29; /* PFLoIndexHashEn = 0x1 */ + dword &= ~(0x3 << 20); /* PFPreferredSORepl = 0x2 */ + dword |= 0x2 << 20; + dword |= 0xf << 12; /* PFSubCacheEn = 0xf */ + dword &= ~(0x3 << 10); /* PFSubCacheSize3 = 0x0 */ + dword &= ~(0x3 << 8); /* PFSubCacheSize2 = 0x0 */ + dword &= ~(0x3 << 6); /* PFSubCacheSize1 = 0x0 */ + dword &= ~(0x3 << 4); /* PFSubCacheSize0 = 0x0 */ + dword &= ~(0x3 << 2); /* PFWayNum = 0x2 */ + dword |= 0x2 << 2; + pci_write_config32(f3x_dev, 0x1d4, dword); + } + } + + udelay(40); + + disable_cache(); + asm("wbinvd"); + for (i = 0; i < sysconf.nodes; i++) { + device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); + + dword = pci_read_config32(f3x_dev, 0x1c4); + dword |= (0x1 << 31); /* L3TagInit = 1 */ + pci_write_config32(f3x_dev, 0x1c4, dword); + do { + } while (pci_read_config32(f3x_dev, 0x1c4) & (0x1 << 31)); + + dword = pci_read_config32(f3x_dev, 0x1d4); + dword &= ~0x3; /* PFMode = pfmode */ + dword |= pfmode & 0x3; + pci_write_config32(f3x_dev, 0x1d4, dword); + do { + } while (!(pci_read_config32(f3x_dev, 0x1d4) & (0x1 << 19))); + } + enable_cache(); + + /* Reenable L3 and DRAM scrubbers */ + for (i = 0; i < sysconf.nodes; i++) { + device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); + + pci_write_config32(f3x_dev, 0x58, f3x58[i]); + pci_write_config32(f3x_dev, 0x5c, f3x5c[i]); + } + + } +} + static void cpu_bus_init(device_t dev) { + detect_and_enable_probe_filter(dev); initialize_cpus(dev->link_list); #if CONFIG_AMD_SB_CIMX sb_After_Pci_Init(); diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index 01c0e48..8ee929d 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -103,6 +103,28 @@ static inline uint8_t is_fam15h(void) return fam15h; } +static inline uint8_t is_gt_rev_d(void) +{ + uint8_t fam15h = 0; + uint8_t rev_gte_d = 0; + uint32_t family; + uint32_t model; + + family = model = cpuid_eax(0x80000001); + model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + if ((model >= 0x8) || fam15h) + /* Revision D or later */ + rev_gte_d = 1; + + return rev_gte_d; +} + /***************************************************************************//** * * SBDFO

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Patch merged into coreboot/master: x86: Add Kconfig to disable early bootblock postcodes
by gerrit＠coreboot.org 18 Nov '15

18 Nov '15

the following patch was just integrated into master: commit 1455437c9e010bcc617c5927e18cf1cb3b02c82f Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 12 14:02:42 2015 -0700 x86: Add Kconfig to disable early bootblock postcodes The Intel cave creek chipset needs to have port 80 routing configured before any post codes can be sent to port 80h. Sending post codes out before the routing is done will hang the system. This patch allows us to disable the first couple of post codes that go out before the routing can be configured. The Kconfig symbol is selected by the cave creek chipset (fsp_i89xx). Change-Id: I9bf41669ec32744f87a1ed2de011d31c72ea38da Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: http://review.coreboot.org/12422 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: York Yang <york.yang(a)intel.com> See http://review.coreboot.org/12422 for details. -gerrit

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New patch to review for coreboot: google/veyron_danger & veyron_emile: Fix Kconfig warnings
by Martin Roth 18 Nov '15

18 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12462 -gerrit commit 904284825fd75ad8d9a5861c1ad5832ec99b410c Author: Martin Roth <martinroth(a)google.com> Date: Wed Nov 18 16:13:12 2015 -0700 google/veyron_danger & veyron_emile: Fix Kconfig warnings These platforms needed to be adjusted to fix various Kconfig warnings. Both platforms needed MAINBOARD_HAS_NATIVE_VGA_INIT because they're setting MAINBOARD_DO_NATIVE_VGA_INIT. veyron_emile needed a few symbols that depend on CHROMEOS to be moved into a new config CHROMEOS section. This matches the other CHROMEOS platforms. veyron_danger needed to select MAINBOARD_HAS_CHROMEOS before the CHROMEOS symbol was set. Change-Id: I8c7f594ba572a02513a68095c16314006fb4e379 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/veyron_danger/Kconfig | 2 ++ src/mainboard/google/veyron_emile/Kconfig | 7 +++++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/veyron_danger/Kconfig b/src/mainboard/google/veyron_danger/Kconfig index 326d940..ab549f6 100644 --- a/src/mainboard/google/veyron_danger/Kconfig +++ b/src/mainboard/google/veyron_danger/Kconfig @@ -29,6 +29,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SPI_FLASH select SPI_FLASH_GIGADEVICE select SPI_FLASH_WINBOND + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_CHROMEOS config CHROMEOS select CHROMEOS_VBNV_FLASH diff --git a/src/mainboard/google/veyron_emile/Kconfig b/src/mainboard/google/veyron_emile/Kconfig index d6ab870..af606e0 100644 --- a/src/mainboard/google/veyron_emile/Kconfig +++ b/src/mainboard/google/veyron_emile/Kconfig @@ -27,14 +27,17 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS - select PHYSICAL_REC_SWITCH select RAM_CODE_SUPPORT select SOC_ROCKCHIP_RK3288 select SPI_FLASH select SPI_FLASH_GIGADEVICE select SPI_FLASH_WINBOND - select VIRTUAL_DEV_SWITCH + select MAINBOARD_HAS_NATIVE_VGA_INIT + +config CHROMEOS select CHROMEOS_VBNV_FLASH + select PHYSICAL_REC_SWITCH + select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string

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New patch to review for coreboot: fsp1_0: Update Kconfig for symbols not depending on FSP binary
by Martin Roth 18 Nov '15

18 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12461 -gerrit commit e208d629a990c4dfe26430f4ba60e548f4d29318 Author: Martin Roth <martinroth(a)google.com> Date: Wed Nov 18 16:07:54 2015 -0700 fsp1_0: Update Kconfig for symbols not depending on FSP binary There were several symbols that were inside the 'if HAVE_FSP_BIN' that don't really depend on having the FSP binary. In theory, we should be able to build a coreboot rom and add the FSP binary later. This doesn't always work in practice, but this is a step in that direction. This also fixes a Kconfig warning for Rangeley. Change-Id: I327d8fe5231d7de25f2a74b8a193deb47e4c5ee1 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/drivers/intel/fsp1_0/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index 36bfa7c..cb83f83 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -48,6 +48,8 @@ config FSP_LOC value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool). +endif #HAVE_FSP_BIN + config ENABLE_FSP_FAST_BOOT bool "Enable Fast Boot" select ENABLE_MRC_CACHE @@ -92,8 +94,6 @@ config VIRTUAL_ROM_SIZE the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM size is 16 MB. -endif #HAVE_FSP_BIN - config CACHE_ROM_SIZE_OVERRIDE hex "Cache ROM Size" default CBFS_SIZE

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Patch set updated for coreboot: google/lars & intel/kunimitsu: Fix Kconfig warnings
by Martin Roth 18 Nov '15

18 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12460 -gerrit commit 02b58c508eb779613865ee33ff30a7e66e28d8f2 Author: Martin Roth <martinroth(a)google.com> Date: Wed Nov 18 15:19:07 2015 -0700 google/lars & intel/kunimitsu: Fix Kconfig warnings EC_SOFTWARE_SYNC depends on CHROMEOS, so move it into the CHROMEOS section. This fixes the kconfig warning: warning: (CHROMEOS && BOARD_SPECIFIC_OPTIONS ...) selects EC_SOFTWARE_SYNC which has unmet direct dependencies (MAINBOARD_HAS_CHROMEOS && CHROMEOS && VBOOT_VERIFY_FIRMWARE) Change-Id: I459f48fd18c7568c4584df7d4aefa69dec3e4907 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/lars/Kconfig | 2 +- src/mainboard/intel/kunimitsu/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/lars/Kconfig b/src/mainboard/google/lars/Kconfig index 4a1bce9..70e6726 100644 --- a/src/mainboard/google/lars/Kconfig +++ b/src/mainboard/google/lars/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC select EC_GOOGLE_CHROMEEC_PD - select EC_SOFTWARE_SYNC select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE @@ -25,6 +24,7 @@ config CHROMEOS select LID_SWITCH select VBOOT_OPROM_MATTERS select VIRTUAL_DEV_SWITCH + select EC_SOFTWARE_SYNC config IRQ_SLOT_COUNT int diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index 4132e86..5a5b3cd 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC select EC_GOOGLE_CHROMEEC_PD - select EC_SOFTWARE_SYNC select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE @@ -25,6 +24,7 @@ config CHROMEOS select LID_SWITCH select VBOOT_OPROM_MATTERS select VIRTUAL_DEV_SWITCH + select EC_SOFTWARE_SYNC config IRQ_SLOT_COUNT int

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Patch merged into coreboot/master: coreinfo: Fix off-by-one in displayed month of year
by gerrit＠coreboot.org 18 Nov '15

18 Nov '15

the following patch was just integrated into master: commit ae16c4034c37a28e352936d0600b51be21340524 Author: Yasha Cherikovsky <yasha.che3(a)gmail.com> Date: Sat Nov 14 19:16:58 2015 +0200 coreinfo: Fix off-by-one in displayed month of year According to C documentation, the range of tm_mon in struct tm is [0, 11]. Before the patch, the displayed month was indeed incorrect. Change-Id: I9f95f1e978c45b3635e2edfe1ec496d7b0dec00a Signed-off-by: Yasha Cherikovsky <yasha.che3(a)gmail.com> Reviewed-on: http://review.coreboot.org/12438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12438 for details. -gerrit

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Patch merged into coreboot/master: coreinfo: Hide blinking cursor
by gerrit＠coreboot.org 18 Nov '15

18 Nov '15

the following patch was just integrated into master: commit 619fc95e7ce62fb6ef2214c2a9f0a2517e25949b Author: Yasha Cherikovsky <yasha.che3(a)gmail.com> Date: Sat Nov 14 19:16:58 2015 +0200 coreinfo: Hide blinking cursor Change-Id: I6297fc178203dcfbd0b2a4c78dd83359e7804933 Signed-off-by: Yasha Cherikovsky <yasha.che3(a)gmail.com> Reviewed-on: http://review.coreboot.org/12437 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/12437 for details. -gerrit

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coreboot-gerrit November 2015