coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

1 participants
1544 discussions

Patch set updated for coreboot: edid: Use a better mode for 640x480
by Patrick Georgi 19 Nov '15

19 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12443 -gerrit commit f91f0cc6eb97e8ea228f59554f2af343e9ad7d3e Author: Douglas Anderson <dianders(a)chromium.org> Date: Wed Oct 28 09:52:22 2015 -0700 edid: Use a better mode for 640x480 The hardcoded clock value for 640x480 was 25.175 MHz. That's a valid clock to use, but is quite hard to make a non-jittery clock from PLLs. It's much easier to make 25.200 MHz, so let's do that. The difference between the two modes is 59.9 Hz vs. 60 Hz and it seems better to make a non-jittery 60 Hz rather than a very jittery 59.9 Hz. BRANCH=none BUG=chrome-os-partner:46256 TEST=Insignia monitor works, so do others Change-Id: I8aa124d04a90f5dcf9cfa923ed3b693fbb4a06d8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e32ce13462101dc60cfed60b6948b7597e93525a Original-Change-Id: Ia9804afe8011a915e4bec306e863d34ad7e27be5 Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309540 Original-Reviewed-by: Stphane Marchesin <marcheu(a)chromium.org> Original-(cherry picked from commit 7f32c9f460991e5e3b947117d6ae4080e630a532) Original-Reviewed-on: https://chromium-review.googlesource.com/309576 Original-Commit-Ready: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/lib/edid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/edid.c b/src/lib/edid.c index 6663d1c..8c8ab6f 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -1003,7 +1003,7 @@ static void dump_breakdown(unsigned char *edid) */ static struct edid_mode known_modes[NUM_KNOWN_MODES] = { [EDID_MODE_640x480_60Hz] = { - .name = "640x480@60Hz", .pixel_clock = 25175, .refresh = 60, + .name = "640x480@60Hz", .pixel_clock = 25200, .refresh = 60, .ha = 640, .hbl = 160, .hso = 16, .hspw = 96, .va = 480, .vbl = 45, .vso = 10, .vspw = 2, .phsync = '-', .pvsync = '-' },

1 0

Patch merged into coreboot/master: documentation: Update the document about building coreboot
by gerrit＠coreboot.org 19 Nov '15

19 Nov '15

the following patch was just integrated into master: commit dea0a7f9ae03eba9b2b0f53da415b057c778ba82 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Nov 17 23:50:14 2015 +0800 documentation: Update the document about building coreboot The previous LinuxBIOS-AMD64.tex was still working with subversion. We need a document to give the preliminary steps to build coreboot for a new guys. Change-Id: I64240c8344456e724f0823680e0534cf1db4c4a8 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/4510 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/4510 for details. -gerrit

1 0

Patch set updated for coreboot: [Not for submission] test whitespace linter on jenkins
by Patrick Georgi 19 Nov '15

19 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12472 -gerrit commit bd899d6ad948435966bf7d022af47125e7f2c851 Author: Martin Roth <martinroth(a)google.com> Date: Wed Nov 18 20:32:21 2015 -0700 [Not for submission] test whitespace linter on jenkins Change-Id: I8295e149d0e3027eb432e7a08ee9d82da135155d Signed-off-by: Martin Roth <martinroth(a)google.com> --- Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index f5326ba..7e572a6 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -15,7 +15,7 @@ GIT:=$(shell [ -d "$(top)/.git" ] && command -v git) -####################################################################### +####################################################################### # misleadingly named, this is the coreboot version export KERNELVERSION := $(strip $(if $(GIT),\ $(shell git describe --dirty --always || git describe),\ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 03dba34..6b0a893 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -16,7 +16,7 @@ ## GNU General Public License for more details. ## -################################################################################ +################################################################################ # i386 specific tools NVRAMTOOL:=$(objutil)/nvramtool/nvramtool

1 0

New patch to review for coreboot: lint: properly terminate junit report on error
by Patrick Georgi 19 Nov '15

19 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12478 -gerrit commit f9a21a734bd102f9d051338fff11394acd8b6f39 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Nov 19 15:46:37 2015 +0100 lint: properly terminate junit report on error Otherwise </testsuite> is missing and jenkins can't make sense of things. Change-Id: If11a6d2506efc9d7c915f50896b2714bc66e3b65 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/lint/lint | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/lint/lint b/util/lint/lint index 8732103..826685d 100755 --- a/util/lint/lint +++ b/util/lint/lint @@ -69,6 +69,6 @@ for script in "$(dirname "$0")/${1}-"*; do junit_write ' </testcase>' done -test $FAILED -eq 0 || { echo "ERROR: $FAILED test(s) failed."; rm -f "$LINTLOG" && exit 1; }; rm -f "$LINTLOG" junit_write '</testsuite>' +test $FAILED -eq 0 || { echo "ERROR: $FAILED test(s) failed."; exit 1; };

1 0

New patch to review for coreboot: build system: tighten down .xcompile handling some more
by Patrick Georgi 19 Nov '15

19 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12477 -gerrit commit 3d2919b711c7d05c09cf97d85e6912173386ec11 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Nov 19 15:15:33 2015 +0100 build system: tighten down .xcompile handling some more Bail out if .xcompile is incomplete or can't be regenerated. Change-Id: I74adeded7a3e849b25bf65c5b02f67820f29c7e2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile | 9 ++++++++- util/xcompile/xcompile | 1 + 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 1c6fede..bf66817 100644 --- a/Makefile +++ b/Makefile @@ -35,6 +35,7 @@ $(if $(wildcard .xcompile),,$(eval $(shell util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile))) .xcompile: util/xcompile/xcompile + rm -f $@ $< $(XGCCPATH) > $@.tmp \mv -f $@.tmp $@ 2> /dev/null @@ -120,7 +121,13 @@ else include $(HAVE_DOTCONFIG) -include .xcompile +-include .xcompile + +ifneq ($(XCOMPILE_COMPLETE),1) +$(shell rm -f .xcompile) +$(error .xcompile deleted because it's invalid. \ + Restarting the build should fix that, or explain the problem) +endif ifneq ($(CONFIG_MMX),y) CFLAGS_x86_32 += -mno-mmx diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 76c3698..a727547 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -355,3 +355,4 @@ for architecture in $SUPPORTED_ARCHITECTURES; do report_arch_toolchain fi done +echo XCOMPILE_COMPLETE:=1

1 0

Patch set updated for coreboot: build system: don't let a broken .xcompile linger in the tree
by Patrick Georgi 19 Nov '15

19 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12473 -gerrit commit 3d10161235dd73f0aa0a782592dd43e7b74aa39a Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Nov 19 09:53:04 2015 +0100 build system: don't let a broken .xcompile linger in the tree If the xcompile script fails (with an error message), we should delete the generated file so that later builds try to regenerate the file and re-report the problem if it still persists. Change-Id: I70ec37ca8ccb8ed3d8d0da48b326f5e0d722f314 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 107f3c8..1c6fede 100644 --- a/Makefile +++ b/Makefile @@ -32,7 +32,7 @@ # in addition to the dependency below, create the file if it doesn't exist # to silence stupid warnings about a file that would be generated anyway. -$(if $(wildcard .xcompile),,$(eval $(shell util/xcompile/xcompile $(XGCCPATH) > .xcompile))) +$(if $(wildcard .xcompile),,$(eval $(shell util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile))) .xcompile: util/xcompile/xcompile $< $(XGCCPATH) > $@.tmp

1 0

Patch merged into coreboot/master: device/device.c: remove warning for missing apic read resources
by gerrit＠coreboot.org 19 Nov '15

19 Nov '15

the following patch was just integrated into master: commit 7bc74ab25b81a9f1d0156a6137b40d6155a81b51 Author: Martin Roth <martinroth(a)google.com> Date: Wed Nov 18 20:23:02 2015 -0700 device/device.c: remove warning for missing apic read resources We have had the "APIC: 00 missing read_resources" messages for many years. It's obviously not an error, and also doesn't cause boot failures. Therefore, remove the message. Change-Id: I7f99c5950a3457df04e7ef6edb456b70dba9680c Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: http://review.coreboot.org/12471 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See http://review.coreboot.org/12471 for details. -gerrit

1 0

New patch to review for coreboot: siemens/mc_tcu3: Clear checksums in hwinfo
by Werner Zeh 19 Nov '15

19 Nov '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12475 -gerrit commit f253e0e6b32d12556c6ee581e9935d830951d55e Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Nov 19 14:00:55 2015 +0100 siemens/mc_tcu3: Clear checksums in hwinfo Clear the precomputed checksums in hwinfo as they will be updated in manufacturing process. Change-Id: I952ca8f1ca32831c4b296de633c0d58da111ccba Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_tcu3/hwinfo.hex | Bin 7424 -> 7424 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/src/mainboard/siemens/mc_tcu3/hwinfo.hex b/src/mainboard/siemens/mc_tcu3/hwinfo.hex index 8b1cadf..bbf6783 100644 Binary files a/src/mainboard/siemens/mc_tcu3/hwinfo.hex and b/src/mainboard/siemens/mc_tcu3/hwinfo.hex differ

1 0

Patch merged into coreboot/master: lenovo/r400: Add clone of Lenovo T400
by gerrit＠coreboot.org 19 Nov '15

19 Nov '15

the following patch was just integrated into master: commit 9d0330f537d5c6b778531a7ca209b53d060ac2ef Author: Michał Masłowski <mtjm(a)mtjm.eu> Date: Tue Feb 3 23:26:05 2015 +0100 lenovo/r400: Add clone of Lenovo T400 The existing code for the Lenovo T400 works without changes on the Lenovo R400. Same HDA verbs are provided by Lenovo BIOS on both laptops. Change-Id: I1dadddd7250ab80a4c40c2435865d72e3e5d99c9 Signed-off-by: Michał Masłowski <mtjm(a)mtjm.eu> Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> Reviewed-on: http://review.coreboot.org/8393 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See http://review.coreboot.org/8393 for details. -gerrit

1 0

New patch to review for coreboot: amdfwtool: Complete the PSP2 directory layout
by Zheng Bao 19 Nov '15

19 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12474 -gerrit commit 98c07439d22627c7c36fbde4a2c2dbcbf3aa33af Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Thu Nov 19 19:33:47 2015 +0800 amdfwtool: Complete the PSP2 directory layout PSP2 is for Combo BIOS, which is the idea that one image supports 2 kinds of APU. The PSP2 feature is for the future, not for current products. The newest document about PSP2 is not available. I made it from the draft code I made when I was in AMD. Change-Id: I65328db197c02ee67f3e99faf4ab8acabd339657 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/amdfwtool/amdfwtool.c | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index f090411..8f0343e 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -40,9 +40,22 @@ * | | * | | * +------------+---------------+----------------+------------+ + * + * PSP2 directory + * +------------+---------------+----------------+------------+ + * | 'PSP2' | Fletcher | Count | Reserved | + * +------------+---------------+----------------+------------+ + * | 1 | PSP ID | Base address | | 2nd PSP directory + * +------------+---------------+----------------+------------+ + * | 2 | PSP ID | Base address | | 3rd PSP directory + * +------------+---------------+----------------+------------+ + * | | + * | Other PSP | + * | | + * +------------+---------------+----------------+------------+ + * */ - #include <fcntl.h> #include <errno.h> #include <stdio.h> @@ -348,7 +361,7 @@ int main(int argc, char **argv) #endif void *rom = NULL; uint32_t current; - uint32_t *amd_romsig, *pspdir; + uint32_t *amd_romsig, *pspdir, *psp2dir; int targetfd; char *output; @@ -511,11 +524,25 @@ int main(int argc, char **argv) #if PSP2 if (psp2flag == 1) { - current = ALIGN(current, 0x10000); - pspdir = rom + current; + current = ALIGN(current, 0x10000); /* PSP2 dir */ + psp2dir = rom + current; amd_romsig[5] = current + ROM_BASE_ADDRESS; - current += 0x200; /* Conservative size of pspdir */ + /* TODO: remove the hardcode. */ + count = 1; + psp2dir[0] = 1347637298; /* 'PSP2' */ + psp2dir[2] = count; /* Count */ + psp2dir[3] = 0; + psp2dir[4] = count; /* PSP No.1 */ + psp2dir[5] = 0x10220b00; /* PSP ID. Documentation is needed. */ + + current += 0x100; /* Add conservative size of psp2dir. 2nd PSP dir. */ + pspdir = rom + current; + + psp2dir[6] = current + ROM_BASE_ADDRESS; + psp2dir[1] = fletcher32((uint16_t *)&psp2dir[1], (count*16 + 16)/2 - 2); + + current += 0x200; /* Add conservative size of pspdir. Start of 2nd PSP entries. */ for (count = 0; count < sizeof(amd_psp2_fw_table) / sizeof(amd_fw_entry); count ++) { current = integerate_one_psp(rom, current, pspdir, count); }

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2015