coreboot-gerrit November 2015

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Patch set updated for coreboot: fsp1_1: Don't hide build related options behind HAVE_FSP_BIN
by Stefan Reinauer 19 Nov '15

19 Nov '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12465 -gerrit commit 7e5746eb9ef0a78918c39b01988fc904329ee797 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:28:19 2015 -0800 fsp1_1: Don't hide build related options behind HAVE_FSP_BIN The right thing to do is to hide them behind PLATFORM_USES_FSP1_1. The only things that should depend on HAVE_FSP_BIN is the code that actually adds the file to CBFS, and the path to the file in Kconfig. Removing the HAVE_FSP_BIN check requires some default values for two Kconfig variables. Change-Id: I9b6c3ed0cdfb0e02421d7b98c488a66e39add947 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/drivers/intel/fsp1_1/Kconfig | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 51fa314..43435c7 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -40,8 +40,6 @@ config HAVE_FSP_BIN Note: Without this binary, coreboot builds relying on the FSP will not boot -if HAVE_FSP_BIN - config CPU_MICROCODE_CBFS_LEN hex "Microcode update region length in bytes" default 0 @@ -62,19 +60,19 @@ config FSP_FILE config FSP_IMAGE_ID_STRING string "8 byte platform string identifying the FSP platform" + default "FSPROCKS" help 8 ASCII character byte signature string that will help match the FSP binary to a supported hardware configuration. config FSP_LOC hex "Intel FSP Binary location in CBFS" + default 0xffee0000 help The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool). -endif #HAVE_FSP_BIN - config DISPLAY_FAST_BOOT_DATA bool "Display fast boot data" default n

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Patch set updated for coreboot: Don't include files from blobs / fsp directory
by Stefan Reinauer 19 Nov '15

19 Nov '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12464 -gerrit commit 3178e0168a497cf7e6e1a07e194a3889ca6d758a Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:26:07 2015 -0800 Don't include files from blobs / fsp directory coreboot's binary policy forbids to store include files required to build the host binaries in the blobs directory. Hence remove the infrastructure to do so. Change-Id: I66d57f84cbc392bbfc1f951d13424742d2cff978 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/drivers/intel/fsp1_1/Kconfig | 5 ----- src/drivers/intel/fsp1_1/Makefile.inc | 2 -- src/drivers/intel/fsp1_1/include/fsp/soc_binding.h | 2 +- 3 files changed, 1 insertion(+), 8 deletions(-) diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 4ae3727..51fa314 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -66,11 +66,6 @@ config FSP_IMAGE_ID_STRING 8 ASCII character byte signature string that will help match the FSP binary to a supported hardware configuration. -config FSP_INCLUDE_PATH - string "Path for FSP specific include files" - help - The path and filename of the Intel FSP binary for this platform. - config FSP_LOC hex "Intel FSP Binary location in CBFS" help diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index a296b53..f101cc4 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -36,8 +36,6 @@ ramstage-y += stage_cache.c ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include -# Where FspUpdVpd.h can be picked up from. -CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH) cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc diff --git a/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h b/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h index 04b01e9..affb43f 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h +++ b/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h @@ -27,7 +27,7 @@ #pragma pack(push) /* - * This file is found by way of the Kconfig FSP_INCLUDE_PATH option. It is + * This file is found in the soc / chipset directory. It is * a per implementation specific header. i.e. different FSP implementations * for different chipsets. */

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Patch set updated for coreboot: intel/skylake: Fix flash_controller.c compilation
by Stefan Reinauer 19 Nov '15

19 Nov '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12466 -gerrit commit 1dcf308e9a2f2832aaa149767b9510078f674410 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:31:15 2015 -0800 intel/skylake: Fix flash_controller.c compilation Since this code is not currently being built by coreboot, it failed compilation. Change-Id: Ib8a0e1ebc76b7dca3dd785b09398b73abad46366 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/soc/intel/skylake/flash_controller.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c index a68c1e9..aca22a9 100644 --- a/src/soc/intel/skylake/flash_controller.c +++ b/src/soc/intel/skylake/flash_controller.c @@ -61,18 +61,18 @@ static int wait_for_completion(pch_spi_regs * const regs, int timeout_ms, stopwatch_init_msecs_expire(&sw, timeout_ms); - while (!(timeout = stopwatch_expired(&sw))) { + do { hsfs = spi_read_hsfs(regs); if ((hsfs & (HSFS_FDONE | HSFS_FCERR))) break; - } + } while (!(timeout = stopwatch_expired(&sw))); if (timeout) { addr = spi_read_faddr(regs); hsfc = spi_read_hsfc(regs); printk(BIOS_ERR, "%ld ms Transaction timeout between offset " - "0x%08x and 0x%08x (= 0x%08x + %zd) HSFC=%x HSFS=%x!\n", + "0x%08x and 0x%08zx (= 0x%08x + %zd) HSFC=%x HSFS=%x!\n", stopwatch_duration_msecs(&sw), addr, addr + len - 1, addr, len - 1, hsfc, hsfs); return 1; @@ -82,7 +82,7 @@ static int wait_for_completion(pch_spi_regs * const regs, int timeout_ms, addr = spi_read_faddr(regs); hsfc = spi_read_hsfc(regs); printk(BIOS_ERR, "Transaction error between offset 0x%08x and " - "0x%08x (= 0x%08x + %zd) HSFC=%x HSFS=%x!\n", + "0x%08zx (= 0x%08x + %zd) HSFC=%x HSFS=%x!\n", addr, addr + len - 1, addr, len - 1, hsfc, hsfs); return 1;

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Patch merged into coreboot/master: romcc: Allow adding non-existent paths to include path
by gerrit＠coreboot.org 19 Nov '15

19 Nov '15

the following patch was just integrated into master: commit 3d0ba1c47f81776c9e84bc9718b7100d0a629f96 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 17:23:39 2015 -0800 romcc: Allow adding non-existent paths to include path This models gcc's (and other compilers') behavior to not bail out with an error when one of the include paths does not exist. Change-Id: Ic93a55cea6b32516fd76da9b49abe7b990829889 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/12469 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com> See http://review.coreboot.org/12469 for details. -gerrit

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Patch merged into coreboot/master: mainboard/asus/kgpe-d16: Fix I/O link detection
by gerrit＠coreboot.org 19 Nov '15

19 Nov '15

the following patch was just integrated into master: commit 48bfcdf0063d69f7bc7d3695e49a330f5a847952 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 2 21:28:31 2015 -0500 mainboard/asus/kgpe-d16: Fix I/O link detection Change-Id: Ibefc9dc2e1e0267389eb8d716408bae6026ce084 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12024 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/12024 for details. -gerrit

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Patch merged into coreboot/master: northbridge/amd/amdmct/mct_ddr3: Move K10D configuration into separate file
by gerrit＠coreboot.org 19 Nov '15

19 Nov '15

the following patch was just integrated into master: commit 4530df431e186c3ff62312b7d8551f0253c22c77 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 2 21:23:02 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Move K10D configuration into separate file Change-Id: Id45888f266fac7810a63fef43b8d7a0ee40cbf70 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12023 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/12023 for details. -gerrit

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Patch merged into coreboot/master: cpu/amd/fam10h-fam15h: Bring HT register configuration in line with BKDG
by gerrit＠coreboot.org 19 Nov '15

19 Nov '15

the following patch was just integrated into master: commit 51cfbcdddea8c4fadf378b91015045e6916c01a4 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 2 21:18:29 2015 -0500 cpu/amd/fam10h-fam15h: Bring HT register configuration in line with BKDG The existing HyperTransport register configuration values were incorrect in many spots. Apply the correct values from the BKDG on Family 10h and Family 15h processors. Change-Id: I009b6f478340e2dbfcda2b4534473d4397f9ecef Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12022 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/12022 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/sandybridge/raminit: Comment the code
by gerrit＠coreboot.org 19 Nov '15

19 Nov '15

the following patch was just integrated into master: commit 371d291df511679c6a63dfe658c4b349ee77e979 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Oct 9 13:33:25 2015 +0200 nb/intel/sandybridge/raminit: Comment the code Add lots of comments for better documentation. Change-Id: Ia203cb649857f979bb6c1c2d405b74f2ccc8f99d Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: http://review.coreboot.org/11915 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr(a)das-labor.org> See http://review.coreboot.org/11915 for details. -gerrit

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New patch to review for coreboot: console: Add help for serial IO port selection
by Martin Roth 19 Nov '15

19 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12487 -gerrit commit 2fc653e16cafc0d6a68354e16b5d8c65f57eb8e1 Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 19 11:40:43 2015 -0700 console: Add help for serial IO port selection Add help and a comment about the serial IO port selection to give the user better feedback when a port index is selected. Change-Id: I4c1614be51aee0286308fbc5c24554e218120bf7 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/console/Kconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/console/Kconfig b/src/console/Kconfig index d815637..3130ee9 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -43,6 +43,9 @@ if CONSOLE_SERIAL config UART_FOR_CONSOLE int "Index for UART port to use for console" default 0 + help + Select an I/O port to use for serial console: + 0 = 0x3f8, 1 = 0x2f8, 2 = 0x3e8, 3 = 0x2e8 # FIXME: Early programming in romstage is incorrect as we should # program different LDN to actually change the physical port. @@ -56,6 +59,15 @@ config TTYS0_BASE help Map the COM port number to the respective I/O port. +comment "Serial port base address = 0x3f8" +depends on UART_FOR_CONSOLE = 0 +comment "Serial port base address = 0x2f8" +depends on UART_FOR_CONSOLE = 1 +comment "Serial port base address = 0x3e8" +depends on UART_FOR_CONSOLE = 2 +comment "Serial port base address = 0x2e8" +depends on UART_FOR_CONSOLE = 3 + choice prompt "Baud rate" default CONSOLE_SERIAL_115200

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New patch to review for coreboot: hexdump: Fix output if length is not a multiple of 16
by Ben Gardner 19 Nov '15

19 Nov '15

Ben Gardner (gardner.ben(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12486 -gerrit commit 21a2bcb8f5a2b08481306b32b56b20b05de095e9 Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Thu Nov 19 11:43:05 2015 -0600 hexdump: Fix output if length is not a multiple of 16 hexdump currently rounds up length to a multiple of 16. So, hexdump(ptr, 12) prints 16 hex digits, including 4 garbage bytes. That isn't desirable and is easy to fix. Change-Id: I86415fa9bc6cdc84b111e5e1968e39f570f294d9 Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> --- src/lib/hexdump.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/src/lib/hexdump.c b/src/lib/hexdump.c index 6b09379..7907a38 100644 --- a/src/lib/hexdump.c +++ b/src/lib/hexdump.c @@ -30,21 +30,28 @@ void hexdump(const void *memory, size_t length) for (i = 0; i < length; i += 16) { int j; + int left = MIN(length - i, 16); - all_zero++; - for (j = 0; j < 16; j++) { - if (m[i + j] != 0) { - all_zero = 0; - break; + if (left < 16) { + all_zero = 0; + } else { + all_zero++; + for (j = 0; j < 16; j++) { + if (m[i + j] != 0) { + all_zero = 0; + break; + } } } if (all_zero < 2) { printk(BIOS_DEBUG, "%p:", memory + i); - for (j = 0; j < 16; j++) + for (j = 0; j < left; j++) printk(BIOS_DEBUG, " %02x", m[i + j]); + for (j = left; j < 16; j++) + printk(BIOS_DEBUG, " "); printk(BIOS_DEBUG, " "); - for (j = 0; j < 16; j++) + for (j = 0; j < left; j++) printk(BIOS_DEBUG, "%c", isprint(m[i + j]) ? m[i + j] : '.'); printk(BIOS_DEBUG, "\n");

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coreboot-gerrit November 2015