coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: coreinfo: Rewrite bootlog_module
by Yasha Cherikovsky 19 Nov '15

19 Nov '15

Yasha Cherikovsky (yasha.che3(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12440 -gerrit commit b9e6dc32315572388db7e681e8cb8436a44e94e5 Author: Yasha Cherikovsky <yasha.che3(a)gmail.com> Date: Sat Nov 14 19:21:14 2015 +0200 coreinfo: Rewrite bootlog_module The old bootlog_module implementation was completely broken: - It assumed that the console buffer is located at address 0x90000, and of size 64K. It is not correct nowadays. - It displayed the buffer in a very hacky way, the code was riddled with TODOs and FIXMEs. Scrolling had sometimes unexpected behavior. The new implementation: - Uses the cbmem console as the source of data. It takes the console information from lib_sysinfo of libpayload, which is constructed from the coreboot tables (no more hardcoded adressess). - Properly sanitizes the console buffer for display, which makes scolling and display much easier to implement. Change-Id: I3f87ec920631da2acfd3f52273228703f22f469f Signed-off-by: Yasha Cherikovsky <yasha.che3(a)gmail.com> --- payloads/coreinfo/bootlog_module.c | 209 +++++++++++++++++++++++++------------ 1 file changed, 144 insertions(+), 65 deletions(-) diff --git a/payloads/coreinfo/bootlog_module.c b/payloads/coreinfo/bootlog_module.c index 27653d3..1d990d1 100644 --- a/payloads/coreinfo/bootlog_module.c +++ b/payloads/coreinfo/bootlog_module.c @@ -17,33 +17,134 @@ #if IS_ENABLED(CONFIG_MODULE_BOOTLOG) -#define CONFIG_COREBOOT_PRINTK_BUFFER_ADDR 0x90000 -#define CONFIG_COREBOOT_PRINTK_BUFFER_SIZE 65536 +#define LINES_SHOWN 19 +#define TAB_WIDTH 2 -static char *buf; -static s32 cursor = 0; -static s32 cursor_max; + +/* Globals that are used for tracking screen state */ +static char *g_buf = NULL; +static s32 g_line = 0; +static s32 g_lines_count = 0; +static s32 g_max_cursor_line = 0; + + +/* Copied from libpayload/drivers/cbmem_console.c */ +struct cbmem_console { + u32 size; + u32 cursor; + u8 body[0]; +} __attribute__ ((__packed__)); + + +static u32 char_width(char c, u32 cursor, u32 screen_width) +{ + if (c == '\n') { + return screen_width - (cursor % screen_width); + } else if (c == '\t') { + return TAB_WIDTH; + } else if (isprint(c)) { + return 1; + } + + return 0; +} + +static u32 calculate_chars_count(char *str, u32 str_len, u32 screen_width, u32 screen_height) +{ + u32 i, count = 0; + + for (i = 0; i < str_len; i++) { + count += char_width(str[i], count, screen_width); + } + + /* Ensure that 'count' can occupy at least the whole screen */ + if (count < screen_width * screen_height) { + count = screen_width * screen_height; + } + + /* Pad to line end */ + if (count % screen_width != 0) { + count += screen_width - (count % screen_width); + } + + return count; +} + +/* + * This method takes an input buffer and sanitizes it for display, which means: + * - '\n' is converted to spaces until end of line + * - Tabs are converted to spaces of size TAB_WIDTH + * - Only printable characters are preserved + */ +static int sanitize_buffer_for_display(char *str, u32 str_len, char *out, u32 out_len, u32 screen_width) +{ + u32 cursor = 0; + u32 i; + + for (i = 0; i < str_len && cursor < out_len; i++) { + u32 width = char_width(str[i], cursor, screen_width); + if (width == 1) { + out[cursor++] = str[i]; + } else if (width > 1) { + while (width-- && cursor < out_len) { + out[cursor++] = ' '; + } + } + } + + /* Fill the rest of the out buffer with spaces */ + while (cursor < out_len) { + out[cursor++] = ' '; + } + + return 0; +} static int bootlog_module_init(void) { - int i; - volatile unsigned long *ptr = - (void *)(CONFIG_COREBOOT_PRINTK_BUFFER_ADDR + 16); /* FIXME */ + /* Make sure that lib_sysinfo is initialized */ + int ret = lib_get_sysinfo(); + if (ret) { + return -1; + } + + struct cbmem_console *console = lib_sysinfo.cbmem_cons; + if (console == NULL) { + return -1; + } + /* Extract console information */ + char *buffer = (char *)(&(console->body)); + u32 buffer_size = console->size; + u32 cursor = console->cursor; + + /* The cursor may be bigger than buffer size when the buffer is full */ + if (cursor >= buffer_size) { + cursor = buffer_size - 1; + } + + /* Calculate how much characters will be displayed on screen */ + u32 chars_count = calculate_chars_count(buffer, cursor + 1, SCREEN_X, LINES_SHOWN); - buf = malloc(CONFIG_COREBOOT_PRINTK_BUFFER_SIZE); - if (!buf) { - /* TODO */ + /* Sanity check, chars_count must be padded to full line */ + if (chars_count % SCREEN_X != 0) { + return -2; } - memcpy(buf, (char *)ptr, CONFIG_COREBOOT_PRINTK_BUFFER_SIZE); + g_lines_count = chars_count / SCREEN_X; + g_max_cursor_line = MAX(g_lines_count - 1 - LINES_SHOWN, 0); - cursor_max = CONFIG_COREBOOT_PRINTK_BUFFER_SIZE; - for (i = 0; i < 20; i++) { - do { - cursor_max--; - } while (*(buf + cursor_max) != '\n'); + g_buf = malloc(chars_count); + if (!g_buf) { + return -3; + } + + if (sanitize_buffer_for_display(buffer, cursor + 1, + g_buf, chars_count, + SCREEN_X) < 0) { + free(g_buf); + g_buf = NULL; + return -4; } - cursor_max++; /* Stay _behind_ the newline. */ /* TODO: Maybe a _cleanup hook where we call free()? */ @@ -52,74 +153,52 @@ static int bootlog_module_init(void) static int bootlog_module_redraw(WINDOW *win) { - int x = 0, y = 0; - char *tmp = buf + cursor; - print_module_title(win, "Coreboot Bootlog"); - /* FIXME: Handle lines longer than 80 characters. */ - while (y <= 18) { - mvwaddch(win, y + 2, x, isprint(*tmp) ? *tmp : ' '); - x++; - tmp++; - if (*tmp == '\n') { - y++; - x = 0; - tmp++; /* Skip the newline. */ + if (!g_buf) { + return -1; + } + + int x = 0, y = 0; + char *tmp = g_buf + g_line * SCREEN_X; + + for (y = 0; y < LINES_SHOWN; y++) { + for (x = 0; x < SCREEN_X; x++) { + mvwaddch(win, y + 2, x, *tmp); + tmp++; } + } return 0; } -/* TODO: Simplify code. */ static int bootlog_module_handle(int key) { - int i; + if (!g_buf) { + return 0; + } switch (key) { case KEY_DOWN: - if (cursor == cursor_max) - return 0; - while (*(buf + cursor) != '\n') - cursor++; - cursor++; /* Skip the newline. */ + g_line++; break; case KEY_UP: - if (cursor == 0) - return 0; - cursor--; /* Skip the newline. */ - do { - cursor--; - } while (*(buf + cursor) != '\n'); - cursor++; /* Stay _behind_ the newline. */ + g_line--; break; - case KEY_NPAGE: - if (cursor == cursor_max) - return 0; - for (i = 0; i < 20; i++) { - while (*(buf + cursor) != '\n') - cursor++; - cursor++; /* Skip the newline. */ - } + case KEY_NPAGE: /* Page up */ + g_line -= LINES_SHOWN; break; - case KEY_PPAGE: - if (cursor == 0) - return 0; - for (i = 0; i < 20; i++) { - do { - cursor--; - } while (*(buf + cursor) != '\n'); - } - cursor++; /* Stay _behind_ the newline. */ + case KEY_PPAGE: /* Page down */ + g_line += LINES_SHOWN; break; } - if (cursor > cursor_max) - cursor = cursor_max; + if (g_line < 0) + g_line = 0; - if (cursor < 0) - cursor = 0; + if (g_line > g_max_cursor_line) + g_line = g_max_cursor_line; return 1; }

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Patch set updated for coreboot: IASL: Enable warnings as errors
by Martin Roth 19 Nov '15

19 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10663 -gerrit commit 05e50c2521a98dbb8fbb6afcd3f97d0b75e3c279 Author: Martin Roth <gaumless(a)gmail.com> Date: Thu Jun 25 09:36:27 2015 -0600 IASL: Enable warnings as errors Change-Id: If0da0ac709bd8c0e8e2dbd3a498fe6ecb5500a81 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 65aa71c..f5dde5b 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -196,7 +196,7 @@ cbfs-files-$(if $(2),$(2),y) += $(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1). $(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h @printf " IASL $$(subst $(top)/,,$$(@))\n" $(CC_ramstage) -x assembler-with-cpp -E -MMD -MT $$(@) $$(CPPFLAGS_ramstage) -D__ACPI__ -P -include $(src)/include/kconfig.h -I$(obj) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-$(ARCH-ramstage-y))/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$@ - cd $$(dir $$@); $(IASL) -p $$(notdir $$@) $$(notdir $$@) + cd $$(dir $$@); $(IASL) -we -p $$(notdir $$@) $$(notdir $$@) endef #######################################################################

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Patch set updated for coreboot: Drop abuild.disabled files for Braswell / Skylake boards
by Stefan Reinauer 19 Nov '15

19 Nov '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12463 -gerrit commit df8d97edcc8fcd0bbd91a8a9f6acdf8e42f941de Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:21:34 2015 -0800 Drop abuild.disabled files for Braswell / Skylake boards Make sure the latest & greatest Intel targets actually build in our build system. Change-Id: I479ad473c260fc914d224cb58f4be1837aff2502 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/google/chell/abuild.disabled | 2 -- src/mainboard/google/cyan/abuild.disabled | 2 -- src/mainboard/google/glados/abuild.disabled | 2 -- src/mainboard/google/lars/abuild.disabled | 2 -- src/mainboard/intel/kunimitsu/abuild.disabled | 2 -- src/mainboard/intel/sklrvp/abuild.disabled | 2 -- src/mainboard/intel/strago/abuild.disabled | 2 -- 7 files changed, 14 deletions(-) diff --git a/src/mainboard/google/chell/abuild.disabled b/src/mainboard/google/chell/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/chell/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/google/cyan/abuild.disabled b/src/mainboard/google/cyan/abuild.disabled deleted file mode 100644 index 025ebea..0000000 --- a/src/mainboard/google/cyan/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Braswell FSP binary and header -files along with the Braswell microcode files from Intel. diff --git a/src/mainboard/google/glados/abuild.disabled b/src/mainboard/google/glados/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/glados/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/google/lars/abuild.disabled b/src/mainboard/google/lars/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/lars/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/intel/kunimitsu/abuild.disabled b/src/mainboard/intel/kunimitsu/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/intel/kunimitsu/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/intel/sklrvp/abuild.disabled b/src/mainboard/intel/sklrvp/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/intel/sklrvp/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/intel/strago/abuild.disabled b/src/mainboard/intel/strago/abuild.disabled deleted file mode 100644 index 025ebea..0000000 --- a/src/mainboard/intel/strago/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Braswell FSP binary and header -files along with the Braswell microcode files from Intel.

1 0

Patch set updated for coreboot: braswell/skylake: Add FspUpdVpd.h to fix compilation
by Stefan Reinauer 19 Nov '15

19 Nov '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12467 -gerrit commit ccb7fbf554566b701a8deb509b0aecf4343b248b Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:32:27 2015 -0800 braswell/skylake: Add FspUpdVpd.h to fix compilation Imported from cros repo 18ae19c Change-Id: Ib88ac9b37d2f86d323b9a04cb17a5a490c61ff5b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/soc/intel/braswell/Makefile.inc | 1 + src/soc/intel/skylake/Makefile.inc | 1 + .../intel/fsp/fsp1_1/braswell/FspUpdVpd.h | 507 ++++++++++++++ .../intel/fsp/fsp1_1/skylake/FspUpdVpd.h | 740 +++++++++++++++++++++ 4 files changed, 1249 insertions(+) diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 426f359..54b9c6a 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -54,6 +54,7 @@ smm-y += tsc_freq.c CPPFLAGS_common += -I$(src)/soc/intel/braswell/ CPPFLAGS_common += -I$(src)/soc/intel/braswell/include +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/braswell CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 682f90d..e824f2a 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -73,6 +73,7 @@ smm-$(CONFIG_UART_DEBUG) += uart_debug.c CPPFLAGS_common += -I$(src)/soc/intel/skylake CPPFLAGS_common += -I$(src)/soc/intel/skylake/include +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake # Currently used for microcode path. CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR) diff --git a/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h new file mode 100644 index 0000000..e0a82df --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h @@ -0,0 +1,507 @@ +/** @file + +Copyright (c) 2015, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPDVPD_H__ +#define __FSPUPDVPD_H__ + +#pragma pack(1) + + +#define MAX_CHANNELS_NUM 2 +#define MAX_DIMMS_NUM 2 + +typedef struct { + UINT32 VendorDeviceId; + UINT16 SubSystemId; + UINT8 RevisionId; /// 0xFF applies to all steppings + UINT8 FrontPanelSupport; + UINT16 NumberOfRearJacks; + UINT16 NumberOfFrontJacks; +} BL_PCH_AZALIA_VERB_TABLE_HEADER; + +typedef struct { + BL_PCH_AZALIA_VERB_TABLE_HEADER VerbTableHeader; + UINT32 *VerbTableData; +} BL_PCH_AZALIA_VERB_TABLE; + +typedef struct { + UINT8 Pme : 1; /// 0: Disable; 1: Enable + UINT8 DS : 1; /// 0: Docking is not supported; 1:Docking is supported + UINT8 DA : 1; /// 0: Docking is not attached; 1:Docking is attached + UINT8 HdmiCodec : 1; /// 0: Disable; 1: Enable + UINT8 AzaliaVCi : 1; /// 0: Disable; 1: Enable + UINT8 Rsvdbits : 3; + UINT8 AzaliaVerbTableNum; /// Number of verb tables provided by platform + BL_PCH_AZALIA_VERB_TABLE *AzaliaVerbTable; /// Pointer to the actual verb table(s) + UINT16 ResetWaitTimer; /// The delay timer after Azalia reset, the value is number of microseconds +} BL_PCH_AZALIA_CONFIG; + +typedef struct { + UINT32 Confg; + UINT32 ConfgChanges; + UINT32 Misc; + UINT32 MmioAddr; + CHAR16 *Name; +} BL_GPIO_FAMILY_INIT; + +typedef struct { + UINT32 Confg0; + UINT32 Confg0Changes; + UINT32 Confg1; + UINT32 Confg1Changes; + UINT32 Community; + UINT32 MmioAddr; + CHAR16 *Name; + UINT32 Misc; +} BL_GPIO_PAD_INIT; + +typedef struct { + UINT8 DimmId; + UINT32 SizeInMb; + UINT16 MfgId; + /** Module part number for DRR3 is 18 bytes + but DRR4 is 20 bytes as per JEDEC Spec, so + reserving 20 bytes **/ + UINT8 ModulePartNum[20]; +} DIMM_INFO; + +typedef struct { + UINT8 ChannelId; + UINT8 DimmCount; + DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; +} CHANNEL_INFO; + +typedef struct { + UINT8 Revision; + UINT8 DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; + UINT16 MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + UINT8 ChannelCount; + CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; +} FSP_SMBIOS_MEMORY_INFO; + + + +typedef struct { +/** Offset 0x0020 +**/ + UINT64 Signature; +/** Offset 0x0028 +**/ + UINT8 Revision; +/** Offset 0x0029 +**/ + UINT8 UnusedUpdSpace2[7]; +/** Offset 0x0030 + Tseg Size + Size of SMRAM memory reserved. +**/ + UINT16 PcdMrcInitTsegSize; +/** Offset 0x0032 + MMIO Size + Size of memory address space reserved for MMIO (Memory Mapped I/O). +**/ + UINT16 PcdMrcInitMmioSize; +/** Offset 0x0034 + DIMM 0 SPD SMBus Address + SPD Address of DIMM. +**/ + UINT8 PcdMrcInitSpdAddr1; +/** Offset 0x0035 + DIMM 1 SPD SMBus Address + SPD Address of DIMM. +**/ + UINT8 PcdMrcInitSpdAddr2; +/** Offset 0x0036 +**/ + UINT8 PcdMemChannel0Config; +/** Offset 0x0037 +**/ + UINT8 PcdMemChannel1Config; +/** Offset 0x0038 +**/ + UINT32 PcdMemorySpdPtr; +/** Offset 0x003C + Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics +**/ + UINT8 PcdIgdDvmt50PreAlloc; +/** Offset 0x003D + Aperture Size + Select the Aperture Size. +**/ + UINT8 PcdApertureSize; +/** Offset 0x003E + GTT Size + Select the GTT Size. +**/ + UINT8 PcdGttSize; +/** Offset 0x003F + Enable Legacy E/F segments decoding to ROM + If disabled, E0000h-FFFFFh decoding will be routed to DRAM. +**/ + UINT8 PcdLegacySegDecode; +/** Offset 0x0040 + Enable DVFS + Enable/disable DVFS. +**/ + UINT8 PcdDvfsEnable; +/** Offset 0x0041 + MemoryType + To Configure Memory Type +**/ + UINT8 PcdMemoryTypeEnable; +/** Offset 0x0042 +**/ + UINT8 ReservedMemoryInitUpd[190]; +} MEMORY_INIT_UPD; + +typedef struct { +/** Offset 0x0100 +**/ + UINT64 Signature; +/** Offset 0x0108 +**/ + UINT8 Revision; +/** Offset 0x0109 +**/ + UINT8 UnusedUpdSpace3[7]; +/** Offset 0x0110 + SD Card Mode + SD Card Mode +**/ + UINT8 PcdSdcardMode; +/** Offset 0x0111 + Enable HSUART0 + Enable/disable HSUART0. +**/ + UINT8 PcdEnableHsuart0; +/** Offset 0x0112 + Enable HSUART1 + Enable/disable HSUART1. +**/ + UINT8 PcdEnableHsuart1; +/** Offset 0x0113 + Enable Azalia + Enable/disable Azalia controller. +**/ + UINT8 PcdEnableAzalia; +/** Offset 0x0114 +**/ + BL_PCH_AZALIA_CONFIG *AzaliaConfigPtr; +/** Offset 0x0118 + Enable SATA + Enable/disable SATA controller. +**/ + UINT8 PcdEnableSata; +/** Offset 0x0119 + Enable XHCI + Enable/disable XHCI controller. +**/ + UINT8 PcdEnableXhci; +/** Offset 0x011A + Enable LPE + Choose LPE Mode. +**/ + UINT8 PcdEnableLpe; +/** Offset 0x011B + Enable DMA0 + Enable/disable DMA0. +**/ + UINT8 PcdEnableDma0; +/** Offset 0x011C + Enable DMA1 + Enable/disable DMA1. +**/ + UINT8 PcdEnableDma1; +/** Offset 0x011D + Enable I2C0 + Enable/disable I2C0. +**/ + UINT8 PcdEnableI2C0; +/** Offset 0x011E + Enable I2C1 + Enable/disable I2C1. +**/ + UINT8 PcdEnableI2C1; +/** Offset 0x011F + Enable I2C2 + Enable/disable I2C2. +**/ + UINT8 PcdEnableI2C2; +/** Offset 0x0120 + Enable I2C3 + Enable/disable I2C3. +**/ + UINT8 PcdEnableI2C3; +/** Offset 0x0121 + Enable I2C4 + Enable/disable I2C4. +**/ + UINT8 PcdEnableI2C4; +/** Offset 0x0122 + Enable I2C5 + Enable/disable I2C5. +**/ + UINT8 PcdEnableI2C5; +/** Offset 0x0123 + Enable I2C6 + Enable/disable I2C6. +**/ + UINT8 PcdEnableI2C6; +/** Offset 0x0124 +**/ + UINT32 GraphicsConfigPtr; +/** Offset 0x0128 +**/ + BL_GPIO_FAMILY_INIT *GpioFamilyInitTablePtr; +/** Offset 0x012C +**/ + BL_GPIO_PAD_INIT *GpioPadInitTablePtr; +/** Offset 0x0130 +**/ + UINT8 PunitPwrConfigDisable; +/** Offset 0x0131 +**/ + UINT8 ChvSvidConfig; +/** Offset 0x0132 +**/ + UINT8 DptfDisable; +/** Offset 0x0133 + eMMC Mode + EMMC Mode +**/ + UINT8 PcdEmmcMode; +/** Offset 0x0134 +**/ + UINT8 PcdUsb3ClkSsc; +/** Offset 0x0135 +**/ + UINT8 PcdDispClkSsc; +/** Offset 0x0136 +**/ + UINT8 PcdSataClkSsc; +/** Offset 0x0137 +**/ + UINT8 Usb2Port0PerPortPeTxiSet; +/** Offset 0x0138 +**/ + UINT8 Usb2Port0PerPortTxiSet; +/** Offset 0x0139 +**/ + UINT8 Usb2Port0IUsbTxEmphasisEn; +/** Offset 0x013A +**/ + UINT8 Usb2Port0PerPortTxPeHalf; +/** Offset 0x013B +**/ + UINT8 Usb2Port1PerPortPeTxiSet; +/** Offset 0x013C +**/ + UINT8 Usb2Port1PerPortTxiSet; +/** Offset 0x013D +**/ + UINT8 Usb2Port1IUsbTxEmphasisEn; +/** Offset 0x013E +**/ + UINT8 Usb2Port1PerPortTxPeHalf; +/** Offset 0x013F +**/ + UINT8 Usb2Port2PerPortPeTxiSet; +/** Offset 0x0140 +**/ + UINT8 Usb2Port2PerPortTxiSet; +/** Offset 0x0141 +**/ + UINT8 Usb2Port2IUsbTxEmphasisEn; +/** Offset 0x0142 +**/ + UINT8 Usb2Port2PerPortTxPeHalf; +/** Offset 0x0143 +**/ + UINT8 Usb2Port3PerPortPeTxiSet; +/** Offset 0x0144 +**/ + UINT8 Usb2Port3PerPortTxiSet; +/** Offset 0x0145 +**/ + UINT8 Usb2Port3IUsbTxEmphasisEn; +/** Offset 0x0146 +**/ + UINT8 Usb2Port3PerPortTxPeHalf; +/** Offset 0x0147 +**/ + UINT8 Usb2Port4PerPortPeTxiSet; +/** Offset 0x0148 +**/ + UINT8 Usb2Port4PerPortTxiSet; +/** Offset 0x0149 +**/ + UINT8 Usb2Port4IUsbTxEmphasisEn; +/** Offset 0x014A +**/ + UINT8 Usb2Port4PerPortTxPeHalf; +/** Offset 0x014B +**/ + UINT8 Usb3Lane0Ow2tapgen2deemph3p5; +/** Offset 0x014C +**/ + UINT8 Usb3Lane1Ow2tapgen2deemph3p5; +/** Offset 0x014D +**/ + UINT8 Usb3Lane2Ow2tapgen2deemph3p5; +/** Offset 0x014E +**/ + UINT8 Usb3Lane3Ow2tapgen2deemph3p5; +/** Offset 0x014F + SATA Interface Speed + Select SATA controller Interface Speed. +**/ + UINT8 PcdSataInterfaceSpeed; +/** Offset 0x0150 +**/ + UINT8 PcdPchUsbSsicPort; +/** Offset 0x0151 +**/ + UINT8 PcdPchUsbHsicPort; +/** Offset 0x0152 +**/ + UINT8 PcdPcieRootPortSpeed; +/** Offset 0x0153 +**/ + UINT8 PcdPchSsicEnable; +/** Offset 0x0154 +**/ + UINT32 PcdLogoPtr; +/** Offset 0x0158 +**/ + UINT32 PcdLogoSize; +/** Offset 0x015C +**/ + UINT8 PcdRtcLock; +/** Offset 0x015D + PMIC I2c Bus Number + I2c Bus Number to communicate with PMIC +**/ + UINT8 PMIC_I2CBus; +/** Offset 0x015E + Enable ISP + Enable/disable ISP. +**/ + UINT8 ISPEnable; +/** Offset 0x015F + Select ISP Device Number + Select ISP PCI Device Configuration +**/ + UINT8 ISPPciDevConfig; +/** Offset 0x0160 + Processor Turbo Mode + Enable/disable Processor Turbo Mode. +**/ + UINT8 PcdTurboMode; +/** Offset 0x0161 +**/ + UINT8 ReservedSiliconInitUpd[413]; +} SILICON_INIT_UPD; + +#define FSP_UPD_SIGNATURE 0x2444505557534224 /* '$BSWUPD$' */ +#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ +#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ + +typedef struct _UPD_DATA_REGION { +/** Offset 0x0000 +**/ + UINT64 Signature; +/** Offset 0x0008 +**/ + UINT8 Revision; +/** Offset 0x0009 +**/ + UINT8 UnusedUpdSpace0[7]; +/** Offset 0x0010 +**/ + UINT32 MemoryInitUpdOffset; +/** Offset 0x0014 +**/ + UINT32 SiliconInitUpdOffset; +/** Offset 0x0018 +**/ + UINT64 UnusedUpdSpace1; +/** Offset 0x0020 +**/ + MEMORY_INIT_UPD MemoryInitUpd; +/** Offset 0x0100 +**/ + SILICON_INIT_UPD SiliconInitUpd; +/** Offset 0x02FE +**/ + UINT16 PcdRegionTerminator; +/** Offset 0x0300 +**/ + UINT8 UnusedUpdSpace4[2123]; +/** Offset 0x0B4B +**/ + UINT8 PcdPaddingSpace; +} UPD_DATA_REGION; + +#define FSP_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */ +#define FSP_IMAGE_REV 0x01010100 + +typedef struct _VPD_DATA_REGION { +/** Offset 0x0000 +**/ + UINT64 PcdVpdRegionSign; +/** Offset 0x0008 + PcdImageRevision +**/ + UINT32 PcdImageRevision; +/** Offset 0x000C +**/ + UINT32 PcdUpdRegionOffset; +/** Offset 0x0010 +**/ + UINT8 UnusedVpdSpace0[20]; +/** Offset 0x0024 +**/ + UINT8 PcdEnableSecureBoot; +} VPD_DATA_REGION; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h new file mode 100644 index 0000000..be1f2f8 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h @@ -0,0 +1,740 @@ +/** @file + +Copyright (c) 2015, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPDVPD_H__ +#define __FSPUPDVPD_H__ + +#pragma pack(push, 1) + + +#define MRC_MAX_RCOMP 3 +#define MRC_MAX_RCOMP_TARGETS 5 +#define MAX_CHANNELS_NUM 2 +#define MAX_DIMMS_NUM 2 + +typedef struct { + UINT16 RcompResistor[MRC_MAX_RCOMP]; ///< Offset 0: Reference RCOMP resistors on motherboard + UINT16 RcompTarget[MRC_MAX_RCOMP_TARGETS]; ///< Offset 6: RCOMP target values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv +} MEMORY_RCOMP; + + +typedef struct { + UINT32 VendorDeviceId; /* Vendor ID/Device ID */ + UINT16 SubSystemId; /* SubSystem ID */ + UINT8 RevisionId; /* Revision ID. 0xFF applies to all steppings */ + UINT8 FrontPanelSupport; /* Front panel support (1=yes, 2=no) */ + UINT16 NumberOfRearJacks; /* Number of Rear Jacks */ + UINT16 NumberOfFrontJacks; /* Number of Front Jacks */ +} SA_HDA_HEADER; + +typedef struct { + UINT16 VendorId; /* Codec Vendor ID */ + UINT16 DeviceId; /* Codec Device ID */ + UINT8 RevisionId; /* Revision ID of the codec. 0xFF matches any revision. */ + UINT8 SdiNo; /* SDI number, 0xFF matches any SDI. */ + UINT16 DataDwords; /* Number of data DWORDs pointed by the codec data buffer. */ + UINT32 Reserved; /* Reserved for future use. Must be set to 0. */ +} AZALIA_HEADER; + +typedef struct { + AZALIA_HEADER Header; /* AZALIA PCH header */ + UINT32 *Data; /* Pointer to the data buffer. Its length is specified in the header */ +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + +typedef struct { + UINT8 DimmId; + UINT32 SizeInMb; + UINT16 MfgId; + UINT8 ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */ +} DIMM_INFO; + +typedef struct { + UINT8 ChannelId; + UINT8 DimmCount; + DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; +} CHANNEL_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; + UINT16 MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + UINT8 ChannelCount; + CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; +} FSP_SMBIOS_MEMORY_INFO; + + + +/** UPD data structure for FspMemoryInitApi +**/ +typedef struct { + +/** Offset 0x0020 +**/ + UINT64 Signature; + +/** Offset 0x0028 - Revision + Revision version of the MemoryInitUpd Region +**/ + UINT8 Revision; + +/** Offset 0x0029 +**/ + UINT8 UnusedUpdSpace0[7]; + +/** Offset 0x0030 - Platform Reserved Memory Size + The minimum platform memory size required to pass control into DXE + 0x400000 : 0x400000 +**/ + UINT64 PlatformMemorySize; + +/** Offset 0x0038 - Memory SPD Pointer Channel 0 Dimm 0 + Pointer to SPD data in Memory. Default: 0 for empty channel +**/ + UINT32 MemorySpdPtr00; + +/** Offset 0x003C - Memory SPD Pointer Channel 0 Dimm 1 + Pointer to SPD data in Memory. Default: 0 for empty channel +**/ + UINT32 MemorySpdPtr01; + +/** Offset 0x0040 - Memory SPD Pointer Channel 1 Dimm 0 + Pointer to SPD data in Memory. Default: 0 for empty channel +**/ + UINT32 MemorySpdPtr10; + +/** Offset 0x0044 - Memory SPD Pointer Channel 1 Dimm 1 + Pointer to SPD data in Memory. Default: 0 for empty channel +**/ + UINT32 MemorySpdPtr11; + +/** Offset 0x0048 - SPD Data Length + Length of SPD Data + 0x100:256 Bytes, 0x200:512 Bytes +**/ + UINT16 MemorySpdDataLen; + +/** Offset 0x004A - Dq Byte Map CH0 + Dq byte mapping between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqByteMapCh0[12]; + +/** Offset 0x0056 - Dq Byte Map CH1 + Dq byte mapping between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqByteMapCh1[12]; + +/** Offset 0x0062 - Dqs Map CPU to DRAM CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramCh0[8]; + +/** Offset 0x006A - Dqs Map CPU to DRAM CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramCh1[8]; + +/** Offset 0x0072 - RcompResister settings + Indicates RcompReister settings: Board-dependent +**/ + UINT16 RcompResistor[3]; + +/** Offset 0x0078 - RcompTarget settings + RcompTarget settings: board-dependent +**/ + UINT16 RcompTarget[5]; + +/** Offset 0x0082 - Dqs Pins Interleaved Setting + Indicates DqPinsInterleaved setting: board-dependent + $EN_DIS +**/ + UINT8 DqPinsInterleaved; + +/** Offset 0x0083 - VREF_CA + CA Vref routing: board-dependent + 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, 2:VREF_CA to CH_A and VREF_DQ_B to CH_B +**/ + UINT8 CaVrefConfig; + +/** Offset 0x0084 - Smram Mask + The SMM Regions AB-SEG and/or H-SEG reserved + 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both +**/ + UINT8 SmramMask; + +/** Offset 0x0085 - MRC Fast Boot + Enables/Disable the MRC fast path thru the MRC + $EN_DIS +**/ + UINT8 MrcFastBoot; + +/** Offset 0x0086 +**/ + UINT16 UnusedUpdSpace1; + +/** Offset 0x0088 - Intel Enhanced Debug + Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied + 0 : Disable, 0x400000 : Enable +**/ + UINT32 IedSize; + +/** Offset 0x008C - Tseg Size + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build + 0x0400000:4MB, 0x01000000:16MB +**/ + UINT32 TsegSize; + +/** Offset 0x0090 - MMIO Size + Size of memory address space reserved for MMIO (Memory Mapped I/O) in MB. + 0x0600 : 0x0600 +**/ + UINT16 MmioSize; + +/** Offset 0x0092 - Probeless Trace + Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. This also requires IED to be enabled. + $EN_DIS +**/ + UINT8 ProbelessTrace; + +/** Offset 0x0093 - Enable LAN + Enable/disable LAN controller. + $EN_DIS +**/ + UINT8 EnableLan; + +/** Offset 0x0094 +**/ + UINT16 UnusedUpdSpace2; + +/** Offset 0x0096 - Enable Trace Hub + Enable/disable Trace Hub function. + $EN_DIS +**/ + UINT8 EnableTraceHub; + +/** Offset 0x0097 - Enable PCIE RP + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + UINT8 PcieRpEnable[20]; + +/** Offset 0x00AB - Enable PCIE RP CLKREQ Support + Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + UINT8 PcieRpClkReqSupport[20]; + +/** Offset 0x00BF - Configure CLKREQ Number + Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + UINT8 PcieRpClkReqNumber[20]; + +/** Offset 0x00D3 - Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics. + 0x00:0 MB, 0x01:32 MB, 0x02:64 MB, 0x03:128 MB, 0x04:256 MB, 0x05:512 MB +**/ + UINT8 IgdDvmt50PreAlloc; + +/** Offset 0x00D4 - Internal Graphics + Enable/disable internal graphics. + $EN_DIS +**/ + UINT8 InternalGfx; + +/** Offset 0x00D5 - Aperture Size + Select the Aperture Size. + 0:128 MB, 1:256 MB, 2:512 MB +**/ + UINT8 ApertureSize; + +/** Offset 0x00D6 - SA GV + System Agent dynamic frequency support and when enabled memory will be training at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, 2=FixedHigh, and 3=Enabled. + 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled +**/ + UINT8 SaGv; + +/** Offset 0x00D7 - Rank Margin Tool + Enable/disable Rank Margin Tool. + $EN_DIS +**/ + UINT8 RMT; + +/** Offset 0x00D8 - DDR Frequency Limit + Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, 2400 and 0 for Auto. + 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 0:Auto +**/ + UINT16 DdrFreqLimit; + +/** Offset 0x00DA - Board Type + MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server + 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server +**/ + UINT8 UserBd; + +/** Offset 0x00DB +**/ + UINT8 UnusedUpdSpace3[105]; + +/** Offset 0x0144 - MMA Test Content Pointer + Pointer to MMA Test Content in Memory +**/ + UINT32 MmaTestContentPtr; + +/** Offset 0x0148 - MMA Test Content Size + Size of MMA Test Content in Memory +**/ + UINT32 MmaTestContentSize; + +/** Offset 0x014C - MMA Test Config Pointer + Pointer to MMA Test Config in Memory +**/ + UINT32 MmaTestConfigPtr; + +/** Offset 0x0150 - MMA Test Config Size + Size of MMA Test Config in Memory +**/ + UINT32 MmaTestConfigSize; + +/** Offset 0x0154 - Enable CIO2 Controller + Enable/disable SKYCAM CIO2 Controller. + $EN_DIS +**/ + UINT8 Cio2Enable; + +/** Offset 0x0155 +**/ + UINT8 ReservedMemoryInitUpd[171]; +} MEMORY_INIT_UPD; + +/** UPD data structure for FspSiliconInitApi +**/ +typedef struct { + +/** Offset 0x0200 +**/ + UINT64 Signature; + +/** Offset 0x0208 - Revision + Revision version of the SiliconInitUpd Region +**/ + UINT8 Revision; + +/** Offset 0x0209 +**/ + UINT8 UnusedUpdSpace4[7]; + +/** Offset 0x0210 - Logo Pointer + Points to PEI Display Logo Image + 0 : 0 +**/ + UINT32 LogoPtr; + +/** Offset 0x0214 - Logo Size + Size of PEI Display Logo Image + 0 : 0 +**/ + UINT32 LogoSize; + +/** Offset 0x0218 - Graphics Configuration Ptr + Points to VBT + 0 : 0 +**/ + UINT32 GraphicsConfigPtr; + +/** Offset 0x021C - Enable Device 4 + Enable/disable Device 4 + $EN_DIS +**/ + UINT8 Device4Enable; + +/** Offset 0x021D - Enable Azalia + Enable/disable Azalia controller. + $EN_DIS +**/ + UINT8 EnableAzalia; + +/** Offset 0x021E - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + UINT8 DspEnable; + +/** Offset 0x021F - Select HDAudio IoBuffer Ownership + Indicates the ownership of the I/O buffer between Intel HD Audio link vs I2S0 / I2S port. 0: Intel HD-Audio link owns all the I/O buffers. 1: Intel HD-Audio link owns 4 of the I/O buffers for 1 HD-Audio codec connection, and I2S1 port owns 4 of the I/O buffers for 1 I2S codec connection. 2: Reserved. 3: I2S0 and I2S1 ports own all the I/O buffers. + 0:HD-A Link, 1:Shared HD-A Link and I2S Port, 3:I2S Ports +**/ + UINT8 IoBufferOwnership; + +/** Offset 0x0220 +**/ + UINT8 UnusedUpdSpace5; + +/** Offset 0x0221 - Enable eMMC Controller + Enable/disable eMMC Controller. + $EN_DIS +**/ + UINT8 ScsEmmcEnabled; + +/** Offset 0x0222 - Enable eMMC HS400 Mode + Enable eMMC HS400 Mode. + $EN_DIS +**/ + UINT8 ScsEmmcHs400Enabled; + +/** Offset 0x0223 - Enable SdCard Controller + Enable/disable SD Card Controller. + $EN_DIS +**/ + UINT8 ScsSdCardEnabled; + +/** Offset 0x0224 - Enable ISH Controller + Enable/disable ISH Controller. + $EN_DIS +**/ + UINT8 IshEnable; + +/** Offset 0x0225 - Show SPI controller + Enable/disable to show SPI controller. + $EN_DIS +**/ + UINT8 ShowSpiController; + +/** Offset 0x0226 - HSIO HECI Messaging + Enable/Disable. 0: Disable, prevent the HSIO version check and HSIO init messages from being sent, 1: enable + $EN_DIS +**/ + UINT8 HsioMessaging; + +/** Offset 0x0227 - HECI3 state + The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 Heci3Enabled; + +/** Offset 0x0228 - MicrocodeRegionBase + Memory Base of Microcode Updates +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x022C - MicrocodeRegionSize + Size of Microcode Updates +**/ + UINT32 MicrocodeRegionSize; + +/** Offset 0x0230 - Turbo Mode + Enable/Disable Turbo mode. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 TurboMode; + +/** Offset 0x0231 - Enable SATA SALP Support + Enable/disable SATA Aggressive Link Power Management. + $EN_DIS +**/ + UINT8 SataSalpSupport; + +/** Offset 0x0232 - Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsEnable[8]; + +/** Offset 0x023A - Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlp[8]; + +/** Offset 0x0242 - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 PortUsb20Enable[16]; + +/** Offset 0x0252 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 PortUsb30Enable[10]; + +/** Offset 0x025C - Enable xDCI controller + Enable/disable to xDCI controller. + $EN_DIS +**/ + UINT8 XdciEnable; + +/** Offset 0x025D - Enable XHCI SSIC Eanble + Enable/disable XHCI SSIC port. + $EN_DIS +**/ + UINT8 SsicPortEnable; + +/** Offset 0x025E - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + UINT8 SmbusEnable; + +/** Offset 0x025F - Enable SerialIo Device Mode + 0:Disabled, 1:ACPI Mode, 2:PCI Mode, 3:Hidden mode, 4:Legacy UART mode - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,UART0,UART1,UART2 device mode respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. +**/ + UINT8 SerialIoDevMode[11]; + +/** Offset 0x026A - Address of PCH_DEVICE_INTERRUPT_CONFIG table. + The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. +**/ + UINT32 DevIntConfigPtr; + +/** Offset 0x026E - Number of DevIntConfig Entry + Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL. +**/ + UINT8 NumOfDevIntConfig; + +/** Offset 0x026F - PIRQx to IRQx Map Config + PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode. +**/ + UINT8 PxRcConfig[8]; + +/** Offset 0x0277 - Select GPIO IRQ Route + GPIO IRQ Select. The valid value is 14 or 15. + 0 : 0xFF +**/ + UINT8 GpioIrqRoute; + +/** Offset 0x0278 - Select SciIrqSelect + SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. + 0 : 0xFF +**/ + UINT8 SciIrqSelect; + +/** Offset 0x0279 - Select TcoIrqSelect + TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. + 0 : 0xFF +**/ + UINT8 TcoIrqSelect; + +/** Offset 0x027A - Enable/Disable Tco IRQ + Enable/disable TCO IRQ + $EN_DIS +**/ + UINT8 TcoIrqEnable; + +/** Offset 0x027B - AzaliaVerbTableNumEntries + Number of Entries in Azalia Verb Table +**/ + UINT8 AzaliaVerbTableNumEntries; + +/** Offset 0x027C - AzaliaVerbTablePtr + Pointer to Array of pointers to Codec Table. +**/ + UINT32 AzaliaVerbTablePtr; + +/** Offset 0x0280 - RTC CMOS RAM LOCK + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. + $EN_DIS +**/ + UINT8 RtcLock; + +/** Offset 0x0281 - Enable SATA + Enable/disable SATA controller. + $EN_DIS +**/ + UINT8 EnableSata; + +/** Offset 0x0282 - SATA Mode + Select SATA controller working mode. + 0:AHCI, 1:RAID +**/ + UINT8 SataMode; + +/** Offset 0x0283 - USB Per Port HS Preemphasis Bias + USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. +**/ + UINT8 Usb2AfePetxiset[16]; + +/** Offset 0x0293 - USB Per Port HS Transmitter Bias + USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. +**/ + UINT8 Usb2AfeTxiset[16]; + +/** Offset 0x02A3 - USB Per Port HS Transmitter Emphasis + USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. +**/ + UINT8 Usb2AfePredeemp[16]; + +/** Offset 0x02B3 - USB Per Port Half Bit Pre-emphasis + USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port. +**/ + UINT8 Usb2AfePehalfbit[16]; + +/** Offset 0x02C3 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment + Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmphEnable[10]; + +/** Offset 0x02CD - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmph[10]; + +/** Offset 0x02D7 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment + Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmpEnable[10]; + +/** Offset 0x02E1 - USB 3.0 TX Output Downscale Amplitude Adjustment + USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmp[10]; + +/** Offset 0x02EB +**/ + UINT8 ReservedSiliconInitUpd[271]; +} SILICON_INIT_UPD; + +#define FSP_UPD_SIGNATURE 0x244450554C4B5324 /* '$SKLUPD$' */ +#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ +#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ + +/** UPD data structure. The UPD_DATA_REGION may contain some reserved or unused fields in the data structure. These fields are required to use the default values provided in the FSP binary. Intel always recommends copying the whole UPD_DATA_REGION from the flash to a local structure in the stack before overriding any field. +**/ +typedef struct { + +/** Offset 0x0000 +**/ + UINT64 Signature; + +/** Offset 0x0008 - This field is not an option and is a Revision of the UPD_DATA_REGION. It can be used by the boot loader to validate the UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package. + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build +**/ + UINT8 Revision; + +/** Offset 0x0009 +**/ + UINT8 ReservedUpd0[7]; + +/** Offset 0x0010 - MemoryInitUpdOffset + This field contains the offset of the MemoryInitUpd structure relative to UPD_DATA_REGION +**/ + UINT32 MemoryInitUpdOffset; + +/** Offset 0x0014 - SiliconInitUpdOffset + This field contains the offset of the SiliconInitUpd structure relative to UPD_DATA_REGION +**/ + UINT32 SiliconInitUpdOffset; + +/** Offset 0x0018 +**/ + UINT64 ReservedUpd1; + +/** Offset 0x0020 +**/ + MEMORY_INIT_UPD MemoryInitUpd; + +/** Offset 0x0200 +**/ + SILICON_INIT_UPD SiliconInitUpd; + +/** Offset 0x03FA - RegionTerminator + This field is not an option and is a termination field at the end of the data structure. This field is will have a value 0x55AA indicating the end of UPD data.The boot loader should never override this field. +**/ + UINT16 RegionTerminator; +} UPD_DATA_REGION; + +#define FSP_IMAGE_ID 0x245053464C4B5324 /* '$SKLFSP$' */ +#define FSP_IMAGE_REV 0x01070000 + +/** VPD data structure +**/ +typedef struct { + +/** Offset 0x0000 +**/ + UINT64 PcdVpdRegionSign; + +/** Offset 0x0008 - PcdImageRevision + This field is not an option and is a revision ID for the FSP release. It can be used by the boot loader to validate the VPD/UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION/VPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package. This should match the ImageRevision in FSP_INFO_HEADER. +**/ + UINT32 PcdImageRevision; + +/** Offset 0x000C - PcdUpdRegionOffset + This field is not an option and contains the offset of the UPD data region within the FSP release image. The boot loader can use it to find the location of UPD_DATA_REGION. +**/ + UINT32 PcdUpdRegionOffset; + +/** Offset 0x0010 +**/ + UINT8 UnusedVpdSpace0[32]; + +/** Offset 0x0030 - PcdSerialIoUartDebugEnable + Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. + 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing +**/ + UINT8 PcdSerialIoUartDebugEnable; + +/** Offset 0x0031 - PcdSerialIoUartNumber + Select SerialIo Uart Controller for debug. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 PcdSerialIoUartNumber; + +/** Offset 0x0032 +**/ + UINT32 PcdSerialIoUartInputClock; +} VPD_DATA_REGION; + +#pragma pack(pop) + +#endif

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Patch merged into coreboot/master: nb/intel/sandybridge/raminit: Factor out code into toggle_io_reset
by gerrit＠coreboot.org 19 Nov '15

19 Nov '15

the following patch was just integrated into master: commit 9b51568897ff476ed770f455a54745551d5e5614 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Oct 9 13:43:51 2015 +0200 nb/intel/sandybridge/raminit: Factor out code into toggle_io_reset Found while doing code review. Use a function to toggle IO reset signal. Change-Id: I4cb0885ed9be763fbc4069e4d015a36a7183c823 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: http://review.coreboot.org/11916 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr(a)das-labor.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> See http://review.coreboot.org/11916 for details. -gerrit

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Patch merged into coreboot/master: vendorcode/google/chromeos: Cache VPD data into CBMEM
by gerrit＠coreboot.org 19 Nov '15

19 Nov '15

the following patch was just integrated into master: commit b15a0d0a6fdd4cce7f6e22570642d863391fc5c6 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Jul 13 15:49:57 2015 +0800 vendorcode/google/chromeos: Cache VPD data into CBMEM There are few drawbacks reading VPD from SPI flash in user land, including "lack of firmware level authority" and "slow reading speed". Since for many platforms we are already reading VPD in firmware (for example MAC and serial number), caching the VPD data in CBMEM should will speed up and simplify user land VPD processing without adding performance cost. A new CBMEM ID is added: CBMEM_ID_VPD, referring to a structure containing raw Google VPD 2.0 structure and can be found by the new LB_TAG_VPD in Coreboot tables. BRANCH=smaug BUG=chrome-os-partner:39945 TEST=emerge-smaug coreboot chromeos-bootimage # and boots successfully. [pg: lots of changes to make it work with what happened in upstream since 2013] Change-Id: If8629ac002d52abed7b480d3d06298665613edbf Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 117a9e88912860a22d250ff0e53a7d40237ddd45 Original-Change-Id: Ic79f424a6e3edfb6c5d168b9661d61a56fab295f Original-Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285031 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/12453 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/12453 for details. -gerrit

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Patch merged into coreboot/master: edid: Use a better mode for 640x480
by gerrit＠coreboot.org 19 Nov '15

19 Nov '15

the following patch was just integrated into master: commit 78e226cf36af511bd435d4f6b3f9163fbc8322a0 Author: Douglas Anderson <dianders(a)chromium.org> Date: Wed Oct 28 09:52:22 2015 -0700 edid: Use a better mode for 640x480 The hardcoded clock value for 640x480 was 25.175 MHz. That's a valid clock to use, but is quite hard to make a non-jittery clock from PLLs. It's much easier to make 25.200 MHz, so let's do that. The difference between the two modes is 59.9 Hz vs. 60 Hz and it seems better to make a non-jittery 60 Hz rather than a very jittery 59.9 Hz. BRANCH=none BUG=chrome-os-partner:46256 TEST=Insignia monitor works, so do others Change-Id: I8aa124d04a90f5dcf9cfa923ed3b693fbb4a06d8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e32ce13462101dc60cfed60b6948b7597e93525a Original-Change-Id: Ia9804afe8011a915e4bec306e863d34ad7e27be5 Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309540 Original-Reviewed-by: Stphane Marchesin <marcheu(a)chromium.org> Original-(cherry picked from commit 7f32c9f460991e5e3b947117d6ae4080e630a532) Original-Reviewed-on: https://chromium-review.googlesource.com/309576 Original-Commit-Ready: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/12443 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12443 for details. -gerrit

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Patch merged into coreboot/master: edid: Don't half parse (and wrongly print) more detailed timings
by gerrit＠coreboot.org 19 Nov '15

19 Nov '15

the following patch was just integrated into master: commit bca67fb7dc02a6342f6a19738bfd25da21369057 Author: Douglas Anderson <dianders(a)chromium.org> Date: Wed Oct 28 09:18:28 2015 -0700 edid: Don't half parse (and wrongly print) more detailed timings The EDID parsing code continued to update _some_ fields of the output edid but not others if "did_detailed_timing" was already set. It also then went on to print out this halfway mix of modes each time, despite the fact that it didn't really update everything. Let's fix that. We'll reduce code changes by using a temporary copy of data in detailed_block() and then we'll copy it back if we decide we should update. BRANCH=none BUG=chrome-os-partner:46998 TEST=No more bogus printouts Change-Id: Idbfa233e0997244c22ef21c892c4473a91621821 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4d69999cdd7ce3cd2c9332ab3f22ea8eb4b6f2e9 Original-Change-Id: Ia72cac7fda2772f26477e43237678fa30feca584 Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309541 Original-Reviewed-on: https://chromium-review.googlesource.com/309609 Original-Commit-Ready: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/12444 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12444 for details. -gerrit

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Patch merged into coreboot/master: edid: Don't set standard timings as supported if they're not
by gerrit＠coreboot.org 19 Nov '15

19 Nov '15

the following patch was just integrated into master: commit 9fa0760e9769af20fbb7b30ab3dda7ba7885c7da Author: Douglas Anderson <dianders(a)chromium.org> Date: Wed Oct 28 10:19:52 2015 -0700 edid: Don't set standard timings as supported if they're not The set to say that a standard timing was supported was not properly in the "if" test. That meant that even when standard timings weren't supported, we thought that they were. That had the side effect of never using the detailed mode. BRANCH=none BUG=chrome-os-partner:46998 TEST=Adafruit panel works now Change-Id: Ide3ed6c5682840f808d854755dac58e9057e6bda Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c99d3ee8d163fc6be207c5a7df2a7aecd7af7849 Original-Change-Id: Ib67735219fd28516857d9b63f1ba156573f1bea3 Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309521 Original-(cherry picked from commit 4e4c2816e2239299bc02e3a57fb18056db62b56c) Original-Reviewed-on: https://chromium-review.googlesource.com/309552 Original-Commit-Ready: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/12442 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12442 for details. -gerrit

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Patch merged into coreboot/master: edid: Remove useless parameter from detailed_cvt_descriptor()
by gerrit＠coreboot.org 19 Nov '15

19 Nov '15

the following patch was just integrated into master: commit 14dd3701c30788e52d5e970798bb68e8f1ff23b2 Author: Douglas Anderson <dianders(a)chromium.org> Date: Wed Oct 28 11:19:57 2015 -0700 edid: Remove useless parameter from detailed_cvt_descriptor() The detailed_cvt_descriptor() function takes a parameter "out" for no good reason. Remove it. BRANCH=none BUG=chrome-os-partner:46998 TEST=Build and boot Change-Id: I1042dba9ddf2b4b543bd07615013088be5055950 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5c3474c9b1f9fb73f44d64d3a0592f92339da2df Original-Change-Id: I4d695a6dba6606d2132578ce0ab4cb612c83d0f4 Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309598 Original-(cherry picked from commit 39122e242e808d71a4e274e8a23e9a63f4984388) Original-Reviewed-on: https://chromium-review.googlesource.com/309496 Original-Commit-Ready: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/12441 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12441 for details. -gerrit

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coreboot-gerrit November 2015