coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

1 participants
1544 discussions

New patch to review for coreboot: cbfstool: Add EFI and MMA file types
by Patrick Georgi 19 Nov '15

19 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12480 -gerrit commit 4e55c421770750cdc5863c02685e82ac9356f6bb Author: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> Date: Wed Sep 2 13:46:30 2015 -0700 cbfstool: Add EFI and MMA file types Add efi and mma file types. BRANCH=none BUG=chrome-os-partner:43731 TEST=Build and Boot kunimitsu (FAB3). cbfstool shows mma and efi file types. Not tested on Glados CQ-DEPEND=CL:299476,CL:299474,CL:299473,CL:299509,CL:299508,CL:299507,CL:*230478,CL:*230479 Change-Id: I4f24a8426028428d613eb875c11cca70d9461dd6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3c625ad2aeca3a9358fba1eb7434c66ff991131a Original-Change-Id: I611819d213d87fbbb20816fdfb9e4b1401b3b89b Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/299475 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> --- util/cbfstool/cbfs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index 486e2db..4a2a1ed 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -168,6 +168,8 @@ struct cbfs_payload { #define CBFS_COMPONENT_MICROCODE 0x53 #define CBFS_COMPONENT_FSP 0x60 #define CBFS_COMPONENT_MRC 0x61 +#define CBFS_COMPONENT_MMA 0x62 +#define CBFS_COMPONENT_EFI 0x63 #define CBFS_COMPONENT_CMOS_DEFAULT 0xaa #define CBFS_COMPONENT_SPD 0xab #define CBFS_COMPONENT_MRC_CACHE 0xac @@ -207,6 +209,8 @@ static struct typedesc_t filetypes[] unused = { {CBFS_COMPONENT_CMOS_LAYOUT, "cmos_layout"}, {CBFS_COMPONENT_SPD, "spd"}, {CBFS_COMPONENT_MRC_CACHE, "mrc_cache"}, + {CBFS_COMPONENT_MMA, "mma"}, + {CBFS_COMPONENT_EFI, "efi"}, {CBFS_COMPONENT_DELETED, "deleted"}, {CBFS_COMPONENT_NULL, "null"} };

1 0

New patch to review for coreboot: console_init: Add ENV_SMM to the log
by Ben Gardner 19 Nov '15

19 Nov '15

Ben Gardner (gardner.ben(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12479 -gerrit commit 90c60ff969c9a2b6b66b151369b406464d303ec9 Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Thu Nov 19 09:50:05 2015 -0600 console_init: Add ENV_SMM to the log Looks better than UNKNOWN when SMM logging is turned on. Change-Id: I577ddf2de4ef249a1a4ce627bb55608731a9f5ed Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> --- src/console/init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/console/init.c b/src/console/init.c index 7e7c5ac..6590f60 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -53,6 +53,8 @@ void console_init(void) "ramstage" #elif ENV_VERSTAGE "verstage" +#elif ENV_SMM + "smm" #else "UNKNOWN" #endif

1 0

Patch merged into coreboot/master: crossgcc: Update makefile builds
by gerrit＠coreboot.org 19 Nov '15

19 Nov '15

the following patch was just integrated into master: commit 8fe681872b38c23a2a9172199d1e9c0edae12937 Author: Martin Roth <martinroth(a)google.com> Date: Tue Oct 27 15:03:46 2015 -0600 crossgcc: Update makefile builds - Only build IASL once for the 'all' targets instead of once for each. - Change the control of what gets built from different targets to variables on the build line. - Clean up and correct the list of phony targets - Don't keep the temporary files around while building all. This takes up a lot of space. If it's desired behavior, add BUILDGCC_OPTIONS=-t on the make command line. - Add comments about CPU= and BUILDGCC_OPTIONS= variables - Add KEEP_SOURCES option Change-Id: I7752974e249f25717b42be25a841c69af84d5c69 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: http://review.coreboot.org/12300 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/12300 for details. -gerrit

1 0

Patch set updated for coreboot: fsp1_0: Update Kconfig for symbols not depending on FSP binary
by Martin Roth 19 Nov '15

19 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12461 -gerrit commit 2dadcd120cdacff92c97ffbd0bff88c8a055016d Author: Martin Roth <martinroth(a)google.com> Date: Wed Nov 18 16:07:54 2015 -0700 fsp1_0: Update Kconfig for symbols not depending on FSP binary There were several symbols that were inside the 'if HAVE_FSP_BIN' that don't really depend on having the FSP binary. In theory, we should be able to build a coreboot rom and add the FSP binary later. This doesn't always work in practice, but this is a step in that direction. This also fixes a Kconfig warning for Rangeley. Change-Id: I327d8fe5231d7de25f2a74b8a193deb47e4c5ee1 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/drivers/intel/fsp1_0/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index 36bfa7c..28df90e 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -41,6 +41,8 @@ config FSP_FILE help The path and filename of the Intel FSP binary for this platform. +endif #HAVE_FSP_BIN + config FSP_LOC hex "Intel FSP Binary location in CBFS" help @@ -92,8 +94,6 @@ config VIRTUAL_ROM_SIZE the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM size is 16 MB. -endif #HAVE_FSP_BIN - config CACHE_ROM_SIZE_OVERRIDE hex "Cache ROM Size" default CBFS_SIZE

1 0

Patch set updated for coreboot: vendorcode/google/chromeos: Cache VPD data into CBMEM
by Patrick Georgi 19 Nov '15

19 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12453 -gerrit commit 30cc1435aa3114e3c7990dedd3b9b24b1aeb2fdf Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Jul 13 15:49:57 2015 +0800 vendorcode/google/chromeos: Cache VPD data into CBMEM There are few drawbacks reading VPD from SPI flash in user land, including "lack of firmware level authority" and "slow reading speed". Since for many platforms we are already reading VPD in firmware (for example MAC and serial number), caching the VPD data in CBMEM should will speed up and simplify user land VPD processing without adding performance cost. A new CBMEM ID is added: CBMEM_ID_VPD, referring to a structure containing raw Google VPD 2.0 structure and can be found by the new LB_TAG_VPD in Coreboot tables. BRANCH=smaug BUG=chrome-os-partner:39945 TEST=emerge-smaug coreboot chromeos-bootimage # and boots successfully. [pg: lots of changes to make it work with what happened in upstream since 2013] Change-Id: If8629ac002d52abed7b480d3d06298665613edbf Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 117a9e88912860a22d250ff0e53a7d40237ddd45 Original-Change-Id: Ic79f424a6e3edfb6c5d168b9661d61a56fab295f Original-Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285031 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/commonlib/include/commonlib/cbmem_id.h | 2 + src/commonlib/include/commonlib/coreboot_tables.h | 1 + src/lib/coreboot_table.c | 1 + src/vendorcode/google/chromeos/Makefile.inc | 2 +- src/vendorcode/google/chromeos/cros_vpd.c | 146 ++++++++++++++++------ 5 files changed, 112 insertions(+), 40 deletions(-) diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 580d5ea..44ab31e 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -62,6 +62,7 @@ #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 #define CBMEM_ID_VBOOT_SEL_REG 0x780074f1 #define CBMEM_ID_VBOOT_WORKBUF 0x78007343 +#define CBMEM_ID_VPD 0x56504420 #define CBMEM_ID_WIFI_CALIBRATION 0x57494649 #define CBMEM_ID_TO_NAME_TABLE \ @@ -105,5 +106,6 @@ { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \ { CBMEM_ID_VBOOT_SEL_REG, "VBOOT SEL " }, \ { CBMEM_ID_VBOOT_WORKBUF, "VBOOT WORK " }, \ + { CBMEM_ID_VPD, "VPD " }, \ { CBMEM_ID_WIFI_CALIBRATION, "WIFI CLBR " }, #endif /* _CBMEM_ID_H_ */ diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 5e0c87c..32c388b 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -245,6 +245,7 @@ void lb_ramoops(struct lb_header *header); #define LB_TAG_MRC_CACHE 0x0018 #define LB_TAG_ACPI_GNVS 0x0024 #define LB_TAG_WIFI_CALIBRATION 0x0027 +#define LB_TAG_VPD 0x002c struct lb_cbmem_ref { uint32_t tag; uint32_t size; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 258a4a5..2226f5e 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -285,6 +285,7 @@ static void add_cbmem_pointers(struct lb_header *header) {CBMEM_ID_TIMESTAMP, LB_TAG_TIMESTAMPS}, {CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE}, {CBMEM_ID_ACPI_GNVS, LB_TAG_ACPI_GNVS}, + {CBMEM_ID_VPD, LB_TAG_VPD}, {CBMEM_ID_WIFI_CALIBRATION, LB_TAG_WIFI_CALIBRATION} }; int i; diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 6f6f709..ef84798 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -36,7 +36,7 @@ ramstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c -romstage-y += vpd_decode.c cros_vpd.c +romstage-y += vpd_decode.c ramstage-y += vpd_decode.c cros_vpd.c vpd_mac.c vpd_serialno.c vpd_calibration.c ifeq ($(CONFIG_ARCH_X86)$(CONFIG_ARCH_MIPS),) bootblock-y += watchdog.c diff --git a/src/vendorcode/google/chromeos/cros_vpd.c b/src/vendorcode/google/chromeos/cros_vpd.c index f9aec88..8215454 100644 --- a/src/vendorcode/google/chromeos/cros_vpd.c +++ b/src/vendorcode/google/chromeos/cros_vpd.c @@ -6,6 +6,7 @@ #include <console/console.h> +#include <cbmem.h> #include <fmap.h> #include <stdlib.h> #include <string.h> @@ -17,6 +18,8 @@ /* Currently we only support Google VPD 2.0, which has a fixed offset. */ enum { GOOGLE_VPD_2_0_OFFSET = 0x600, + CROSVPD_CBMEM_MAGIC = 0x43524f53, + CROSVPD_CBMEM_VERSION = 0x0001, }; struct vpd_gets_arg { @@ -26,56 +29,121 @@ struct vpd_gets_arg { int matched; }; -static int cros_vpd_load(uint8_t **vpd_address, int32_t *vpd_size) +struct vpd_cbmem { + uint32_t magic; + uint32_t version; + uint32_t ro_size; + uint32_t rw_size; + uint8_t blob[0]; + /* The blob contains both RO and RW data. It starts with RO (0 .. + * ro_size) and then RW (ro_size .. ro_size+rw_size). + */ +}; + +/* returns the size of data in a VPD 2.0 formatted fmap region, or 0 */ +static int32_t get_vpd_size(const char *fmap_name, int32_t *base) { - MAYBE_STATIC int cached = 0; - MAYBE_STATIC uint8_t *cached_address = NULL; - MAYBE_STATIC int32_t cached_size = 0; - MAYBE_STATIC int result = -1; struct google_vpd_info info; - int32_t base; struct region_device vpd; + int32_t size; - if (cached) { - *vpd_address = cached_address; - *vpd_size = cached_size; - return result; - } - - cached = 1; - if (fmap_locate_area_as_rdev("RO_VPD", &vpd)) { - printk(BIOS_ERR, "%s: No RO_VPD FMAP section.\n", __func__); - return result; + if (fmap_locate_area_as_rdev(fmap_name, &vpd)) { + printk(BIOS_ERR, "%s: No %s FMAP section.\n", __func__, + fmap_name); + return 0; } - base = 0; - cached_size = region_device_sz(&vpd); + size = region_device_sz(&vpd); - if ((cached_size < GOOGLE_VPD_2_0_OFFSET + sizeof(info)) || + if ((size < GOOGLE_VPD_2_0_OFFSET + sizeof(info)) || rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET, - cached_size - GOOGLE_VPD_2_0_OFFSET)) { + size - GOOGLE_VPD_2_0_OFFSET)) { printk(BIOS_ERR, "%s: Too small (%d) for Google VPD 2.0.\n", - __func__, cached_size); - return result; + __func__, size); + return 0; } /* Try if we can find a google_vpd_info, otherwise read whole VPD. */ - if (rdev_readat(&vpd, &info, base, sizeof(info)) == sizeof(info) && + if (rdev_readat(&vpd, &info, *base, sizeof(info)) == sizeof(info) && memcmp(info.header.magic, VPD_INFO_MAGIC, sizeof(info.header.magic)) - == 0 && cached_size >= info.size + sizeof(info)) { - base += sizeof(info); - cached_size = info.size; + == 0 && size >= info.size + sizeof(info)) { + *base += sizeof(info); + size = info.size; + } else { + size -= GOOGLE_VPD_2_0_OFFSET; + } + + return size; +} + +static void cbmem_add_cros_vpd(int is_recovery) +{ + struct region_device vpd; + struct vpd_cbmem *cbmem; + int32_t ro_vpd_base = 0, rw_vpd_base = 0; + int32_t ro_vpd_size, rw_vpd_size; + + ro_vpd_size = get_vpd_size("RO_VPD", &ro_vpd_base); + rw_vpd_size = get_vpd_size("RW_VPD", &rw_vpd_base); + + /* no VPD at all? nothing to do then */ + if ((ro_vpd_size == 0) && (rw_vpd_size == 0)) + return; + + cbmem = cbmem_add(CBMEM_ID_VPD, sizeof(*cbmem) + ro_vpd_size + + rw_vpd_size); + if (!cbmem) { + printk(BIOS_ERR, "%s: Failed to allocate CBMEM (%u+%u).\n", + __func__, ro_vpd_size, rw_vpd_size); + return; } - cached_address = rdev_mmap(&vpd, base, cached_size); - if (cached_address) { - *vpd_address = cached_address; - *vpd_size = cached_size; - printk(BIOS_DEBUG, "%s: Got VPD: %#x+%#x\n", __func__, base, - cached_size); - result = 0; + cbmem->magic = CROSVPD_CBMEM_MAGIC; + cbmem->version = CROSVPD_CBMEM_VERSION; + cbmem->ro_size = 0; + cbmem->rw_size = 0; + + if (ro_vpd_size) { + if (fmap_locate_area_as_rdev("RO_VPD", &vpd)) { + /* shouldn't happen, but let's be extra defensive */ + printk(BIOS_ERR, "%s: No RO_VPD FMAP section.\n", + __func__); + return; + } + rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET, + region_device_sz(&vpd) - GOOGLE_VPD_2_0_OFFSET); + + + if (rdev_readat(&vpd, cbmem->blob, ro_vpd_base, ro_vpd_size) == + ro_vpd_size) { + cbmem->ro_size = ro_vpd_size; + } else { + printk(BIOS_ERR, + "%s: Reading RO_VPD FMAP section failed.\n", + __func__); + ro_vpd_size = 0; + } + } + + if (rw_vpd_size) { + if (fmap_locate_area_as_rdev("RW_VPD", &vpd)) { + /* shouldn't happen, but let's be extra defensive */ + printk(BIOS_ERR, "%s: No RW_VPD FMAP section.\n", + __func__); + return; + } + rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET, + region_device_sz(&vpd) - GOOGLE_VPD_2_0_OFFSET); + + if (rdev_readat(&vpd, cbmem->blob + ro_vpd_size, rw_vpd_base, + rw_vpd_size) == rw_vpd_size) { + cbmem->rw_size = rw_vpd_size; + } else { + printk(BIOS_ERR, + "%s: Reading RW_VPD FMAP section failed.\n", + __func__); + } } - return result; } static int vpd_gets_callback(const uint8_t *key, int32_t key_len, @@ -97,19 +165,18 @@ static int vpd_gets_callback(const uint8_t *key, int32_t key_len, const void *cros_vpd_find(const char *key, int *size) { - uint8_t *vpd_address = NULL; - int32_t vpd_size = 0; struct vpd_gets_arg arg = {0}; int consumed = 0; + const struct vpd_cbmem *vpd; - if (cros_vpd_load(&vpd_address, &vpd_size) != 0) { + vpd = cbmem_find(CBMEM_ID_VPD); + if (!vpd || !vpd->ro_size) return NULL; - } arg.key = (const uint8_t *)key; arg.key_len = strlen(key); - while (VPD_OK == decodeVpdString(vpd_size, vpd_address, &consumed, + while (VPD_OK == decodeVpdString(vpd->ro_size, vpd->blob, &consumed, vpd_gets_callback, &arg)) { /* Iterate until found or no more entries. */ } @@ -141,3 +208,4 @@ char *cros_vpd_gets(const char *key, char *buffer, int size) return buffer; } +RAMSTAGE_CBMEM_INIT_HOOK(cbmem_add_cros_vpd)

1 0

Patch merged into coreboot/master: lint: properly terminate junit report on error
by gerrit＠coreboot.org 19 Nov '15

19 Nov '15

the following patch was just integrated into master: commit a791fbb0fa585befa91d12fe685cf1f4da8e579f Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Nov 19 15:46:37 2015 +0100 lint: properly terminate junit report on error Otherwise </testsuite> is missing and jenkins can't make sense of things. Change-Id: If11a6d2506efc9d7c915f50896b2714bc66e3b65 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/12478 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12478 for details. -gerrit

1 0

Patch set updated for coreboot: vendorcode/google/chromeos: Cache VPD data into CBMEM
by Patrick Georgi 19 Nov '15

19 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12453 -gerrit commit c10419b9980a20c3279658ad257e762946a4ed4f Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Jul 13 15:49:57 2015 +0800 vendorcode/google/chromeos: Cache VPD data into CBMEM There are few drawbacks reading VPD from SPI flash in user land, including "lack of firmware level authority" and "slow reading speed". Since for many platforms we are already reading VPD in firmware (for example MAC and serial number), caching the VPD data in CBMEM should will speed up and simplify user land VPD processing without adding performance cost. A new CBMEM ID is added: CBMEM_ID_VPD, referring to a structure containing raw Google VPD 2.0 structure and can be found by the new LB_TAG_VPD in Coreboot tables. BRANCH=smaug BUG=chrome-os-partner:39945 TEST=emerge-smaug coreboot chromeos-bootimage # and boots successfully. [pg: lots of changes to make it work with what happened in upstream since 2013] Change-Id: If8629ac002d52abed7b480d3d06298665613edbf Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 117a9e88912860a22d250ff0e53a7d40237ddd45 Original-Change-Id: Ic79f424a6e3edfb6c5d168b9661d61a56fab295f Original-Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285031 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/commonlib/include/commonlib/cbmem_id.h | 2 + src/commonlib/include/commonlib/coreboot_tables.h | 1 + src/lib/coreboot_table.c | 1 + src/vendorcode/google/chromeos/cros_vpd.c | 146 ++++++++++++++++------ 4 files changed, 111 insertions(+), 39 deletions(-) diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 580d5ea..44ab31e 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -62,6 +62,7 @@ #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 #define CBMEM_ID_VBOOT_SEL_REG 0x780074f1 #define CBMEM_ID_VBOOT_WORKBUF 0x78007343 +#define CBMEM_ID_VPD 0x56504420 #define CBMEM_ID_WIFI_CALIBRATION 0x57494649 #define CBMEM_ID_TO_NAME_TABLE \ @@ -105,5 +106,6 @@ { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \ { CBMEM_ID_VBOOT_SEL_REG, "VBOOT SEL " }, \ { CBMEM_ID_VBOOT_WORKBUF, "VBOOT WORK " }, \ + { CBMEM_ID_VPD, "VPD " }, \ { CBMEM_ID_WIFI_CALIBRATION, "WIFI CLBR " }, #endif /* _CBMEM_ID_H_ */ diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 5e0c87c..32c388b 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -245,6 +245,7 @@ void lb_ramoops(struct lb_header *header); #define LB_TAG_MRC_CACHE 0x0018 #define LB_TAG_ACPI_GNVS 0x0024 #define LB_TAG_WIFI_CALIBRATION 0x0027 +#define LB_TAG_VPD 0x002c struct lb_cbmem_ref { uint32_t tag; uint32_t size; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 258a4a5..2226f5e 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -285,6 +285,7 @@ static void add_cbmem_pointers(struct lb_header *header) {CBMEM_ID_TIMESTAMP, LB_TAG_TIMESTAMPS}, {CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE}, {CBMEM_ID_ACPI_GNVS, LB_TAG_ACPI_GNVS}, + {CBMEM_ID_VPD, LB_TAG_VPD}, {CBMEM_ID_WIFI_CALIBRATION, LB_TAG_WIFI_CALIBRATION} }; int i; diff --git a/src/vendorcode/google/chromeos/cros_vpd.c b/src/vendorcode/google/chromeos/cros_vpd.c index f9aec88..72f1219 100644 --- a/src/vendorcode/google/chromeos/cros_vpd.c +++ b/src/vendorcode/google/chromeos/cros_vpd.c @@ -6,6 +6,7 @@ #include <console/console.h> +#include <cbmem.h> #include <fmap.h> #include <stdlib.h> #include <string.h> @@ -17,6 +18,8 @@ /* Currently we only support Google VPD 2.0, which has a fixed offset. */ enum { GOOGLE_VPD_2_0_OFFSET = 0x600, + CROSVPD_CBMEM_MAGIC = 0x43524f53, + CROSVPD_CBMEM_VERSION = 0x0001, }; struct vpd_gets_arg { @@ -26,56 +29,121 @@ struct vpd_gets_arg { int matched; }; -static int cros_vpd_load(uint8_t **vpd_address, int32_t *vpd_size) +struct vpd_cbmem { + uint32_t magic; + uint32_t version; + uint32_t ro_size; + uint32_t rw_size; + uint8_t blob[0]; + /* The blob contains both RO and RW data. It starts with RO (0 .. + * ro_size) and then RW (ro_size .. ro_size+rw_size). + */ +}; + +/* returns the size of data in a VPD 2.0 formatted fmap region, or 0 */ +static int32_t get_vpd_size(const char *fmap_name, int32_t *base) { - MAYBE_STATIC int cached = 0; - MAYBE_STATIC uint8_t *cached_address = NULL; - MAYBE_STATIC int32_t cached_size = 0; - MAYBE_STATIC int result = -1; struct google_vpd_info info; - int32_t base; struct region_device vpd; + int32_t size; - if (cached) { - *vpd_address = cached_address; - *vpd_size = cached_size; - return result; - } - - cached = 1; - if (fmap_locate_area_as_rdev("RO_VPD", &vpd)) { - printk(BIOS_ERR, "%s: No RO_VPD FMAP section.\n", __func__); - return result; + if (fmap_locate_area_as_rdev(fmap_name, &vpd)) { + printk(BIOS_ERR, "%s: No %s FMAP section.\n", __func__, + fmap_name); + return 0; } - base = 0; - cached_size = region_device_sz(&vpd); + size = region_device_sz(&vpd); - if ((cached_size < GOOGLE_VPD_2_0_OFFSET + sizeof(info)) || + if ((size < GOOGLE_VPD_2_0_OFFSET + sizeof(info)) || rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET, - cached_size - GOOGLE_VPD_2_0_OFFSET)) { + size - GOOGLE_VPD_2_0_OFFSET)) { printk(BIOS_ERR, "%s: Too small (%d) for Google VPD 2.0.\n", - __func__, cached_size); - return result; + __func__, size); + return 0; } /* Try if we can find a google_vpd_info, otherwise read whole VPD. */ - if (rdev_readat(&vpd, &info, base, sizeof(info)) == sizeof(info) && + if (rdev_readat(&vpd, &info, *base, sizeof(info)) == sizeof(info) && memcmp(info.header.magic, VPD_INFO_MAGIC, sizeof(info.header.magic)) - == 0 && cached_size >= info.size + sizeof(info)) { - base += sizeof(info); - cached_size = info.size; + == 0 && size >= info.size + sizeof(info)) { + *base += sizeof(info); + size = info.size; + } else { + size -= GOOGLE_VPD_2_0_OFFSET; + } + + return size; +} + +static void cbmem_add_cros_vpd(int is_recovery) +{ + struct region_device vpd; + struct vpd_cbmem *cbmem; + int32_t ro_vpd_base = 0, rw_vpd_base = 0; + int32_t ro_vpd_size, rw_vpd_size; + + ro_vpd_size = get_vpd_size("RO_VPD", &ro_vpd_base); + rw_vpd_size = get_vpd_size("RW_VPD", &rw_vpd_base); + + /* no VPD at all? nothing to do then */ + if ((ro_vpd_size == 0) && (rw_vpd_size == 0)) + return; + + cbmem = cbmem_add(CBMEM_ID_VPD, sizeof(*cbmem) + ro_vpd_size + + rw_vpd_size); + if (!cbmem) { + printk(BIOS_ERR, "%s: Failed to allocate CBMEM (%zu+%zu).\n", + __func__, ro_vpd_size, rw_vpd_size); + return; } - cached_address = rdev_mmap(&vpd, base, cached_size); - if (cached_address) { - *vpd_address = cached_address; - *vpd_size = cached_size; - printk(BIOS_DEBUG, "%s: Got VPD: %#x+%#x\n", __func__, base, - cached_size); - result = 0; + cbmem->magic = CROSVPD_CBMEM_MAGIC; + cbmem->version = CROSVPD_CBMEM_VERSION; + cbmem->ro_size = 0; + cbmem->rw_size = 0; + + if (ro_vpd_size) { + if (fmap_locate_area_as_rdev("RO_VPD", &vpd)) { + /* shouldn't happen, but let's be extra defensive */ + printk(BIOS_ERR, "%s: No RO_VPD FMAP section.\n", + __func__); + return; + } + rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET, + region_device_sz(&vpd) - GOOGLE_VPD_2_0_OFFSET); + + + if (rdev_readat(&vpd, cbmem->blob, ro_vpd_base, ro_vpd_size) == + ro_vpd_size) { + cbmem->ro_size = ro_vpd_size; + } else { + printk(BIOS_ERR, + "%s: Reading RO_VPD FMAP section failed.\n", + __func__); + ro_vpd_size = 0; + } + } + + if (rw_vpd_size) { + if (fmap_locate_area_as_rdev("RW_VPD", &vpd)) { + /* shouldn't happen, but let's be extra defensive */ + printk(BIOS_ERR, "%s: No RW_VPD FMAP section.\n", + __func__); + return; + } + rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET, + region_device_sz(&vpd) - GOOGLE_VPD_2_0_OFFSET); + + if (rdev_readat(&vpd, cbmem->blob + ro_vpd_size, rw_vpd_base, + rw_vpd_size) == rw_vpd_size) { + cbmem->rw_size = rw_vpd_size; + } else { + printk(BIOS_ERR, + "%s: Reading RW_VPD FMAP section failed.\n", + __func__); + } } - return result; } static int vpd_gets_callback(const uint8_t *key, int32_t key_len, @@ -97,19 +165,18 @@ static int vpd_gets_callback(const uint8_t *key, int32_t key_len, const void *cros_vpd_find(const char *key, int *size) { - uint8_t *vpd_address = NULL; - int32_t vpd_size = 0; struct vpd_gets_arg arg = {0}; int consumed = 0; + const struct vpd_cbmem *vpd; - if (cros_vpd_load(&vpd_address, &vpd_size) != 0) { + vpd = cbmem_find(CBMEM_ID_VPD); + if (!vpd || !vpd->ro_size) return NULL; - } arg.key = (const uint8_t *)key; arg.key_len = strlen(key); - while (VPD_OK == decodeVpdString(vpd_size, vpd_address, &consumed, + while (VPD_OK == decodeVpdString(vpd->ro_size, vpd->blob, &consumed, vpd_gets_callback, &arg)) { /* Iterate until found or no more entries. */ } @@ -141,3 +208,4 @@ char *cros_vpd_gets(const char *key, char *buffer, int size) return buffer; } +RAMSTAGE_CBMEM_INIT_HOOK(cbmem_add_cros_vpd)

1 0

Patch set updated for coreboot: edid: Don't half parse (and wrongly print) more detailed timings
by Patrick Georgi 19 Nov '15

19 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12444 -gerrit commit e85643707c55be24225c5ec7ee4f6b93ab1c7a8e Author: Douglas Anderson <dianders(a)chromium.org> Date: Wed Oct 28 09:18:28 2015 -0700 edid: Don't half parse (and wrongly print) more detailed timings The EDID parsing code continued to update _some_ fields of the output edid but not others if "did_detailed_timing" was already set. It also then went on to print out this halfway mix of modes each time, despite the fact that it didn't really update everything. Let's fix that. We'll reduce code changes by using a temporary copy of data in detailed_block() and then we'll copy it back if we decide we should update. BRANCH=none BUG=chrome-os-partner:46998 TEST=No more bogus printouts Change-Id: Idbfa233e0997244c22ef21c892c4473a91621821 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4d69999cdd7ce3cd2c9332ab3f22ea8eb4b6f2e9 Original-Change-Id: Ia72cac7fda2772f26477e43237678fa30feca584 Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309541 Original-Reviewed-on: https://chromium-review.googlesource.com/309609 Original-Commit-Ready: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/lib/edid.c | 125 +++++++++++++++++++++++++++++++-------------------------- 1 file changed, 67 insertions(+), 58 deletions(-) diff --git a/src/lib/edid.c b/src/lib/edid.c index 8c8ab6f..3aebc65 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -91,6 +91,8 @@ static struct { const char *stereo; } extra_info; +static struct edid tmp_edid; + static int vbe_valid; static struct lb_framebuffer edid_fb; @@ -197,9 +199,10 @@ extract_string(unsigned char *x, int *valid_termination, int len) /* 1 means valid data */ static int -detailed_block(struct edid *out, unsigned char *x, int in_extension, +detailed_block(struct edid *result_edid, unsigned char *x, int in_extension, struct edid_context *c) { + struct edid *out = &tmp_edid; int i; #if 1 printk(BIOS_SPEW, "Hex of detail: "); @@ -208,6 +211,9 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension, printk(BIOS_SPEW, "\n"); #endif + /* Result might already have some valid fields like mode_is_supported */ + *out = *result_edid; + if (x[0] == 0 && x[1] == 0) { /* Monitor descriptor block, not detailed timing descriptor. */ if (x[2] != 0) { @@ -443,63 +449,59 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension, c->has_valid_descriptor_ordering = 0; } - if (! c->did_detailed_timing){ - /* Edid contains pixel clock in terms of 10KHz */ - out->mode.pixel_clock = (x[0] + (x[1] << 8)) * 10; - /* - LVDS supports following pixel clocks - 25000...112000 kHz: single channel - 80000...224000 kHz: dual channel - There is some overlap in theoretically supported - pixel clock between single-channel and dual-channel. - In practice with current panels all panels - <= 75200 kHz: single channel - >= 97750 kHz: dual channel - We have no samples between those values, so put a - threshold at 95000 kHz. If we get anything over - 95000 kHz with single channel, we can make this - more sofisticated but it's currently not needed. - */ - out->mode.lvds_dual_channel = (out->mode.pixel_clock >= 95000); - extra_info.x_mm = (x[12] + ((x[14] & 0xF0) << 4)); - extra_info.y_mm = (x[13] + ((x[14] & 0x0F) << 8)); - out->mode.ha = (x[2] + ((x[4] & 0xF0) << 4)); - out->mode.hbl = (x[3] + ((x[4] & 0x0F) << 8)); - out->mode.hso = (x[8] + ((x[11] & 0xC0) << 2)); - out->mode.hspw = (x[9] + ((x[11] & 0x30) << 4)); - out->mode.hborder = x[15]; - out->mode.va = (x[5] + ((x[7] & 0xF0) << 4)); - out->mode.vbl = (x[6] + ((x[7] & 0x0F) << 8)); - out->mode.vso = ((x[10] >> 4) + ((x[11] & 0x0C) << 2)); - out->mode.vspw = ((x[10] & 0x0F) + ((x[11] & 0x03) << 4)); - out->mode.vborder = x[16]; - /* set up some reasonable defaults for payloads. - * We observe that most modern chipsets we work with - * tend to support rgb888 without regard to the - * panel bits per color or other settings. The rgb888 - * is a convenient layout for software because - * it avoids the messy bit stuffing of rgb565 or rgb444. - * It makes a reasonable trade of memory for speed. - * So, set up the default for - * 32 bits per pixel - * rgb888 (i.e. no alpha, but pixels on 32-bit boundaries) - * The mainboard can modify these if needed, though - * we have yet to see a case where that will happen. - * The existing ARM mainboards don't even call this function - * so this will not affect them. - */ - out->framebuffer_bits_per_pixel = 32; - - out->x_resolution = ALIGN(out->mode.ha * - ((out->framebuffer_bits_per_pixel + 7) / 8), - 64) / (out->framebuffer_bits_per_pixel/8); - out->y_resolution = out->mode.va; - out->bytes_per_line = ALIGN(out->mode.ha * - ((out->framebuffer_bits_per_pixel + 7)/8), - 64); - printk(BIOS_SPEW, "Did detailed timing\n"); - } - c->did_detailed_timing = 1; + /* Edid contains pixel clock in terms of 10KHz */ + out->mode.pixel_clock = (x[0] + (x[1] << 8)) * 10; + /* + LVDS supports following pixel clocks + 25000...112000 kHz: single channel + 80000...224000 kHz: dual channel + There is some overlap in theoretically supported + pixel clock between single-channel and dual-channel. + In practice with current panels all panels + <= 75200 kHz: single channel + >= 97750 kHz: dual channel + We have no samples between those values, so put a + threshold at 95000 kHz. If we get anything over + 95000 kHz with single channel, we can make this + more sofisticated but it's currently not needed. + */ + out->mode.lvds_dual_channel = (out->mode.pixel_clock >= 95000); + extra_info.x_mm = (x[12] + ((x[14] & 0xF0) << 4)); + extra_info.y_mm = (x[13] + ((x[14] & 0x0F) << 8)); + out->mode.ha = (x[2] + ((x[4] & 0xF0) << 4)); + out->mode.hbl = (x[3] + ((x[4] & 0x0F) << 8)); + out->mode.hso = (x[8] + ((x[11] & 0xC0) << 2)); + out->mode.hspw = (x[9] + ((x[11] & 0x30) << 4)); + out->mode.hborder = x[15]; + out->mode.va = (x[5] + ((x[7] & 0xF0) << 4)); + out->mode.vbl = (x[6] + ((x[7] & 0x0F) << 8)); + out->mode.vso = ((x[10] >> 4) + ((x[11] & 0x0C) << 2)); + out->mode.vspw = ((x[10] & 0x0F) + ((x[11] & 0x03) << 4)); + out->mode.vborder = x[16]; + /* set up some reasonable defaults for payloads. + * We observe that most modern chipsets we work with + * tend to support rgb888 without regard to the + * panel bits per color or other settings. The rgb888 + * is a convenient layout for software because + * it avoids the messy bit stuffing of rgb565 or rgb444. + * It makes a reasonable trade of memory for speed. + * So, set up the default for + * 32 bits per pixel + * rgb888 (i.e. no alpha, but pixels on 32-bit boundaries) + * The mainboard can modify these if needed, though + * we have yet to see a case where that will happen. + * The existing ARM mainboards don't even call this function + * so this will not affect them. + */ + out->framebuffer_bits_per_pixel = 32; + + out->x_resolution = ALIGN(out->mode.ha * + ((out->framebuffer_bits_per_pixel + 7) / 8), + 64) / (out->framebuffer_bits_per_pixel/8); + out->y_resolution = out->mode.va; + out->bytes_per_line = ALIGN(out->mode.ha * + ((out->framebuffer_bits_per_pixel + 7)/8), + 64); switch ((x[17] & 0x18) >> 3) { case 0x00: extra_info.syncmethod = " analog composite"; @@ -556,6 +558,13 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension, out->mode.phsync, out->mode.pvsync, extra_info.syncmethod, x[17] & 0x80 ?" interlaced" : "", extra_info.stereo); + + if (! c->did_detailed_timing) { + printk(BIOS_SPEW, "Did detailed timing\n"); + c->did_detailed_timing = 1; + *result_edid = *out; + } + return 1; }

1 0

Patch set updated for coreboot: edid: Remove useless parameter from detailed_cvt_descriptor()
by Patrick Georgi 19 Nov '15

19 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12441 -gerrit commit e9d975a9516add75a34aa2dff4094514149cb39e Author: Douglas Anderson <dianders(a)chromium.org> Date: Wed Oct 28 11:19:57 2015 -0700 edid: Remove useless parameter from detailed_cvt_descriptor() The detailed_cvt_descriptor() function takes a parameter "out" for no good reason. Remove it. BRANCH=none BUG=chrome-os-partner:46998 TEST=Build and boot Change-Id: I1042dba9ddf2b4b543bd07615013088be5055950 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5c3474c9b1f9fb73f44d64d3a0592f92339da2df Original-Change-Id: I4d695a6dba6606d2132578ce0ab4cb612c83d0f4 Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309598 Original-(cherry picked from commit 39122e242e808d71a4e274e8a23e9a63f4984388) Original-Reviewed-on: https://chromium-review.googlesource.com/309496 Original-Commit-Ready: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/lib/edid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/lib/edid.c b/src/lib/edid.c index 0f5643d..e94720e 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -110,7 +110,7 @@ static char *manufacturer_name(unsigned char *x) } static int -detailed_cvt_descriptor(struct edid *out, unsigned char *x, int first) +detailed_cvt_descriptor(unsigned char *x, int first) { const unsigned char empty[3] = { 0, 0, 0 }; const char *names[] = { "50", "60", "75", "85" }; @@ -253,7 +253,7 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension, return 0; } for (i = 0; i < 4; i++) - valid_cvt &= detailed_cvt_descriptor(out, x + 6 + (i * 3), (i == 0)); + valid_cvt &= detailed_cvt_descriptor(x + 6 + (i * 3), (i == 0)); c->has_valid_cvt &= valid_cvt; return 1; }

1 0

Patch set updated for coreboot: edid: Don't set standard timings as supported if they're not
by Patrick Georgi 19 Nov '15

19 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12442 -gerrit commit 29e0bd926ecbff4fbe217ee17c03382a6354e9a9 Author: Douglas Anderson <dianders(a)chromium.org> Date: Wed Oct 28 10:19:52 2015 -0700 edid: Don't set standard timings as supported if they're not The set to say that a standard timing was supported was not properly in the "if" test. That meant that even when standard timings weren't supported, we thought that they were. That had the side effect of never using the detailed mode. BRANCH=none BUG=chrome-os-partner:46998 TEST=Adafruit panel works now Change-Id: Ide3ed6c5682840f808d854755dac58e9057e6bda Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c99d3ee8d163fc6be207c5a7df2a7aecd7af7849 Original-Change-Id: Ib67735219fd28516857d9b63f1ba156573f1bea3 Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309521 Original-(cherry picked from commit 4e4c2816e2239299bc02e3a57fb18056db62b56c) Original-Reviewed-on: https://chromium-review.googlesource.com/309552 Original-Commit-Ready: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/lib/edid.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/lib/edid.c b/src/lib/edid.c index e94720e..6663d1c 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -1272,13 +1272,13 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) if (edid[0x23 + i / 8] & (1 << (7 - i % 8))) { printk(BIOS_SPEW, " %dx%d@%dHz\n", established_timings[i].x, established_timings[i].y, established_timings[i].refresh); - } - for (j = 0; j < NUM_KNOWN_MODES; j++) { - if (known_modes[j].ha == established_timings[i].x && - known_modes[j].va == established_timings[i].y && - known_modes[j].refresh == established_timings[i].refresh) + for (j = 0; j < NUM_KNOWN_MODES; j++) { + if (known_modes[j].ha == established_timings[i].x && + known_modes[j].va == established_timings[i].y && + known_modes[j].refresh == established_timings[i].refresh) out->mode_is_supported[j] = 1; + } } }

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2015