coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: x86: Add Kconfig to disable early bootblock postcodes
by Martin Roth 17 Nov '15

17 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12422 -gerrit commit 7b9c64d48f02dfae6a2134bf065b39ab1d3a6efe Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 12 14:02:42 2015 -0700 x86: Add Kconfig to disable early bootblock postcodes The Intel cave creek chipset needs to have port 80 routing configured before any post codes can be sent to port 80h. Sending post codes out before the routing is done will hang the system. This patch allows us to disable the first couple of post codes that go out before the routing can be configured. Change-Id: I9bf41669ec32744f87a1ed2de011d31c72ea38da Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/console/Kconfig | 9 +++++++++ src/cpu/x86/16bit/entry16.inc | 3 ++- src/cpu/x86/32bit/entry32.inc | 2 ++ src/southbridge/intel/fsp_i89xx/Kconfig | 1 + 4 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index a2f893a..d815637 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -350,4 +350,13 @@ config POST_IO_PORT depending on the presence of coprocessors/microcontrollers or if the platform does not support IO in the conventional x86 manner. +config NO_EARLY_BOOTBLOCK_POSTCODES + def_bool n + help + Some chipsets require that the routing for the port 80h POST + code be configured before any POST codes are sent out. + This can be done in the boot block, but there are a couple of + POST codes that go out before the chipset's bootblock initialization + can happen. This option suppresses those POST codes. + endmenu diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 4dad1e5..abaf671 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -36,8 +36,9 @@ _start: cli /* Save the BIST result */ movl %eax, %ebp - +#if !IS_ENABLED(CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES) post_code(POST_RESET_VECTOR_CORRECT) +#endif /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before * executing any further code. Even though paging is disabled we diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index 5c3072e..9ef3bc1 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -56,7 +56,9 @@ __protected_start: /* Save the BIST value */ movl %eax, %ebp +#if !IS_ENABLED(CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES) post_code(POST_ENTER_PROTECTED_MODE) +#endif movw $ROM_DATA_SEG, %ax movw %ax, %ds diff --git a/src/southbridge/intel/fsp_i89xx/Kconfig b/src/southbridge/intel/fsp_i89xx/Kconfig index d1426d6..9d195d2 100644 --- a/src/southbridge/intel/fsp_i89xx/Kconfig +++ b/src/southbridge/intel/fsp_i89xx/Kconfig @@ -34,6 +34,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SPI_FLASH select COMMON_FADT select HAVE_INTEL_FIRMWARE + select NO_EARLY_BOOTBLOCK_POSTCODES config EHCI_BAR hex

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Patch set updated for coreboot: amdfwtool: Add amdfwtool to combine AMD firmwares
by Zheng Bao 17 Nov '15

17 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12419 -gerrit commit 25c4c65755ab18b9c798f60782077945acb0d9f9 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Nov 17 22:57:39 2015 +0800 amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- Makefile.inc | 8 +- util/amdfwtool/Makefile | 36 +++ util/amdfwtool/amdfwtool.c | 534 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 574 insertions(+), 4 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index b85a2cb..f5326ba 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -290,7 +290,7 @@ CFLAGS_common += -Os endif additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \ - $(objutil)/ifdfake $(objutil)/options $(objutil)/fletcher \ + $(objutil)/ifdfake $(objutil)/options $(objutil)/amdfwtool \ $(objutil)/cbootimage $(objutil)/bimgtool ####################################################################### @@ -348,10 +348,10 @@ $(IFDFAKE): $(top)/util/ifdfake/ifdfake.c @printf " HOSTCC $(subst $(obj)/,,$(@))\n" $(HOSTCC) $(HOSTCFLAGS) -o $@ $< -FLETCHER:=$(objutil)/fletcher/fletcher -$(FLETCHER): $(top)/util/fletcher/fletcher.c +AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool +$(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c @printf " HOSTCC $(subst $(obj)/,,$(@))\n" - $(HOSTCC) $(HOSTCFLAGS) -o $@ $< + $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $< CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage diff --git a/util/amdfwtool/Makefile b/util/amdfwtool/Makefile new file mode 100644 index 0000000..f252066 --- /dev/null +++ b/util/amdfwtool/Makefile @@ -0,0 +1,36 @@ +#***************************************************************************** +# +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Advanced Micro Devices, Inc. nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#***************************************************************************** +HOSTCC ?= cc + +amdfwtool_exe : amdfwtool.c + $(HOSTCC) amdfwtool.c -o amdfwtool + +amdfwtool : amdfwtool_exe + +clean: + @rm -f amdfwtool.o amdfwtool amdfwtool.exe diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c new file mode 100644 index 0000000..f090411 --- /dev/null +++ b/util/amdfwtool/amdfwtool.c @@ -0,0 +1,534 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * ROMSIG At ROMBASE + 0x20000: + * +------------+---------------+----------------+------------+ + * | 0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | + * +------------+---------------+----------------+------------+ + * | PSPDIR ADDR|PSP2DIR ADDR | + * +------------+---------------+ + * EC ROM should be 64K aligned. + * + * PSP directory + * +------------+---------------+----------------+------------+ + * | 'PSP$' | Fletcher | Count | Reserved | + * +------------+---------------+----------------+------------+ + * | 0 | size | Base address | Reserved | Pubkey + * +------------+---------------+----------------+------------+ + * | 1 | size | Base address | Reserved | Bootloader + * +------------+---------------+----------------+------------+ + * | 8 | size | Base address | Reserved | Smu Firmware + * +------------+---------------+----------------+------------+ + * | 3 | size | Base address | Reserved | Recovery Firmware + * +------------+---------------+----------------+------------+ + * | | + * | | + * | Other PSP Firmware | + * | | + * | | + * +------------+---------------+----------------+------------+ + */ + + +#include <fcntl.h> +#include <errno.h> +#include <stdio.h> +#include <sys/stat.h> +#include <sys/types.h> +#include <unistd.h> +#include <string.h> +#include <stdlib.h> +#include <getopt.h> + +#ifndef CONFIG_ROM_SIZE +#define CONFIG_ROM_SIZE 0x400000 +#endif + +#define ROM_BASE_ADDRESS (0xFFFFFFFF - CONFIG_ROM_SIZE + 1) +#define AMD_ROMSIG_OFFSET 0x20000 + +#define ALIGN(val, by) (((val) + (by)-1)&~((by)-1)) + +/* + Reserved for future. + TODO: PSP2 is for Combo BIOS, which is the idea that one image supports 2 + kinds of APU. +*/ +#define PSP2 1 + +typedef unsigned int uint32_t; +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; + +/* + * Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3. + * The checksum field of the passed PDU does not need to be reset to zero. + * + * The "Fletcher Checksum" was proposed in a paper by John G. Fletcher of + * Lawrence Livermore Labs. The Fletcher Checksum was proposed as an + * alternative to cyclical redundancy checks because it provides error- + * detection properties similar to cyclical redundancy checks but at the + * cost of a simple summation technique. Its characteristics were first + * published in IEEE Transactions on Communications in January 1982. One + * version has been adopted by ISO for use in the class-4 transport layer + * of the network protocol. + * + * This program expects: + * stdin: The input file to compute a checksum for. The input file + * not be longer than 256 bytes. + * stdout: Copied from the input file with the Fletcher's Checksum + * inserted 8 bytes after the beginning of the file. + * stderr: Used to print out error messages. + */ +uint32_t fletcher32 (const uint16_t *pptr, int length) +{ + uint32_t c0; + uint32_t c1; + uint32_t checksum; + int index; + + c0 = 0xFFFF; + c1 = 0xFFFF; + + for (index = 0; index < length; index++) { + /* + * Ignore the contents of the checksum field. + */ + c0 += *(pptr++); + c1 += c0; + if ((index % 360) == 0) { + c0 = (c0 & 0xFFFF) + (c0 >> 16); // Sum0 modulo 65535 + the overflow + c1 = (c1 & 0xFFFF) + (c1 >> 16); // Sum1 modulo 65535 + the overflow + } + } + + c0 = (c0 & 0xFFFF) + (c0 >> 16); // Sum0 modulo 65535 + the overflow + c1 = (c1 & 0xFFFF) + (c1 >> 16); // Sum1 modulo 65535 + the overflow + checksum = (c1 << 16) | c0; + + return checksum; +} + +void usage() +{ + printf("Create AMD Firmware combination\n"); +} + +typedef enum _amd_fw_type { + AMD_FW_PSP_PUBKEY = 0, + AMD_FW_PSP_BOOTLOADER = 1, + AMD_FW_PSP_SMU_FIRMWARE = 8, + AMD_FW_PSP_RECOVERY = 3, + AMD_FW_PSP_RTM_PUBKEY = 5, + AMD_FW_PSP_SECURED_OS = 2, + AMD_FW_PSP_NVRAM = 4, + AMD_FW_PSP_SECURED_DEBUG = 9, + AMD_FW_PSP_TRUSTLETS = 12, + AMD_FW_PSP_TRUSTLETKEY = 13, + AMD_FW_PSP_SMU_FIRMWARE2 = 18, + AMD_PSP_FUSE_CHAIN = 11, + AMD_FW_PSP_SMUSCS = 95, + + AMD_FW_IMC, + AMD_FW_GEC, + AMD_FW_XHCI, +} amd_fw_type; + +typedef struct _amd_fw_entry { + amd_fw_type type; + char *filename; +} amd_fw_entry; + +amd_fw_entry amd_psp_fw_table[] = { + { .type = AMD_FW_PSP_PUBKEY }, + { .type = AMD_FW_PSP_BOOTLOADER }, + { .type = AMD_FW_PSP_SMU_FIRMWARE }, + { .type = AMD_FW_PSP_RECOVERY }, + { .type = AMD_FW_PSP_RTM_PUBKEY }, + { .type = AMD_FW_PSP_SECURED_OS }, + { .type = AMD_FW_PSP_NVRAM }, + { .type = AMD_FW_PSP_SECURED_DEBUG }, + { .type = AMD_FW_PSP_TRUSTLETS }, + { .type = AMD_FW_PSP_TRUSTLETKEY }, + { .type = AMD_FW_PSP_SMU_FIRMWARE2 }, + { .type = AMD_FW_PSP_SMUSCS }, + { .type = AMD_PSP_FUSE_CHAIN }, +}; + +#if PSP2 +amd_fw_entry amd_psp2_fw_table[] = { + { .type = AMD_FW_PSP_PUBKEY }, + { .type = AMD_FW_PSP_BOOTLOADER }, + { .type = AMD_FW_PSP_SMU_FIRMWARE }, + { .type = AMD_FW_PSP_RECOVERY }, + { .type = AMD_FW_PSP_RTM_PUBKEY }, + { .type = AMD_FW_PSP_SECURED_OS }, + { .type = AMD_FW_PSP_NVRAM }, + { .type = AMD_FW_PSP_SECURED_DEBUG }, + { .type = AMD_FW_PSP_TRUSTLETS }, + { .type = AMD_FW_PSP_TRUSTLETKEY }, + { .type = AMD_FW_PSP_SMU_FIRMWARE2 }, + { .type = AMD_FW_PSP_SMUSCS }, + { .type = AMD_PSP_FUSE_CHAIN }, +}; +#endif + +amd_fw_entry amd_fw_table[] = { + { .type = AMD_FW_XHCI }, + { .type = AMD_FW_IMC }, + { .type = AMD_FW_GEC }, +}; + +void fill_psp_head(uint32_t *pspdir, int count) +{ + pspdir[0] = 1347637284; /* 'PSP$' */ + pspdir[2] = count; /* size */ + pspdir[3] = 0; + pspdir[1] = fletcher32((uint16_t *)&pspdir[1], (count *16 + 16)/2 - 2); +} + +uint32_t integerate_one_fw(void *base, uint32_t pos, uint32_t *romsig, int i) +{ + int fd; + struct stat fd_stat; + + if (amd_fw_table[i].filename != NULL) { + fd = open (amd_fw_table[i].filename, O_RDONLY); + fstat(fd, &fd_stat); + + switch (amd_fw_table[i].type) { + case AMD_FW_IMC: + pos = ALIGN(pos, 0x10000); + romsig[1] = pos + ROM_BASE_ADDRESS; + break; + case AMD_FW_GEC: + romsig[2] = pos + ROM_BASE_ADDRESS; + break; + case AMD_FW_XHCI: + romsig[3] = pos + ROM_BASE_ADDRESS; + break; + default: + /* Error */ + break; + } + + read (fd, base+pos, fd_stat.st_size); + + pos += fd_stat.st_size; + pos = ALIGN(pos, 0x100); + close (fd); + } + + return pos; +} + +uint32_t integerate_one_psp(void *base, uint32_t pos, uint32_t *pspdir, int i) +{ + int fd; + struct stat fd_stat; + + if (amd_psp_fw_table[i].type == AMD_PSP_FUSE_CHAIN) { + pspdir[4+4*i+0] = amd_psp_fw_table[i].type; + pspdir[4+4*i+1] = 0xFFFFFFFF; + pspdir[4+4*i+2] = 1; + pspdir[4+4*i+3] = 0; + } else if (amd_psp_fw_table[i].filename != NULL) { + pspdir[4+4*i+0] = amd_psp_fw_table[i].type; + + fd = open (amd_psp_fw_table[i].filename, O_RDONLY); + fstat(fd, &fd_stat); + pspdir[4+4*i+1] = fd_stat.st_size; + + pspdir[4+4*i+2] = pos + ROM_BASE_ADDRESS; + pspdir[4+4*i+3] = 0; + + read (fd, base+pos, fd_stat.st_size); + + pos += fd_stat.st_size; + pos = ALIGN(pos, 0x100); + close (fd); + } else { + /* This APU doesn't have this firmware. */ + } + + return pos; +} + +static const char *optstring = "x:i:g:p:b:s:r:k:o:n:d:t:u:w:m:h"; +static struct option long_options[] = { + {"xhci", required_argument, 0, 'x' }, + {"imc", required_argument, 0, 'i' }, + {"gec", required_argument, 0, 'g' }, + /* PSP */ + {"pubkey", required_argument, 0, 'p' }, + {"bootloader", required_argument, 0, 'b' }, + {"smufirmware", required_argument, 0, 's' }, + {"recovery", required_argument, 0, 'r' }, + {"rtmpubkey", required_argument, 0, 'k' }, + {"secureos", required_argument, 0, 'c' }, + {"nvram", required_argument, 0, 'n' }, + {"securedebug", required_argument, 0, 'd' }, + {"trustlets", required_argument, 0, 't' }, + {"trustletkey", required_argument, 0, 'u' }, + {"smufirmware2", required_argument, 0, 'w' }, + {"smuscs", required_argument, 0, 'm' }, + + /* TODO: PSP2 */ +#if PSP2 + {"pubkey2", required_argument, 0, 'P' }, + {"bootloader2", required_argument, 0, 'B' }, + {"smufirmware2", required_argument, 0, 'S' }, + {"recovery2", required_argument, 0, 'R' }, + {"rtmpubkey2", required_argument, 0, 'K' }, + {"secureos2", required_argument, 0, 'C' }, + {"nvram2", required_argument, 0, 'N' }, + {"securedebug2", required_argument, 0, 'D' }, + {"trustlets2", required_argument, 0, 'T' }, + {"trustletkey2", required_argument, 0, 'U' }, + {"smufirmware2_2",required_argument, 0, 'W' }, + {"smuscs2", required_argument, 0, 'M' }, +#endif + + {"output", required_argument, 0, 'o' }, + {"help", no_argument, 0, 'h' }, + + {NULL, 0, 0, 0 } +}; + +void register_fw_filename(amd_fw_type type, char filename[], int pspflag) +{ + int i; + + for (i = 0; i < sizeof(amd_fw_table)/sizeof(amd_fw_entry); i++) { + if (amd_fw_table[i].type == type) { + amd_fw_table[i].filename = filename; + return; + } + } + + if (pspflag == 1) { + for (i = 0; i < sizeof(amd_psp_fw_table)/sizeof(amd_fw_entry); i++) { + if (amd_psp_fw_table[i].type == type) { + amd_psp_fw_table[i].filename = filename; + return; + } + } + } + +#if PSP2 + if (pspflag == 2) { + for (i = 0; i < sizeof(amd_psp2_fw_table)/sizeof(amd_fw_entry); i++) { + if (amd_psp2_fw_table[i].type == type) { + amd_psp2_fw_table[i].filename = filename; + return; + } + } + } +#endif +} + +int main(int argc, char **argv) +{ + int c, count, pspflag = 0; +#if PSP2 + int psp2flag = 0; +#endif + void *rom = NULL; + uint32_t current; + uint32_t *amd_romsig, *pspdir; + + int targetfd; + char *output; + + rom = malloc(CONFIG_ROM_SIZE); + memset (rom, 0xFF, CONFIG_ROM_SIZE); + if (!rom) { + return 1; + } + + current = AMD_ROMSIG_OFFSET; + amd_romsig = rom + AMD_ROMSIG_OFFSET; + amd_romsig[0] = 0x55AA55AA; /* romsig */ + + current += 0x20; /* size of ROMSIG */ + + while (1) { + int optindex = 0; + + c = getopt_long(argc, argv, optstring, long_options, &optindex); + + if (c == -1) + break; + + switch (c) { + case 'x': + register_fw_filename(AMD_FW_XHCI, optarg, 0); + break; + case 'i': + register_fw_filename(AMD_FW_IMC, optarg, 0); + break; + case 'g': + register_fw_filename(AMD_FW_GEC, optarg, 0); + break; + case 'p': + register_fw_filename(AMD_FW_PSP_PUBKEY, optarg, 1); + pspflag = 1; + break; + case 'b': + register_fw_filename(AMD_FW_PSP_BOOTLOADER, optarg, 1); + pspflag = 1; + break; + case 's': + register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE, optarg, 1); + pspflag = 1; + break; + case 'r': + register_fw_filename(AMD_FW_PSP_RECOVERY, optarg, 1); + pspflag = 1; + break; + case 'k': + register_fw_filename(AMD_FW_PSP_RTM_PUBKEY, optarg, 1); + pspflag = 1; + break; + case 'c': + register_fw_filename(AMD_FW_PSP_SECURED_OS, optarg, 1); + pspflag = 1; + break; + case 'n': + register_fw_filename(AMD_FW_PSP_NVRAM, optarg, 1); + pspflag = 1; + break; + case 'd': + register_fw_filename(AMD_FW_PSP_SECURED_DEBUG, optarg, 1); + pspflag = 1; + break; + case 't': + register_fw_filename(AMD_FW_PSP_TRUSTLETS, optarg, 1); + pspflag = 1; + break; + case 'u': + register_fw_filename(AMD_FW_PSP_TRUSTLETKEY, optarg, 1); + pspflag = 1; + break; + case 'w': + register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE2, optarg, 1); + pspflag = 1; + break; + case 'm': + register_fw_filename(AMD_FW_PSP_SMUSCS, optarg, 1); + pspflag = 1; + break; +#if PSP2 + case 'P': + register_fw_filename(AMD_FW_PSP_PUBKEY, optarg, 2); + psp2flag = 1; + break; + case 'B': + register_fw_filename(AMD_FW_PSP_BOOTLOADER, optarg, 2); + psp2flag = 1; + break; + case 'S': + register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE, optarg, 2); + psp2flag = 1; + break; + case 'R': + register_fw_filename(AMD_FW_PSP_RECOVERY, optarg, 2); + psp2flag = 1; + break; + case 'K': + register_fw_filename(AMD_FW_PSP_RTM_PUBKEY, optarg, 2); + psp2flag = 1; + break; + case 'C': + register_fw_filename(AMD_FW_PSP_SECURED_OS, optarg, 2); + psp2flag = 1; + break; + case 'N': + register_fw_filename(AMD_FW_PSP_NVRAM, optarg, 2); + psp2flag = 1; + break; + case 'D': + register_fw_filename(AMD_FW_PSP_SECURED_DEBUG, optarg, 2); + psp2flag = 1; + break; + case 'T': + register_fw_filename(AMD_FW_PSP_TRUSTLETS, optarg, 2); + psp2flag = 1; + break; + case 'U': + register_fw_filename(AMD_FW_PSP_TRUSTLETKEY, optarg, 2); + psp2flag = 1; + break; + case 'W': + register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE2, optarg, 2); + psp2flag = 1; + break; + case 'M': + register_fw_filename(AMD_FW_PSP_SMUSCS, optarg, 2); + psp2flag = 1; + break; +#endif + case 'o': + output = optarg; + break; + case 'h': + usage(); + return 1; + default: + break; + } + } + + current = ALIGN(current, 0x100); + for (count = 0; count < sizeof(amd_fw_table) / sizeof(amd_fw_entry); count ++) { + current = integerate_one_fw(rom, current, amd_romsig, count); + } + + if (pspflag == 1) { + current = ALIGN(current, 0x10000); + pspdir = rom + current; + amd_romsig[4] = current + ROM_BASE_ADDRESS; + + current += 0x200; /* Conservative size of pspdir */ + for (count = 0; count < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); count ++) { + current = integerate_one_psp(rom, current, pspdir, count); + } + + fill_psp_head(pspdir, count); + +#if PSP2 + if (psp2flag == 1) { + current = ALIGN(current, 0x10000); + pspdir = rom + current; + amd_romsig[5] = current + ROM_BASE_ADDRESS; + current += 0x200; /* Conservative size of pspdir */ + + for (count = 0; count < sizeof(amd_psp2_fw_table) / sizeof(amd_fw_entry); count ++) { + current = integerate_one_psp(rom, current, pspdir, count); + } + + fill_psp_head(pspdir, count); + } +#endif + } + + targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666); + write(targetfd, amd_romsig, current - AMD_ROMSIG_OFFSET); + close(targetfd); + free(rom); + + return 0; +}

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Patch set updated for coreboot: AMD Hudson: Use amdfwtool to integrate firmwares.
by Zheng Bao 17 Nov '15

17 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12435 -gerrit commit 35be748349e3ce3d6618b1575a0124c1fa6f7d0c Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Nov 17 22:58:55 2015 +0800 AMD Hudson: Use amdfwtool to integrate firmwares. Change-Id: Ie17a744b6ef4e5405b3dfcecc1deb6462220ec60 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 102 ++---- src/southbridge/amd/pi/hudson/Makefile.inc | 426 +++++++------------------- 2 files changed, 138 insertions(+), 390 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 9e42cf2..e638c39 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -39,84 +39,6 @@ HUDSON_FWM_POS_CALC=$(call int-add, $(call int-subtract, 0xffffffff $(call int-m HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) HUDSON_FWM_INSIDE_CBFS=$(call int-lt, $(CBFS_BASE_ADDRESS) $(HUDSON_FWM_POSITION)) -#assume the cbfs header is less than 128 bytes. -ROMSIG_SIZE=16 -ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) -HUDSON_XHCI_POSITION=$(call int-add,$(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) 128) -XHCI_FWM_SIZE=$(call file-size,$(CONFIG_HUDSON_XHCI_FWM_FILE)) -else -HUDSON_XHCI_POSITION=0 -XHCI_FWM_SIZE=0 -endif - -ifeq ($(CONFIG_HUDSON_GEC_FWM), y) -HUDSON_GEC_POSITION=$(call int-add,$(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) 128 \ - $(XHCI_FWM_SIZE) 128) -GEC_FWM_SIZE=$(call file-size,$(CONFIG_HUDSON_GEC_FWM_FILE)) -else -HUDSON_GEC_POSITION=0 -GEC_FWM_SIZE=0 -endif - -ifeq ($(CONFIG_HUDSON_IMC_FWM), y) -HUDSON_IMC_POSITION=$(call int-align,\ - $(call int-add,\ - $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) 128 $(XHCI_FWM_SIZE)\ - 128 $(GEC_FWM_SIZE) 128),\ - 65536) -else -HUDSON_IMC_POSITION=0 -endif - -$(obj)/coreboot_hudson_romsig.bin: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ - $(obj)/config.h - echo " Hudson FW $@" - for fwm in 1437226410 \ - $(HUDSON_IMC_POSITION) \ - $(HUDSON_GEC_POSITION) \ - $(HUDSON_XHCI_POSITION) ; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done > $@ - -ifeq ($(CONFIG_HUDSON_FWM), y) -ifneq ($(HUDSON_FWM_POS_CALC), $(HUDSON_FWM_POSITION)) -$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION does not match calculated firmware position $(HUDSON_FWM_POS_CALC) != $(HUDSON_FWM_POSITION) ##### ) -endif -ifneq ($(HUDSON_FWM_INSIDE_CBFS), 1) -$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION ($(HUDSON_FWM_POSITION)) is outside of CBFS area ($(CBFS_BASE_ADDRESS) to 4294967295) ##### ) -endif -cbfs-files-y += hudson/fwm -hudson/fwm-file := $(obj)/coreboot_hudson_romsig.bin -hudson/fwm-position := $(HUDSON_FWM_POSITION) -hudson/fwm-type := raw -endif - -ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) -cbfs-files-y += hudson/xhci -hudson/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) -hudson/xhci-position := $(HUDSON_XHCI_POSITION) -hudson/xhci-type := raw -hudson/xhci-required := Hudson XHCI firmware (available in coreboot/3rdparty/blobs if enabled) -endif - -ifeq ($(CONFIG_HUDSON_IMC_FWM), y) -cbfs-files-y += hudson/imc -hudson/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) -hudson/imc-position := $(HUDSON_IMC_POSITION) -hudson/imc-type := raw -hudson/imc-required := Hudson IMC Firmware (available in coreboot/3rdparty/blobs if enabled) -endif - -ifeq ($(CONFIG_HUDSON_GEC_FWM), y) -cbfs-files-y += hudson/gec -hudson/gec-file := $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) -hudson/gec-position := $(HUDSON_GEC_POSITION) -hudson/gec-type := raw -hudson/gec-required := Hudson Gigabit Ethernet Controller Firmware (Contact your AMD representative) -endif - ifdef CONFIG_HUDSON_AHCI_ROM stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID)) cbfs-files-y += pci$(stripped_ahci_rom_id).rom @@ -124,3 +46,27 @@ pci$(stripped_ahci_rom_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_ROM_FIL pci$(stripped_ahci_rom_id).rom-type := optionrom pci$(stripped_ahci_rom_id).rom-required := Hudson AHCI Option ROM (Contact your AMD representative) endif + +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_HUDSON_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_XHCI_FWM_FILE), --xhci) +OPT_HUDSON_IMC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_IMC_FWM_FILE), --imc) +OPT_HUDSON_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_GEC_FWM_FILEddd), --gec) + +$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ + $(AMDFWTOOL) + rm -f $@ + echo " AMDFWTOOL $@" + $(AMDFWTOOL) \ + $(OPT_HUDSON_XHCI_FWM_FILE) \ + $(OPT_HUDSON_IMC_FWM_FILE) \ + $(OPT_HUDSON_GEC_FWM_FILE) \ + --output $@ + +cbfs-files-y += apu/amdfw +apu/amdfw-file := $(obj)/amdfw.rom +apu/amdfw-position := $(HUDSON_FWM_POSITION) +apu/amdfw-type := raw + diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 00d150f..fb775c5 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -66,371 +66,173 @@ HUDSON_FWM_POS_CALC=$(call int-add, $(call int-subtract, 0xffffffff $(call int-m HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) HUDSON_FWM_INSIDE_CBFS=$(call int-lt, $(CBFS_BASE_ADDRESS) $(HUDSON_FWM_POSITION)) -CBFS_HEADER_SIZE=0x60 - -#assume the cbfs header is less than $(CBFS_HEADER_SIZE) bytes. -ROMSIG_SIZE=4096 -ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) -HUDSON_XHCI_POSITION=$(call int-add,$(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) $(CBFS_HEADER_SIZE)) -XHCI_FWM_SIZE=$(call file-size,$(CONFIG_HUDSON_XHCI_FWM_FILE)) -else -HUDSON_XHCI_POSITION=0 -XHCI_FWM_SIZE=0 -endif - -ifeq ($(CONFIG_HUDSON_GEC_FWM), y) -HUDSON_GEC_POSITION=$(call int-add,$(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) $(CBFS_HEADER_SIZE) \ - $(XHCI_FWM_SIZE) $(CBFS_HEADER_SIZE)) -GEC_FWM_SIZE=$(call file-size,$(CONFIG_HUDSON_GEC_FWM_FILE)) -else -HUDSON_GEC_POSITION=0 -GEC_FWM_SIZE=0 -endif - -ifeq ($(CONFIG_HUDSON_IMC_FWM), y) -HUDSON_IMC_POSITION=$(call int-align,\ - $(call int-add,\ - $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) $(CBFS_HEADER_SIZE) $(XHCI_FWM_SIZE)\ - $(CBFS_HEADER_SIZE) $(GEC_FWM_SIZE) $(CBFS_HEADER_SIZE)),\ - 65536) -IMC_FWM_SIZE=$(call file-size,$(CONFIG_HUDSON_IMC_FWM_FILE)) -else -HUDSON_IMC_POSITION=0 -IMC_FWM_SIZE=0 -endif - -ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -HUDSON_PSP_DIRECTORY_POSITION=$(call int-align,\ - $(call int-add,\ - $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) $(CBFS_HEADER_SIZE) $(XHCI_FWM_SIZE)\ - $(CBFS_HEADER_SIZE) $(GEC_FWM_SIZE) $(CBFS_HEADER_SIZE) $(IMC_FWM_SIZE) $(CBFS_HEADER_SIZE)),\ - 65536) -HUDSON_PSP_DIRECTORY_SIZE=256 -else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -ifeq ($(CONFIG_HUDSON_IMC_FWM), y) -HUDSON_PSP_OFFSET=131072 -else -HUDSON_PSP_OFFSET=0 -endif -HUDSON_PSP_DIRECTORY_POSITION=$(call int-align,\ - $(call int-add,\ - $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) $(CBFS_HEADER_SIZE) $(XHCI_FWM_SIZE)\ - $(CBFS_HEADER_SIZE) $(GEC_FWM_SIZE) $(CBFS_HEADER_SIZE) $(IMC_FWM_SIZE) $(CBFS_HEADER_SIZE) $(HUDSON_PSP_OFFSET)),\ - 65536) -HUDSON_PSP_DIRECTORY_SIZE=256 -else -HUDSON_PSP_DIRECTORY_POSITION=0 -HUDSON_PSP_DIRECTORY_SIZE=0 -endif - -$(obj)/coreboot_hudson_romsig.bin: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ - $(obj)/config.h - echo " Hudson FW $@" - printf %d $(ROMSIG_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' > $@; \ - for fwm in 1437226410 \ - $(HUDSON_IMC_POSITION) \ - $(HUDSON_GEC_POSITION) \ - $(HUDSON_XHCI_POSITION) \ - $(HUDSON_PSP_DIRECTORY_POSITION); do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done > $@.tmp; \ - dd if=$@.tmp of=$@ conv=notrunc status=noxfer 2>/dev/null; \ - rm $@.tmp - -ifeq ($(CONFIG_HUDSON_FWM), y) -ifneq ($(HUDSON_FWM_POS_CALC), $(HUDSON_FWM_POSITION)) -$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION does not match calculated firmware position $(HUDSON_FWM_POS_CALC) != $(HUDSON_FWM_POSITION) ##### ) -endif -ifneq ($(HUDSON_FWM_INSIDE_CBFS), 1) -$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION ($(HUDSON_FWM_POSITION)) is outside of CBFS area ($(CBFS_BASE_ADDRESS) to 4294967295) ##### ) -endif -cbfs-files-y += fch/fwm -fch/fwm-file := $(obj)/coreboot_hudson_romsig.bin -fch/fwm-position := $(HUDSON_FWM_POSITION) -fch/fwm-size := $(ROMSIZE_SIG) -fch/fwm-type := raw -endif - -ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) -cbfs-files-y += fch/xhci -fch/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) -fch/xhci-position := $(HUDSON_XHCI_POSITION) -fch/xhci-type := raw -fch/xhci-required := Hudson XHCI firmware (available in coreboot/3rdparty/blobs if enabled) -endif - -ifeq ($(CONFIG_HUDSON_IMC_FWM), y) -cbfs-files-y += fch/imc -fch/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) -fch/imc-position := $(HUDSON_IMC_POSITION) -fch/imc-type := raw -fch/imc-required := Hudson IMC Firmware (available in coreboot/3rdparty/blobs if enabled) -endif - -ifeq ($(CONFIG_HUDSON_GEC_FWM), y) -cbfs-files-y += fch/gec -fch/gec-file := $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) -fch/gec-position := $(HUDSON_GEC_POSITION) -fch/gec-type := raw -fch/gec-required := Hudson Gigabit Ethernet Controller Firmware (Contact your AMD representative) -endif - -ifdef CONFIG_HUDSON_AHCI_ROM -stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID)) -cbfs-files-y += pci$(stripped_ahci_rom_id).rom -pci$(stripped_ahci_rom_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_ROM_FILE)) -pci$(stripped_ahci_rom_id).rom-type := optionrom -pci$(stripped_ahci_rom_id).rom-required := Hudson AHCI Option ROM (Contact your AMD representative) -endif - +## ifeq ($(CONFIG_HUDSON_PSP), y) +## +### 0 -# 0 -# catenate the pubkey and pspdir together to save some space. -AMDPUBKEY_POS=$(call int-add,$(HUDSON_PSP_DIRECTORY_POSITION) $(HUDSON_PSP_DIRECTORY_SIZE)) -AMDPUBKEY_SIZE=$(call file-size,$(CONFIG_AMD_PUBKEY_FILE)) - +## ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) FIRMWARE_TYPE= endif - +## ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) FIRMWARE_TYPE=CZ endif -#5 +###5 CONFIG_PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key -PUBSIGNEDKEY_POS=$(call int-align, \ - $(call int-add,$(AMDPUBKEY_POS) $(AMDPUBKEY_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -PUBSIGNEDKEY_SIZE=$(call file-size,$(CONFIG_PUBSIGNEDKEY_FILE)) - -#1 +###1 ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) CONFIG_PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader$(FIRMWARE_TYPE).Bypass.sbin else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) CONFIG_PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_$(FIRMWARE_TYPE).sbin endif -PSPBTLDR_POS=$(call int-align, \ - $(call int-add,$(PUBSIGNEDKEY_POS) $(PUBSIGNEDKEY_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -PSPBTLDR_SIZE=$(call file-size,$(CONFIG_PSPBTLDR_FILE)) -#3 +###3 ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) CONFIG_PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery$(FIRMWARE_TYPE).sbin else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) CONFIG_PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_$(FIRMWARE_TYPE).sbin endif -PSPRCVR_POS=$(call int-align, \ - $(call int-add,$(PSPBTLDR_POS) $(PSPBTLDR_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -PSPRCVR_SIZE=$(call file-size,$(CONFIG_PSPRCVR_FILE)) -#2 +###2 ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) CONFIG_PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs$(FIRMWARE_TYPE).sbin else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) CONFIG_PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).csbin endif -PSPSECUREOS_POS=$(call int-align, \ - $(call int-add,$(PSPRCVR_POS) $(PSPRCVR_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -PSPSECUREOS_SIZE=$(call file-size,$(CONFIG_PSPSCUREOS_FILE)) -#4 +###4 CONFIG_PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin -PSPNVRAM_POS=$(call int-align, \ - $(call int-add,$(PSPSECUREOS_POS) $(PSPSECUREOS_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -PSPNVRAM_SIZE=$(call file-size,$(CONFIG_PSPNVRAM_FILE)) -#8 +###8 CONFIG_SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin -SMUFWM_POS=$(call int-align, \ - $(call int-add,$(PSPNVRAM_POS) $(PSPNVRAM_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -SMUFWM_SIZE=$(call file-size,$(CONFIG_SMUFWM_FILE)) -#95 +###95 CONFIG_SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin -SMUSCS_POS=$(call int-align, \ - $(call int-add,$(SMUFWM_POS) $(SMUFWM_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -SMUSCS_SIZE=$(call file-size,$(CONFIG_SMUSCS_FILE)) -#9 +###9 CONFIG_PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key -PSPSECUREDEBUG_POS=$(call int-align, \ - $(call int-add,$(SMUSCS_POS) $(SMUSCS_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -PSPSECUREDEBUG_SIZE=$(call file-size,$(CONFIG_PSPSECUREDEBUG_FILE)) -#12 +###12 ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) CONFIG_PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) CONFIG_PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspTrustlets_prod_$(FIRMWARE_TYPE).cbin endif -PSPTRUSTLETS_POS=$(call int-align, \ - $(call int-add,$(PSPSECUREDEBUG_POS) $(PSPSECUREDEBUG_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -PSPTRUSTLETS_SIZE=$(call file-size,$(CONFIG_PSPTRUSTLETS_FILE)) -#13 +###13 ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) CONFIG_TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) CONFIG_TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_$(FIRMWARE_TYPE).sbin endif -TRUSTLETKEY_POS=$(call int-align, \ - $(call int-add,$(PSPTRUSTLETS_POS) $(PSPTRUSTLETS_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -TRUSTLETKEY_SIZE=$(call file-size,$(CONFIG_TRUSTLETKEY_FILE)) -#18 +###18 ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) CONFIG_SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin -SMUFIRMWARE2_POS=$(call int-align, \ - $(call int-add,$(TRUSTLETKEY_POS) $(TRUSTLETKEY_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -SMUFIRMWARE2_SIZE=$(call file-size,$(CONFIG_SMUFIRMWARE2_FILE)) endif -define output_hex -echo $(1) | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}' -endef - -$(obj)/coreboot_psp_directory.bin: $(obj)/config.h $(FLETCHER) $(RTM_FILE) - echo " PSPDir $@" - for fwm in 0 $(AMDPUBKEY_SIZE) $(AMDPUBKEY_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done > $(a)_tail.tmp - for fwm in 1 $(PSPBTLDR_SIZE) $(PSPBTLDR_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 8 $(SMUFWM_SIZE) $(SMUFWM_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 3 $(PSPRCVR_SIZE) $(PSPRCVR_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 5 $(PUBSIGNEDKEY_SIZE) $(PUBSIGNEDKEY_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 2 $(PSPSECUREOS_SIZE) $(PSPSECUREOS_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 4 $(PSPNVRAM_SIZE) $(PSPNVRAM_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 9 $(PSPSECUREDEBUG_SIZE) $(PSPSECUREDEBUG_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 12 $(PSPTRUSTLETS_SIZE) $(PSPTRUSTLETS_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 13 $(TRUSTLETKEY_SIZE) $(TRUSTLETKEY_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp -ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) - for fwm in 18 $(SMUFIRMWARE2_SIZE) $(SMUFIRMWARE2_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp -endif - for fwm in 95 $(SMUSCS_SIZE) $(SMUSCS_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 11 4294967295 1 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 1347637284 0 `ls -ln $(a)_tail.tmp | awk '{printf("%d", $$5/16);}'` 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done > $(a)_head.tmp - cat $(a)_head.tmp $(a)_tail.tmp > $@.tmp - $(FLETCHER) < $@.tmp > $@ - rm $(a)_head.tmp $(a)_tail.tmp $@.tmp - -$(obj)/coreboot_psp_directory_combine_pubkey.bin: $(obj)/coreboot_psp_directory.bin - cat $(obj)/coreboot_psp_directory.bin > $@ - ls -ln $(obj)/coreboot_psp_directory.bin | LC_ALL=C awk '{for (i=0; i<256-$$5; i++) {printf "%c", 255}}' >> $@ - cat $(top)/$(FIRMWARE_LOCATE)/AmdPubKey$(FIRMWARE_TYPE).bin >> $@ - -cbfs-files-y += apu/pspdir -apu/pspdir-file := $(obj)/coreboot_psp_directory_combine_pubkey.bin -apu/pspdir-position := $(HUDSON_PSP_DIRECTORY_POSITION) -apu/pspdir-type := raw - -# 5 -cbfs-files-y += apu/pubsignedkey -apu/pubsignedkey-file := $(CONFIG_PUBSIGNEDKEY_FILE) -apu/pubsignedkey-position := $(PUBSIGNEDKEY_POS) -apu/pubsignedkey-type := raw - -# 1 -cbfs-files-y += apu/pspbtldr -apu/pspbtldr-file := $(CONFIG_PSPBTLDR_FILE) -apu/pspbtldr-position := $(PSPBTLDR_POS) -apu/pspbtldr-type := raw - -#3 -cbfs-files-y += apu/psprcvr -apu/psprcvr-file := $(CONFIG_PSPRCVR_FILE) -apu/psprcvr-position := $(PSPRCVR_POS) -apu/psprcvr-type := raw - -# 2 -cbfs-files-y += apu/pspsecureos -apu/pspsecureos-file := $(CONFIG_PSPSCUREOS_FILE) -apu/pspsecureos-position := $(PSPSECUREOS_POS) -apu/pspsecureos-type := raw - -# 4 -cbfs-files-y += apu/pspnvram -apu/pspnvram-file := $(CONFIG_PSPNVRAM_FILE) -apu/pspnvram-position := $(PSPNVRAM_POS) -apu/pspnvram-type := raw - -#8 -cbfs-files-y += apu/smufwm -apu/smufwm-file := $(CONFIG_SMUFWM_FILE) -apu/smufwm-position := $(SMUFWM_POS) -apu/smufwm-type := raw - -#95 -cbfs-files-y += apu/smuscs -apu/smuscs-file := $(CONFIG_SMUSCS_FILE) -apu/smuscs-position := $(SMUSCS_POS) -apu/smuscs-type := raw - -#9 -cbfs-files-y += apu/pspsecuredebug -apu/pspsecuredebug-file := $(CONFIG_PSPSECUREDEBUG_FILE) -apu/pspsecuredebug-position := $(PSPSECUREDEBUG_POS) -apu/pspsecuredebug-type := raw - -#12 -cbfs-files-y += apu/psptrustlets -apu/psptrustlets-file := $(CONFIG_PSPTRUSTLETS_FILE) -apu/psptrustlets-position := $(PSPTRUSTLETS_POS) -apu/psptrustlets-type := raw - -#13 -cbfs-files-y += apu/trustletkey -apu/trustletkey-file := $(CONFIG_TRUSTLETKEY_FILE) -apu/trustletkey-position := $(TRUSTLETKEY_POS) -apu/trustletkey-type := raw - -#18 -ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -cbfs-files-y += apu/smufirmware2 -apu/smufirmware2-file := $(CONFIG_SMUFIRMWARE2_FILE) -apu/smufirmware2-position := $(SMUFIRMWARE2_POS) -apu/smufirmware2-type := raw endif -endif +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_HUDSON_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_XHCI_FWM_FILE), --xhci) +OPT_HUDSON_IMC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_IMC_FWM_FILE), --imc) +OPT_HUDSON_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_GEC_FWM_FILEddd), --gec) + +OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) +OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(CONFIG_PSPBTLDR_FILE), --bootloader) +OPT_SMUFWM_FILE=$(call add_opt_prefix, $(CONFIG_SMUFWM_FILE), --smufirmware) +OPT_PSPRCVR_FILE=$(call add_opt_prefix, $(CONFIG_PSPRCVR_FILE), --recovery) +OPT_PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(CONFIG_PUBSIGNEDKEY_FILE), --rtmpubkey) +OPT_PSPSCUREOS_FILE=$(call add_opt_prefix, $(CONFIG_PSPSCUREOS_FILE), --secureos) +OPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(CONFIG_PSPNVRAM_FILE), --nvram) +OPT_PSPSECUREDEBUG_FILE=$(call add_opt_prefix, $(CONFIG_PSPSECUREDEBUG_FILE), --securedebug) +OPT_PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(CONFIG_PSPTRUSTLETS_FILE), --trustlets) +OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(CONFIG_TRUSTLETKEY_FILE), --trustletkey) +OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(CONFIG_SMUFIRMWARE2_FILE), --smufirmware2) +OPT_SMUSCS_FILE=$(call add_opt_prefix, $(CONFIG_SMUSCS_FILE), --smuscs) + +#TODO: Set PSP2 Firmware. The setting below is just for testing. +#CONFIG_2AMD_PUBKEY_FILE =$(CONFIG_AMD_PUBKEY_FILE) +#CONFIG_2PSPBTLDR_FILE =$(CONFIG_PSPBTLDR_FILE) +#CONFIG_2SMUFWM_FILE =$(CONFIG_SMUFWM_FILE) +#CONFIG_2PSPRCVR_FILE =$(CONFIG_PSPRCVR_FILE) +#CONFIG_2PUBSIGNEDKEY_FILE =$(CONFIG_PUBSIGNEDKEY_FILE) +#CONFIG_2PSPSCUREOS_FILE =$(CONFIG_PSPSCUREOS_FILE) +#CONFIG_2PSPNVRAM_FILE =$(CONFIG_PSPNVRAM_FILE) +#CONFIG_2PSPSECUREDEBUG_FILE =$(CONFIG_PSPSECUREDEBUG_FILE) +#CONFIG_2PSPTRUSTLETS_FILE =$(CONFIG_PSPTRUSTLETS_FILE) +#CONFIG_2TRUSTLETKEY_FILE =$(CONFIG_TRUSTLETKEY_FILE) +#CONFIG_2SMUFIRMWARE2_FILE =$(CONFIG_SMUFIRMWARE2_FILE) +#CONFIG_2SMUSCS_FILE =$(CONFIG_SMUSCS_FILE) + +OPT_2AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_2AMD_PUBKEY_FILE), --pubkey2) +OPT_2PSPBTLDR_FILE=$(call add_opt_prefix, $(CONFIG_2PSPBTLDR_FILE), --bootloader2) +OPT_2SMUFWM_FILE=$(call add_opt_prefix, $(CONFIG_2SMUFWM_FILE), --smufirmware2) +OPT_2PSPRCVR_FILE=$(call add_opt_prefix, $(CONFIG_2PSPRCVR_FILE), --recovery2) +OPT_2PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(CONFIG_2PUBSIGNEDKEY_FILE), --rtmpubkey2) +OPT_2PSPSCUREOS_FILE=$(call add_opt_prefix, $(CONFIG_2PSPSCUREOS_FILE), --secureos2) +OPT_2PSPNVRAM_FILE=$(call add_opt_prefix, $(CONFIG_2PSPNVRAM_FILE), --nvram2) +OPT_2PSPSECUREDEBUG_FILE=$(call add_opt_prefix, $(CONFIG_2PSPSECUREDEBUG_FILE), --securedebug2) +OPT_2PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(CONFIG_2PSPTRUSTLETS_FILE), --trustlets2) +OPT_2TRUSTLETKEY_FILE=$(call add_opt_prefix, $(CONFIG_2TRUSTLETKEY_FILE), --trustletkey2) +OPT_2SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(CONFIG_2SMUFIRMWARE2_FILE), --smufirmware2_2) +OPT_2SMUSCS_FILE=$(call add_opt_prefix, $(CONFIG_2SMUSCS_FILE), --smuscs2) + +$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ + $(call strip_quotes, $(CONFIG_PUBSIGNEDKEY_FILE)) \ + $(call strip_quotes, $(CONFIG_PSPBTLDR_FILE)) \ + $(call strip_quotes, $(CONFIG_PSPRCVR_FILE)) \ + $(call strip_quotes, $(CONFIG_PSPSCUREOS_FILE)) \ + $(call strip_quotes, $(CONFIG_PSPNVRAM_FILE)) \ + $(call strip_quotes, $(CONFIG_SMUFWM_FILE)) \ + $(call strip_quotes, $(CONFIG_SMUSCS_FILE)) \ + $(call strip_quotes, $(CONFIG_PSPSECUREDEBUG_FILE)) \ + $(call strip_quotes, $(CONFIG_PSPTRUSTLETS_FILE)) \ + $(call strip_quotes, $(CONFIG_TRUSTLETKEY_FILE)) \ + $(call strip_quotes, $(CONFIG_SMUFIRMWARE2_FILE)) \ + $(AMDFWTOOL) + rm -f $@ + echo " AMDFWTOOL $@" + $(AMDFWTOOL) \ + $(OPT_HUDSON_XHCI_FWM_FILE) \ + $(OPT_HUDSON_IMC_FWM_FILE) \ + $(OPT_HUDSON_GEC_FWM_FILE) \ + $(OPT_AMD_PUBKEY_FILE) \ + $(OPT_PSPBTLDR_FILE) \ + $(OPT_SMUFWM_FILE) \ + $(OPT_PSPRCVR_FILE) \ + $(OPT_PUBSIGNEDKEY_FILE) \ + $(OPT_PSPSCUREOS_FILE) \ + $(OPT_PSPNVRAM_FILE) \ + $(OPT_PSPSECUREDEBUG_FILE) \ + $(OPT_PSPTRUSTLETS_FILE) \ + $(OPT_TRUSTLETKEY_FILE) \ + $(OPT_SMUFIRMWARE2_FILE) \ + $(OPT_SMUSCS_FILE) \ + $(OPT_2AMD_PUBKEY_FILE) \ + $(OPT_2PSPBTLDR_FILE) \ + $(OPT_2SMUFWM_FILE) \ + $(OPT_2PSPRCVR_FILE) \ + $(OPT_2PUBSIGNEDKEY_FILE) \ + $(OPT_2PSPSCUREOS_FILE) \ + $(OPT_2PSPNVRAM_FILE) \ + $(OPT_2PSPSECUREDEBUG_FILE) \ + $(OPT_2PSPTRUSTLETS_FILE) \ + $(OPT_2TRUSTLETKEY_FILE) \ + $(OPT_2SMUFIRMWARE2_FILE) \ + $(OPT_2SMUSCS_FILE) \ + --output $@ + +cbfs-files-y += apu/amdfw +apu/amdfw-file := $(obj)/amdfw.rom +apu/amdfw-position := $(HUDSON_FWM_POSITION) +apu/amdfw-type := raw

1 0

New patch to review for coreboot: [DO_NOT_SUBMIT]coreinfo: use coreboot crosscompiler
by Martin Roth 17 Nov '15

17 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12454 -gerrit commit 8ad117455120ce64c84f7c35d74461cf6cafb623 Author: Martin Roth <martinroth(a)google.com> Date: Mon Nov 16 22:33:48 2015 -0700 [DO_NOT_SUBMIT]coreinfo: use coreboot crosscompiler Initial pass at using the crosscompiler. Restrict to X86_32 GCC only. Change-Id: I1cc180a5eeaf6cb9a36fdcef70a9819d0f459168 Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/coreinfo/Makefile | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index 507e535..2ac0650 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -63,9 +63,36 @@ OBJECTS = cpuinfo_module.o cpuid.S.o pci_module.o coreboot_module.o \ OBJS = $(patsubst %,$(obj)/%,$(OBJECTS)) TARGET = $(obj)/coreinfo.elf +all: real-all + +# in addition to the dependency below, create the file if it doesn't exist +# to silence stupid warnings about a file that would be generated anyway. +$(if $(wildcard .xcompile),,$(eval $(shell ../../util/xcompile/xcompile $(XGCCPATH) > .xcompile))) + +.xcompile: ../../util/xcompile/xcompile + $< $(XGCCPATH) > $@.tmp + \mv -f $@.tmp $@ 2> /dev/null + +CONFIG_COMPILER_GCC := y +ARCH-y := x86_32 + +include .xcompile + +export CC := $(CC_$(ARCH-y)) +export AS := $(AS_$(ARCH-y)) +export LD := $(LD_$(ARCH-y)) +export NM := $(NM_$(ARCH-y)) +export OBJCOPY := $(OBJCOPY_$(ARCH-y)) +export OBJDUMP := $(OBJDUMP_$(ARCH-y)) +export READELF := $(READELF_$(ARCH-y)) +export STRIP := $(STRIP_$(ARCH-y)) +export AR := $(AR_$(ARCH-y)) + +export CFLAGS += $(CFLAGS_$(ARCH-y)) + ifneq ($(strip $(HAVE_DOTCONFIG)),) include $(src)/.config -all: $(TARGET) +real-all: $(TARGET) $(TARGET): $(src)/.config $(obj)/config.h $(OBJS) libpayload printf " LPCC $(subst $(shell pwd)/,,$(@)) (LINK)\n" @@ -83,7 +110,7 @@ $(obj)/%.o: $(src)/%.c libpayload $(LPCC) $(CFLAGS) -c -o $@ $< else -all: config +real-all: config endif ifneq ($(strip $(HAVE_LIBPAYLOAD)),)

1 0

Patch merged into coreboot/master: ifdtool: Makefile: fix install target
by gerrit＠coreboot.org 17 Nov '15

17 Nov '15

the following patch was just integrated into master: commit 46f7b0494f67d4784f633b5e8449fd6ae9f96483 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Wed Nov 11 05:54:55 2015 +0100 ifdtool: Makefile: fix install target ifdtool doesn't have a manual yet, so don't install an unexisting manual file. Change-Id: I290435de7de7177d803cf6cde4f4f42955cbcf5c Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-on: http://review.coreboot.org/12406 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12406 for details. -gerrit

1 0

Patch merged into coreboot/master: $(top)/Makefile: Strip the white space in function strip_quotes
by gerrit＠coreboot.org 17 Nov '15

17 Nov '15

the following patch was just integrated into master: commit 07648928ebe363be33f2a6b51b91a0c290f7951a Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Fri Nov 13 10:42:27 2015 +0800 $(top)/Makefile: Strip the white space in function strip_quotes Change-Id: I5e8cf2ccd1cd53b863cf8d24353428f3c183b68c Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/12434 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12434 for details. -gerrit

1 0

Patch set updated for coreboot: crossgcc: Update makefile builds
by Martin Roth 16 Nov '15

16 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12300 -gerrit commit 062f31f5c7aa2723ea003d6a4feca06de662d3e4 Author: Martin Roth <martinroth(a)google.com> Date: Tue Oct 27 15:03:46 2015 -0600 crossgcc: Update makefile builds - Only build IASL once for the 'all' targets instead of once for each. - Change the control of what gets built from different targets to variables on the build line. - Clean up and correct the list of phony targets - Don't keep the temporary files around while building all. This takes up a lot of space. If it's desired behavior, add BUILDGCC_OPTIONS=-t on the make command line. - Add comments about CPU= and BUILDGCC_OPTIONS= variables - Add KEEP_SOURCES option Change-Id: I7752974e249f25717b42be25a841c69af84d5c69 Signed-off-by: Martin Roth <martinroth(a)google.com> --- Makefile.inc | 21 ++++++++++------ util/crossgcc/Makefile | 66 +++++++++++++++++++++----------------------------- 2 files changed, 41 insertions(+), 46 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index b85a2cb..4666179 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -442,28 +442,33 @@ gitconfig: git config remote.origin.push HEAD:refs/for/master (git config --global user.name >/dev/null && git config --global user.email >/dev/null) || (printf 'Please configure your name and email in git:\n\n git config --global user.name "Your Name Comes Here"\n git config --global user.email your.email(a)example.com\n'; exit 1) -crossgcc: crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 crossgcc-mips crossgcc-riscv +# For the toolchain builds, use CPUS=x to use multiple processors to build +# use BUILDGCC_OPTIONS= to set any crossgcc command line options +# Example: BUILDGCC_OPTIONS='-t' will keep temporary files after build +crossgcc: + $(MAKE) -C util/crossgcc all_without_gdb SKIP_CLANG=1 .PHONY: crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 crossgcc-mips crossgcc-riscv crossgcc-i386: clean-for-update - $(MAKE) -C util/crossgcc build-i386-without-gdb + $(MAKE) -C util/crossgcc build-i386 SKIP_GDB=1 crossgcc-x64: clean-for-update - $(MAKE) -C util/crossgcc build-x64-without-gdb + $(MAKE) -C util/crossgcc build-x64 SKIP_GDB=1 crossgcc-arm: clean-for-update - $(MAKE) -C util/crossgcc build-armv7a-without-gdb + $(MAKE) -C util/crossgcc build-armv7a SKIP_GDB=1 crossgcc-aarch64: clean-for-update - $(MAKE) -C util/crossgcc build-aarch64-without-gdb + $(MAKE) -C util/crossgcc build-aarch64 SKIP_GDB=1 crossgcc-mips: clean-for-update - $(MAKE) -C util/crossgcc build-mips-without-gdb + $(MAKE) -C util/crossgcc build-mips SKIP_GDB=1 crossgcc-riscv: clean-for-update - $(MAKE) -C util/crossgcc build-riscv-without-gdb + $(MAKE) -C util/crossgcc build-riscv SKIP_GDB=1 -crosstools: crosstools-i386 crosstools-x64 crosstools-arm crosstools-aarch64 crosstools-mips crosstools-riscv +crosstools: + $(MAKE) -C util/crossgcc all_with_gdb SKIP_CLANG=1 .PHONY: crosstools-i386 crosstools-x64 crosstools-arm crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-i386: clean-for-update diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 1f1dc1f..152115c 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -1,38 +1,48 @@ # if no architecture is specified, set a default BUILD_PLATFORM ?= i386-elf -all: - $(MAKE) BUILDGCC_OPTIONS=-t build-i386 build-x64 build-armv7a build-mips build-riscv build-aarch64 \ - build_clang - $(MAKE) clean_tempfiles +# For the toolchain builds, use CPUS=x to use multiple processors to build +# use KEEP_SOURCES=1 to keep temporary files after the build +# use BUILDGCC_OPTIONS= to set any other crossgcc command line options +# Example: BUILDGCC_OPTIONS=-c to remove temporary files before build + +all all_with_gdb: + $(MAKE) build-i386 + $(MAKE) SKIP_IASL=1 \ + build-x64 build-armv7a build-mips build-riscv build-aarch64 \ + build_clang all_without_gdb: - $(MAKE) BUILDGCC_OPTIONS=-t build-i386-without-gdb build-x64-without-gdb build-armv7a-without-gdb \ - build-mips-without-gdb build-riscv-without-gdb build-aarch64-without-gdb build_clang - $(MAKE) clean_tempfiles + $(MAKE) SKIP_GDB=1 build-i386 + $(MAKE) SKIP_IASL=1 SKIP_GDB=1 \ + build-x64 build-armv7a build-mips build-riscv build-aarch64 \ + build_clang build_tools: build_gcc build_iasl build_gdb -build_tools_without_gdb: build_gcc build_iasl - ########################################################### ### targets to do buildgcc builds build_gcc: - bash ./buildgcc -p $(BUILD_PLATFORM) $(if $(CPUS),-j $(CPUS)) $(BUILDGCC_OPTIONS) \ + bash ./buildgcc -p $(BUILD_PLATFORM) $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) \ $(if $(BUILD_LANGUAGES),-l $(BUILD_LANGUAGES)) build_gdb: - bash ./buildgcc -p $(BUILD_PLATFORM) -P gdb $(if $(CPUS),-j $(CPUS)) $(BUILDGCC_OPTIONS) +ifeq ($(SKIP_GDB),) + bash ./buildgcc -p $(BUILD_PLATFORM) -P gdb $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) +endif build_iasl: - bash ./buildgcc -P iasl $(if $(CPUS),-j $(CPUS)) $(BUILDGCC_OPTIONS) +ifeq ($(SKIP_IASL),) + bash ./buildgcc -P iasl $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) +endif build_clang: - bash ./buildgcc -P clang $(if $(CPUS),-j $(CPUS)) $(BUILDGCC_OPTIONS) +ifeq ($(SKIP_CLANG),) + bash ./buildgcc -P clang $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) +endif ########################################################### -### Build with GDB ### build-i386: @$(MAKE) build_tools BUILD_PLATFORM=i386-elf @@ -51,26 +61,6 @@ build-mips: build-riscv: @$(MAKE) build_tools BUILD_PLATFORM=riscv-elf -########################################################### -### Build without GDB -build-i386-without-gdb: - @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=i386-elf - -build-x64-without-gdb: - @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=x86_64-elf - -build-armv7a-without-gdb: - @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=armv7a-eabi - -build-aarch64-without-gdb: - @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=aarch64-elf - -build-mips-without-gdb: - @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=mipsel-elf - -build-riscv-without-gdb: - @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=riscv-elf - clean_tempfiles: rm -rf build-* rm -rf binutils-* gcc-* gmp-* libelf-* mpc-* mpfr-* @@ -85,7 +75,7 @@ clean: clean_tempfiles distclean: clean rm -rf tarballs -.PHONY: build_gcc build_iasl build_gdb build_tools build_tools_without_gdb \ - build-i386-without-gdb build-x64-without-gdb build-armv7a-without-gdb \ - build-aarch64-without-gdb build-mips-without-gdb build-riscv-without-gdb \ - all build clean distclean clean_tempfiles all_without_gdb +.PHONY: build_gcc build_iasl build_gdb build_clang \ + all all_with_gdb all_without_gdb build_tools \ + build-i386 build-x64 build-armv7a build-aarch64 build-mips build-riscv \ + clean distclean clean_tempfiles

1 0

Patch merged into coreboot/master: fsp_baytrail: use external microcode .h files
by gerrit＠coreboot.org 16 Nov '15

16 Nov '15

the following patch was just integrated into master: commit 0307e0a4990445d32ee637921dab245554a94c3f Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 5 08:06:54 2015 -0700 fsp_baytrail: use external microcode .h files The microcode for Bay Trail that's in the blobs repo is for the M and D chip variants only. The fsp_baytrail directory is for Bay Trail I chip variants, and will not boot if the M/D microcode is used. The microcode for the I variant is supplied as part of the Bay Trail FSP package. Change-Id: I5493deb1626dc3cf037053e13e092f5a1143a13a Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: http://review.coreboot.org/12334 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/12334 for details. -gerrit

1 0

Patch set updated for coreboot: arm64: tegra132: tegra210: Remove old arm64/stage_entry.S
by Julius Werner 16 Nov '15

16 Nov '15

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12078 -gerrit commit 7503f5230c5d110536b911f812f064fbdf54531e Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Oct 16 13:10:02 2015 -0700 arm64: tegra132: tegra210: Remove old arm64/stage_entry.S This patch removes the old arm64/stage_entry.S code that was too specific to the Tegra SoC boot flow, and replaces it with code that hides the peculiarities of switching to a different CPU/arch in ramstage in the Tegra SoC directories. BRANCH=None BUG=None TEST=Built Ryu and Smaug. !!!UNTESTED!!! Change-Id: Ib3a0448b30ac9c7132581464573efd5e86e03698 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- src/arch/arm64/Kconfig | 1 - src/arch/arm64/Makefile.inc | 13 +-- src/arch/arm64/armv8/bootblock.S | 19 +-- src/arch/arm64/armv8/cpu.S | 15 ++- src/arch/arm64/armv8/exception.c | 1 - src/arch/arm64/boot.c | 2 - src/arch/arm64/c_entry.c | 128 --------------------- src/arch/arm64/cpu-internal.h | 25 ---- src/arch/arm64/cpu-stubs.c | 21 ---- src/arch/arm64/cpu/Kconfig | 19 --- src/arch/arm64/cpu/Makefile.inc | 20 ---- src/arch/arm64/cpu/cortex_a57.S | 25 ---- src/arch/arm64/include/arch/memlayout.h | 5 - src/arch/arm64/include/arch/stages.h | 5 - src/arch/arm64/include/armv8/arch/cpu.h | 12 -- src/arch/arm64/include/armv8/arch/lib_helpers.h | 8 +- src/arch/arm64/transition.c | 41 ++++--- src/lib/Makefile.inc | 1 + src/soc/nvidia/tegra132/Kconfig | 9 -- src/soc/nvidia/tegra132/Makefile.inc | 1 + src/soc/nvidia/tegra132/include/soc/memlayout.ld | 7 +- .../tegra132/include/soc/memlayout_vboot2.ld | 9 +- src/soc/nvidia/tegra132/maincpu.S | 55 --------- src/soc/nvidia/tegra132/ramstage.c | 12 +- src/soc/nvidia/tegra132/romstage.c | 5 + src/soc/nvidia/tegra132/stage_entry.S | 24 ++++ src/soc/nvidia/tegra210/Kconfig | 10 -- src/soc/nvidia/tegra210/cpu.c | 2 +- src/soc/nvidia/tegra210/include/soc/memlayout.ld | 7 +- .../tegra210/include/soc/memlayout_vboot2.ld | 9 +- src/soc/nvidia/tegra210/maincpu.S | 55 --------- src/soc/nvidia/tegra210/ramstage.c | 17 ++- src/soc/nvidia/tegra210/romstage.c | 5 + src/soc/nvidia/tegra210/stage_entry.S | 12 +- 34 files changed, 143 insertions(+), 457 deletions(-) diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index 9b06589..21bbc9b 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -20,7 +20,6 @@ config ARCH_RAMSTAGE_ARM64 default n source src/arch/arm64/armv8/Kconfig -source src/arch/arm64/cpu/Kconfig config ARM64_USE_ARM_TRUSTED_FIRMWARE bool diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 21fda04..1cbc9a4 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -23,7 +23,7 @@ # Take care of subdirectories ################################################################################ -subdirs-y += armv8/ cpu/ +subdirs-y += armv8/ ################################################################################ # ARM specific options @@ -44,8 +44,6 @@ bootblock-y += id.S $(obj)/arch/arm64/id.bootblock.o: $(obj)/build.h bootblock-y += boot.c -bootblock-y += c_entry.c -bootblock-y += cpu-stubs.c bootblock-y += eabi_compat.c bootblock-y += transition.c transition_asm.S @@ -87,8 +85,6 @@ endif # CONFIG_ARCH_VERSTAGE_ARM64 ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM64),y) romstage-y += boot.c -romstage-y += c_entry.c -romstage-y += cpu-stubs.c romstage-y += div0.c romstage-y += eabi_compat.c romstage-y += memset.S @@ -113,7 +109,6 @@ endif # CONFIG_ARCH_ROMSTAGE_ARM64 ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM64),y) -ramstage-y += c_entry.c ramstage-y += div0.c ramstage-y += eabi_compat.c ramstage-y += boot.c @@ -121,15 +116,9 @@ ramstage-y += tables.c ramstage-y += memset.S ramstage-y += memcpy.S ramstage-y += memmove.S -ramstage-y += cpu-stubs.c ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += arm_tf.c ramstage-y += transition.c transition_asm.S -# TODO: Replace this with a simpler ramstage entry point in soc/nvidia/tegra* -ifeq ($(CONFIG_SOC_NVIDIA_TEGRA132)$(CONFIG_SOC_NVIDIA_TEGRA210),y) -ramstage-y += stage_entry.S -endif - rmodules_arm64-y += memset.S rmodules_arm64-y += memcpy.S rmodules_arm64-y += memmove.S diff --git a/src/arch/arm64/armv8/bootblock.S b/src/arch/arm64/armv8/bootblock.S index 4a9fea9..e5758bc 100644 --- a/src/arch/arm64/armv8/bootblock.S +++ b/src/arch/arm64/armv8/bootblock.S @@ -16,21 +16,14 @@ #include <arch/asm.h> +/* NOTE: When making changes to general ARM64 initialization, keep in mind that + * there are other CPU entry points, using BOOTBLOCK_CUSTOM or entering the CPU + * in a later stage (like Tegra). Changes should generally be put into + * arm64_cpu_init so they can be shared between those instances. */ + ENTRY(_start) - /* Initialize PSTATE, SCTLR and caches to clean state. */ + /* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */ bl arm64_init_cpu - /* Initialize stack with sentinel value to later check overflow. */ - ldr x0, =_stack - ldr x1, =_estack - ldr x2, =0xdeadbeefdeadbeef -stack_init_loop: - stp x2, x2, [x0], #16 - cmp x0, x1 - bne stack_init_loop - - /* Leave a line of beef dead for easier visibility in stack dumps. */ - sub sp, x0, #16 - bl main ENDPROC(_start) diff --git a/src/arch/arm64/armv8/cpu.S b/src/arch/arm64/armv8/cpu.S index 4713ca5..711c338 100644 --- a/src/arch/arm64/armv8/cpu.S +++ b/src/arch/arm64/armv8/cpu.S @@ -21,7 +21,8 @@ * Bring an ARMv8 processor we just gained control of (e.g. from IROM) into a * known state regarding caches/SCTLR/PSTATE. Completely cleans and invalidates * icache/dcache, disables MMU and dcache (if active), and enables unaligned - * accesses, icache and branch prediction (if inactive). Clobbers R22 and R23. + * accesses, icache and branch prediction (if inactive). Seeds the stack and + * initializes SP_EL0. Clobbers R22 and R23. */ ENTRY(arm64_init_cpu) /* Initialize PSTATE (unmask all exceptions, select SP_EL0). */ @@ -60,5 +61,17 @@ ENTRY(arm64_init_cpu) dsb sy isb + /* Initialize stack with sentinel value to later check overflow. */ + ldr x2, =0xdeadbeefdeadbeef + ldr x0, =_stack + ldr x1, =_estack +1: + stp x2, x2, [x0], #16 + cmp x0, x1 + bne 1b + + /* Leave a line of beef dead for easier visibility in stack dumps. */ + sub sp, x0, #16 + ret x23 ENDPROC(arm64_init_cpu) diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index 35e3f7f..b872a55 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -166,7 +166,6 @@ void exc_dispatch(struct exc_state *state, uint64_t idx) exc_exit(&state->regs); } - static int test_exception_handler(struct exc_state *state, uint64_t vector_id) { /* Update instruction pointer to next instrution. */ diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 1012d97..c996d50 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -72,10 +72,8 @@ void arch_prog_run(struct prog *prog) doit(prog_entry_arg(prog)); } -#if !IS_ENABLED(CONFIG_SOC_NVIDIA_TEGRA132) /* Generic stage entry point. Can be overridden by board/SoC if needed. */ __attribute__((weak)) void stage_entry(void) { main(); } -#endif diff --git a/src/arch/arm64/c_entry.c b/src/arch/arm64/c_entry.c deleted file mode 100644 index f26ed92..0000000 --- a/src/arch/arm64/c_entry.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cache.h> -#include <arch/cpu.h> -#include <arch/lib_helpers.h> -#include <arch/mmu.h> -#include <arch/stages.h> -#include <gic.h> - -#include "cpu-internal.h" - -void __attribute__((weak)) arm64_soc_init(void) -{ - /* Default weak implementation does nothing. */ -} - -static void seed_stack(void) -{ - char *stack_begin; - uint64_t *slot; - int i; - int size; - - stack_begin = cpu_get_stack(); - stack_begin -= CONFIG_STACK_SIZE; - slot = (void *)stack_begin; - - /* Pad out 256 bytes for current usage. */ - size = CONFIG_STACK_SIZE - 256; - size /= sizeof(*slot); - for (i = 0; i < size; i++) - *slot++ = 0xdeadbeefdeadbeefULL; -} - -/* Set up default SCR values. */ -static void el3_init(void) -{ - uint32_t scr; - - if (get_current_el() != EL3) - return; - - scr = raw_read_scr_el3(); - /* Default to non-secure EL1 and EL0. */ - scr &= ~(SCR_NS_MASK); - scr |= SCR_NS_ENABLE; - /* Disable IRQ, FIQ, and external abort interrupt routing. */ - scr &= ~(SCR_IRQ_MASK | SCR_FIQ_MASK | SCR_EA_MASK); - scr |= SCR_IRQ_DISABLE | SCR_FIQ_DISABLE | SCR_EA_DISABLE; - /* Enable HVC */ - scr &= ~(SCR_HVC_MASK); - scr |= SCR_HVC_ENABLE; - /* Disable SMC */ - scr &= ~(SCR_SMC_MASK); - scr |= SCR_SMC_DISABLE; - /* Disable secure instruction fetches. */ - scr &= ~(SCR_SIF_MASK); - scr |= SCR_SIF_DISABLE; - /* All lower exception levels 64-bit by default. */ - scr &= ~(SCR_RW_MASK); - scr |= SCR_LOWER_AARCH64; - /* Disable secure EL1 access to secure timer. */ - scr &= ~(SCR_ST_MASK); - scr |= SCR_ST_DISABLE; - /* Don't trap on WFE or WFI instructions. */ - scr &= ~(SCR_TWI_MASK | SCR_TWE_MASK); - scr |= SCR_TWI_DISABLE | SCR_TWE_DISABLE; - raw_write_scr_el3(scr); - isb(); -} - -void __attribute__((weak)) arm64_arch_timer_init(void) -{ - /* Default weak implementation does nothing. */ -} - -static void arm64_init(void) -{ - seed_stack(); - - /* Set up default SCR values. */ - el3_init(); - - /* Initialize the GIC. */ - gic_init(); - - /* - * Disable coprocessor traps to EL3: - * TCPAC [20] = 0, disable traps for EL2 accesses to CPTR_EL2 or HCPTR - * and EL2/EL1 access to CPACR_EL1. - * TTA [20] = 0, disable traps for trace register access from any EL. - * TFP [10] = 0, disable traps for floating-point instructions from any - * EL. - */ - raw_write_cptr_el3(CPTR_EL3_TCPAC_DISABLE | CPTR_EL3_TTA_DISABLE | - CPTR_EL3_TFP_DISABLE); - - /* - * Allow FPU accesses: - * FPEN [21:20] = 3, disable traps for floating-point instructions from - * EL0/EL1. - * TTA [28] = 0, disable traps for trace register access from EL0/EL1. - */ - raw_write_cpacr_el1(CPACR_TRAP_FP_DISABLE | CPACR_TTA_DISABLE); - - /* Arch Timer init: setup cntfrq per CPU */ - arm64_arch_timer_init(); - - arm64_soc_init(); - - main(); -} - -/* This variable holds entry point for CPU starting up. */ -void (*c_entry)(void) = &arm64_init; diff --git a/src/arch/arm64/cpu-internal.h b/src/arch/arm64/cpu-internal.h deleted file mode 100644 index 75d2d4d..0000000 --- a/src/arch/arm64/cpu-internal.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ARCH_CPU_INTERNAL_H -#define ARCH_CPU_INTERNAL_H - -/* Return the top of the stack for the cpu. */ -void *cpu_get_stack(void); - -/* Return the top of the exception stack for the cpu. */ -void *cpu_get_exception_stack(void); - -#endif /* ARCH_CPU_INTERNAL_H */ diff --git a/src/arch/arm64/cpu-stubs.c b/src/arch/arm64/cpu-stubs.c deleted file mode 100644 index 1a61872..0000000 --- a/src/arch/arm64/cpu-stubs.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -void arm64_cpu_early_setup(void); - -void __attribute__((weak)) arm64_cpu_early_setup(void) -{ - /* Default empty implementation */ -} diff --git a/src/arch/arm64/cpu/Kconfig b/src/arch/arm64/cpu/Kconfig deleted file mode 100644 index 21526e6..0000000 --- a/src/arch/arm64/cpu/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2015 Google Inc -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config ARCH_ARM64_CPU_CORTEX_A57 - bool - default n - depends on ARCH_ARM64 diff --git a/src/arch/arm64/cpu/Makefile.inc b/src/arch/arm64/cpu/Makefile.inc deleted file mode 100644 index 4b249c7..0000000 --- a/src/arch/arm64/cpu/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -################################################################################ -## -## This file is part of the coreboot project. -## -## Copyright 2015 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -################################################################################ - -ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM64),y) -ramstage-$(CONFIG_ARCH_ARM64_CPU_CORTEX_A57) += cortex_a57.S -endif diff --git a/src/arch/arm64/cpu/cortex_a57.S b/src/arch/arm64/cpu/cortex_a57.S deleted file mode 100644 index 80707ca..0000000 --- a/src/arch/arm64/cpu/cortex_a57.S +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/asm.h> -#include <cpu/cortex_a57.h> - -ENTRY(arm64_cpu_early_setup) - mrs x0, CPUECTLR_EL1 - orr x0, x0, #(1 << SMPEN_SHIFT) - msr CPUECTLR_EL1, x0 - isb - ret -ENDPROC(arm64_cpu_early_setup) diff --git a/src/arch/arm64/include/arch/memlayout.h b/src/arch/arm64/include/arch/memlayout.h index 6db67a9..0bd0835 100644 --- a/src/arch/arm64/include/arch/memlayout.h +++ b/src/arch/arm64/include/arch/memlayout.h @@ -23,13 +23,8 @@ _ = ASSERT(size % 4K == 0, "TTB size must be divisible by 4K!"); /* ARM64 stacks need 16-byte alignment. */ -#if !(IS_ENABLED(CONFIG_SOC_NVIDIA_TEGRA132) || \ - IS_ENABLED(CONFIG_SOC_NVIDIA_TEGRA210)) #define STACK(addr, size) \ REGION(stack, addr, size, 16) \ _ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.inc"); -#else /* Hack around old Tegra stage_entry.S implementation. TODO: remove */ -#define STACK(addr, size) REGION(preram_stack, addr, size, 16) -#endif #endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/arm64/include/arch/stages.h b/src/arch/arm64/include/arch/stages.h index 0d6606f..6dbf389 100644 --- a/src/arch/arm64/include/arch/stages.h +++ b/src/arch/arm64/include/arch/stages.h @@ -24,9 +24,4 @@ void stage_entry(void); void stage_exit(void *); void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size); -/* This function is called upon initial entry of each stage. It is called prior - * to main(). That means all of the common infrastructure will most likely not - * be available to be used (such as console). */ -void arm64_soc_init(void); - #endif diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h index fdc34e5..6e096cc 100644 --- a/src/arch/arm64/include/armv8/arch/cpu.h +++ b/src/arch/arm64/include/armv8/arch/cpu.h @@ -20,18 +20,6 @@ static inline unsigned int smp_processor_id(void) { return 0; } -/* - * The arm64_cpu_startup() initializes CPU's exception stack and regular - * stack as well initializing the C environment for the processor. Finally it - * calls into c_entry. - */ -void arm64_cpu_startup(void); - -/* - * The arm64_arch_timer_init() initializes the CPU's cntfrq register of - * ARM arch timer. - */ -void arm64_arch_timer_init(void); #if !defined(__PRE_RAM__) struct cpu_driver { }; diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h index 6dd33b3..51a754a 100644 --- a/src/arch/arm64/include/armv8/arch/lib_helpers.h +++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h @@ -58,10 +58,10 @@ #define SCR_EA_MASK (1 << SCR_EA_SHIFT) #define SCR_EA_ENABLE (1 << SCR_EA_SHIFT) #define SCR_EA_DISABLE (0 << SCR_EA_SHIFT) -#define SCR_SMC_SHIFT 7 -#define SCR_SMC_MASK (1 << SCR_SMC_SHIFT) -#define SCR_SMC_DISABLE (1 << SCR_SMC_SHIFT) -#define SCR_SMC_ENABLE (0 << SCR_SMC_SHIFT) +#define SCR_SMD_SHIFT 7 +#define SCR_SMD_MASK (1 << SCR_SMD_SHIFT) +#define SCR_SMD_DISABLE (1 << SCR_SMD_SHIFT) +#define SCR_SMD_ENABLE (0 << SCR_SMD_SHIFT) #define SCR_HVC_SHIFT 8 #define SCR_HVC_MASK (1 << SCR_HVC_SHIFT) #define SCR_HVC_DISABLE (0 << SCR_HVC_SHIFT) diff --git a/src/arch/arm64/transition.c b/src/arch/arm64/transition.c index 3900421..9edc011 100644 --- a/src/arch/arm64/transition.c +++ b/src/arch/arm64/transition.c @@ -13,8 +13,10 @@ * GNU General Public License for more details. */ +#include <arch/cache.h> #include <arch/lib_helpers.h> #include <arch/transition.h> +#include <assert.h> #include <console/console.h> /* Litte-endian, No XN-forced, Instr cache disabled, @@ -66,8 +68,6 @@ void transition_with_entry(void *entry, void *arg, struct exc_state *exc_state) void transition(struct exc_state *exc_state) { - uint32_t scr_mask; - uint64_t hcr_mask; uint64_t sctlr; uint32_t current_el = get_current_el(); @@ -89,23 +89,27 @@ void transition(struct exc_state *exc_state) if (elx->spsr & SPSR_ERET_32) die("ARM64 Error: Do not support eret to Aarch32\n"); - else { - scr_mask = SCR_LOWER_AARCH64; - hcr_mask = HCR_LOWER_AARCH64; - } - /* SCR: Write to SCR if current EL is EL3 */ - if (current_el == EL3) { - uint32_t scr = raw_read_scr_el3(); - scr |= scr_mask; - raw_write_scr_el3(scr); - } - /* HCR: Write to HCR if current EL is EL2 */ - else if (current_el == EL2) { - uint64_t hcr = raw_read_hcr_el2(); - hcr |= hcr_mask; - raw_write_hcr_el2(hcr); - } + /* Most parts of coreboot currently don't support EL2 anyway. */ + assert(current_el == EL3); + + /* Initialize SCR with defaults for running without secure monitor. */ + raw_write_scr_el3(SCR_TWE_DISABLE | /* don't trap WFE */ + SCR_TWI_DISABLE | /* don't trap WFI */ + SCR_ST_ENABLE | /* allow secure timer access */ + SCR_LOWER_AARCH64 | /* lower level is AArch64 */ + SCR_SIF_DISABLE | /* disable secure ins. fetch */ + SCR_HVC_ENABLE | /* allow HVC instruction */ + SCR_SMD_ENABLE | /* disable SMC instruction */ + SCR_RES1 | /* reserved-1 bits */ + SCR_EA_DISABLE | /* disable ext. abort trap */ + SCR_FIQ_DISABLE | /* disable FIQ trap to EL3 */ + SCR_IRQ_DISABLE | /* disable IRQ trap to EL3 */ + SCR_NS_ENABLE); /* lower level is non-secure */ + + /* Initialize CPTR to not trap anything to EL3. */ + raw_write_cptr_el3(CPTR_EL3_TCPAC_DISABLE | CPTR_EL3_TTA_DISABLE | + CPTR_EL3_TFP_DISABLE); /* ELR/SPSR: Write entry point and processor state of program */ raw_write_elr_current(elx->elr); @@ -118,6 +122,7 @@ void transition(struct exc_state *exc_state) /* SP_ELx: Initialize stack pointer */ raw_write_sp_elx(elx->sp_elx, elx_el); + isb(); /* Eret to the entry point */ trans_switch(regs); diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index c6e2a53..59b1317 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -84,6 +84,7 @@ romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c +romstage-y += stack.c ifeq ($(CONFIG_EARLY_CBMEM_INIT),y) romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index 8473d4a..04d5783 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -17,11 +17,6 @@ config SOC_NVIDIA_TEGRA132 if SOC_NVIDIA_TEGRA132 -# TODO: Remove after replacing arch/arm64/stage_entry.S -config STACK_SIZE - hex - default 0x1000 - config MAINBOARD_DO_DSI_INIT bool "Use dsi graphics interface" depends on MAINBOARD_DO_NATIVE_VGA_INIT @@ -36,10 +31,6 @@ config MAINBOARD_DO_SOR_INIT help Initialize dp display -config MAX_CPUS - int - default 2 - config MTS_DIRECTORY string "Directory where MTS microcode files are located" default "3rdparty/blobs/cpu/nvidia/tegra132/current/prod" diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 22ccba5..b48fd3a 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -90,6 +90,7 @@ ramstage-y += ramstage.c ramstage-y += mmu_operations.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += ../tegra/usb.c +ramstage-y += stage_entry.S modules_arm-y += monotonic_timer.c diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout.ld b/src/soc/nvidia/tegra132/include/soc/memlayout.ld index d403c17..aad3083 100644 --- a/src/soc/nvidia/tegra132/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra132/include/soc/memlayout.ld @@ -14,6 +14,7 @@ */ #include <memlayout.h> +#include <rules.h> #include <arch/header.ld> @@ -29,7 +30,11 @@ SECTIONS SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 8K) PRERAM_CBFS_CACHE(0x40002000, 84K) - STACK(0x40017000, 14K) +#if ENV_ARM64 + STACK(0x40017000, 8K) +#else /* AVP gets a separate stack to avoid any chance of handoff races. */ + STACK(0x40019000, 6K) +#endif TIMESTAMP(0x4001A800, 2K) BOOTBLOCK(0x4001B800, 22K) ROMSTAGE(0x40021000, 124K) diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld index 7a6a168..e3d221e 100644 --- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld @@ -14,6 +14,7 @@ */ #include <memlayout.h> +#include <rules.h> #include <arch/header.ld> @@ -29,8 +30,12 @@ SECTIONS SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 8K) PRERAM_CBFS_CACHE(0x40002000, 72K) - VBOOT2_WORK(0x40014000, 16K) - STACK(0x40018000, 2K) + VBOOT2_WORK(0x40014000, 12K) +#if ENV_ARM64 + STACK(0x40017000, 3K) +#else /* AVP gets a separate stack to avoid any chance of handoff races. */ + STACK(0x40017C00, 3K) +#endif TIMESTAMP(0x40018800, 2K) BOOTBLOCK(0x40019000, 22K) VERSTAGE(0x4001e800, 55K) diff --git a/src/soc/nvidia/tegra132/maincpu.S b/src/soc/nvidia/tegra132/maincpu.S deleted file mode 100644 index 898d821..0000000 --- a/src/soc/nvidia/tegra132/maincpu.S +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <arch/asm.h> - -ENTRY(maincpu_setup) - /* - * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data - * aborts may happen early and crash before the abort handlers are - * installed, but at least the problem will show up near the code that - * causes it. - */ - msr cpsr, #0xdf - - ldr sp, maincpu_stack_pointer - eor lr, lr - ldr r0, maincpu_entry_point - bx r0 -ENDPROC(maincpu_setup) - - .align 2 - - .global maincpu_stack_pointer -maincpu_stack_pointer: - .word 0 - - .global maincpu_entry_point -maincpu_entry_point: - .word 0 diff --git a/src/soc/nvidia/tegra132/ramstage.c b/src/soc/nvidia/tegra132/ramstage.c index ca9cec4..fec31c4 100644 --- a/src/soc/nvidia/tegra132/ramstage.c +++ b/src/soc/nvidia/tegra132/ramstage.c @@ -14,6 +14,7 @@ */ #include <arch/stages.h> +#include <gic.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/mc.h> @@ -28,8 +29,14 @@ static void lock_down_vpr(void) write32(&regs->video_protect_reg_ctrl, 1); } -void arm64_soc_init(void) +/* Tegra-specific entry point, called from assembly in stage_entry.S */ +void ramstage_entry(void); +void ramstage_entry(void) { + /* TODO: Is this still needed? */ + gic_init(); + + /* TODO: Move TrustZone setup to BL31? */ trustzone_region_init(); tegra132_mmu_init(); @@ -40,4 +47,7 @@ void arm64_soc_init(void) /* Lock down VPR */ lock_down_vpr(); + + /* Jump to boot state machine in common code. */ + main(); } diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index a6753b3..3b45aff 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -19,6 +19,7 @@ #include <cbmem.h> #include <console/cbmem_console.h> #include <console/console.h> +#include <lib.h> #include <program_loading.h> #include <soc/addressmap.h> #include <soc/ccplex.h> @@ -26,6 +27,7 @@ #include <soc/sdram.h> #include <soc/sdram_configs.h> #include <soc/romstage.h> +#include <symbols.h> #include <timer.h> #include <timestamp.h> @@ -82,6 +84,9 @@ void romstage(void) void platform_prog_run(struct prog *prog) { + /* We'll switch to a new stack, so validate our old one here. */ + checkstack(_estack, 0); + ccplex_cpu_start(prog_entry(prog)); clock_halt_avp(); diff --git a/src/soc/nvidia/tegra132/stage_entry.S b/src/soc/nvidia/tegra132/stage_entry.S new file mode 100644 index 0000000..de89f95 --- /dev/null +++ b/src/soc/nvidia/tegra132/stage_entry.S @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/asm.h> + +ENTRY(stage_entry) + /* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */ + bl arm64_init_cpu + + /* Jump to Tegra-specific C entry point. */ + bl ramstage_entry +ENDPROC(stage_entry) diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 002a6d3..5273d81 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -6,7 +6,6 @@ config SOC_NVIDIA_TEGRA210 select ARCH_VERSTAGE_ARMV4 select ARCH_ROMSTAGE_ARMV4 select ARCH_RAMSTAGE_ARMV8_64 - select ARCH_ARM64_CPU_CORTEX_A57 select BOOTBLOCK_CONSOLE select GIC select HAVE_MONOTONIC_TIMER @@ -22,11 +21,6 @@ if SOC_NVIDIA_TEGRA210 config CHROMEOS select CHROMEOS_RAMOOPS_NON_ACPI -# TODO: Remove after replacing arch/arm64/stage_entry.S -config STACK_SIZE - hex - default 0x1000 - config MAINBOARD_DO_DSI_INIT bool "Use dsi graphics interface" depends on MAINBOARD_DO_NATIVE_VGA_INIT @@ -41,10 +35,6 @@ config MAINBOARD_DO_SOR_INIT help Initialize dp display -config MAX_CPUS - int - default 4 - choice CONSOLE_SERIAL_TEGRA210_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_TEGRA210_UARTA diff --git a/src/soc/nvidia/tegra210/cpu.c b/src/soc/nvidia/tegra210/cpu.c index a837a99..0303150 100644 --- a/src/soc/nvidia/tegra210/cpu.c +++ b/src/soc/nvidia/tegra210/cpu.c @@ -23,7 +23,7 @@ static void enable_core_clocks(int cpu) { - const uint32_t cpu_clocks[CONFIG_MAX_CPUS] = { + const uint32_t cpu_clocks[] = { [0] = CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CX0, [1] = CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_DBG1 | diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index 0338cd9..00ecd28 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -14,6 +14,7 @@ */ #include <memlayout.h> +#include <rules.h> #include <arch/header.ld> @@ -29,7 +30,11 @@ SECTIONS SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 8K) PRERAM_CBFS_CACHE(0x40002000, 84K) - STACK(0x40017000, 16K) +#if ENV_ARM64 + STACK(0x40017000, 8K) +#else /* AVP gets a separate stack to avoid any chance of handoff races. */ + STACK(0x40019000, 8K) +#endif TIMESTAMP(0x4001B000, 2K) BOOTBLOCK(0x4001B800, 24K) ROMSTAGE(0x40022000, 120K) diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld index b4b3dc2..c1c581b 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld @@ -14,6 +14,7 @@ */ #include <memlayout.h> +#include <rules.h> #include <arch/header.ld> @@ -29,8 +30,12 @@ SECTIONS SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 8K) PRERAM_CBFS_CACHE(0x40002000, 36K) - VBOOT2_WORK(0x4000B000, 16K) - STACK(0x4000F000, 2K) + VBOOT2_WORK(0x4000B000, 12K) +#if ENV_ARM64 + STACK(0x4000E000, 3K) +#else /* AVP gets a separate stack to avoid any chance of handoff races. */ + STACK(0x4000EC00, 3K) +#endif TIMESTAMP(0x4000F800, 2K) BOOTBLOCK(0x40010000, 28K) VERSTAGE(0x40017000, 64K) diff --git a/src/soc/nvidia/tegra210/maincpu.S b/src/soc/nvidia/tegra210/maincpu.S deleted file mode 100644 index 898d821..0000000 --- a/src/soc/nvidia/tegra210/maincpu.S +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <arch/asm.h> - -ENTRY(maincpu_setup) - /* - * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data - * aborts may happen early and crash before the abort handlers are - * installed, but at least the problem will show up near the code that - * causes it. - */ - msr cpsr, #0xdf - - ldr sp, maincpu_stack_pointer - eor lr, lr - ldr r0, maincpu_entry_point - bx r0 -ENDPROC(maincpu_setup) - - .align 2 - - .global maincpu_stack_pointer -maincpu_stack_pointer: - .word 0 - - .global maincpu_entry_point -maincpu_entry_point: - .word 0 diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index 5c37510..18fdded 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -16,12 +16,13 @@ #include <arch/clock.h> #include <arch/cpu.h> #include <arch/stages.h> +#include <gic.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/mmu_operations.h> #include <soc/mtc.h> -void arm64_arch_timer_init(void) +static void arm64_arch_timer_init(void) { uint32_t freq = clock_get_osc_khz() * 1000; // Set the cntfrq register. @@ -47,11 +48,20 @@ static void mselect_enable_wrap(void) write32((void *)TEGRA_MSELECT_CONFIG, reg); } -void arm64_soc_init(void) +/* Tegra-specific entry point, called from assembly in stage_entry.S */ +void ramstage_entry(void); +void ramstage_entry(void) { + /* TODO: Is this still needed? */ + gic_init(); + + /* TODO: Move arch timer setup to BL31? */ + arm64_arch_timer_init(); + /* Enable WRAP to INCR burst type conversion in MSELECT */ mselect_enable_wrap(); + /* TODO: Move TrustZone setup to BL31? */ trustzone_region_init(); tegra210_mmu_init(); @@ -60,4 +70,7 @@ void arm64_soc_init(void) if (tegra210_run_mtc() != 0) printk(BIOS_ERR, "MTC: No training data.\n"); + + /* Jump to boot state machine in common code. */ + main(); } diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c index 23c5266..c9ff35b 100644 --- a/src/soc/nvidia/tegra210/romstage.c +++ b/src/soc/nvidia/tegra210/romstage.c @@ -19,6 +19,7 @@ #include <cbmem.h> #include <console/cbmem_console.h> #include <console/console.h> +#include <lib.h> #include <program_loading.h> #include <soc/addressmap.h> #include <soc/ccplex.h> @@ -27,6 +28,7 @@ #include <soc/sdram_configs.h> #include <soc/romstage.h> #include <soc/nvidia/tegra/apbmisc.h> +#include <symbols.h> #include <timer.h> #include <timestamp.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -86,6 +88,9 @@ void romstage(void) void platform_prog_run(struct prog *prog) { + /* We'll switch to a new stack, so validate our old one here. */ + checkstack(_estack, 0); + ccplex_cpu_start(prog_entry(prog)); clock_halt_avp(); diff --git a/src/soc/nvidia/tegra210/stage_entry.S b/src/soc/nvidia/tegra210/stage_entry.S index f5dabcb..0eeffce 100644 --- a/src/soc/nvidia/tegra210/stage_entry.S +++ b/src/soc/nvidia/tegra210/stage_entry.S @@ -82,10 +82,10 @@ ENTRY(stage_entry) t210_a57_fixup - b arm64_cpu_startup -ENDPROC(stage_entry) -ENTRY(tegra210_reset_handler) - t210_a57_fixup - b arm64_cpu_startup_resume -ENDPROC(tegra210_reset_handler) + /* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */ + bl arm64_init_cpu + + /* Jump to Tegra-specific C entry point. */ + bl ramstage_entry +ENDPROC(stage_entry)

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Patch merged into coreboot/master: arm64: Implement generic stage transitions for non-Tegra SoCs
by gerrit＠coreboot.org 16 Nov '15

16 Nov '15

the following patch was just integrated into master: commit 66a476ad5f29553ad7c46e58eb35faa7a059a5af Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Oct 12 16:45:21 2015 -0700 arm64: Implement generic stage transitions for non-Tegra SoCs The existing arm64 architecture code has been developed for the Tegra132 and Tegra210 SoCs, which only start their ARM64 cores in ramstage. It interweaves the stage entry point with code that initializes a CPU (and should not be run again if that CPU already ran a previous stage). It also still contains some vestiges of SMP/secmon support (such as setting up stacks in the BSS instead of using the stage-peristent one from memlayout). This patch splits those functions apart and makes the code layout similar to how things work on ARM32. The default stage_entry() symbol is a no-op wrapper that just calls main() for the current stage, for the normal case where a stage ran on the same core as the last one. It can be overridden by SoC code to support special cases like Tegra. The CPU initialization code is split out into armv8/cpu.S (similar to what arm_init_caches() does for ARM32) and called by the default bootblock entry code. SoCs where a CPU starts up in a later stage can call the same code from a stage_entry() override instead. The Tegra132 and Tegra210 code is not touched by this patch to make it easier to review and validate. A follow-up patch will bring those SoCs in line with the model. BRANCH=None BUG=None TEST=Booted Oak with a single mmu_init()/mmu_enable(). Built Ryu and Smaug. Change-Id: I28302a6ace47e8ab7a736e089f64922cef1a2f93 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/12077 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/12077 for details. -gerrit

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coreboot-gerrit November 2015