coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

1 participants
1544 discussions

Patch merged into coreboot/master: intel/fsp_rangeley: Load BSP microcode in bootblock
by gerrit＠coreboot.org 16 Nov '15

16 Nov '15

the following patch was just integrated into master: commit 5f06d53bdb3621ff9e232d4f070f9ff4bbacfa4c Author: David Guckian <david.guckian(a)intel.com> Date: Mon Nov 9 16:19:18 2015 +0000 intel/fsp_rangeley: Load BSP microcode in bootblock Load microcode to BSP in bootblock so later on the FSP TempRamInit call will return with success. The updated fsp1_0 driver calls TempRamInit API with dummy microcode, so FSP will not handle the microcode load. If BSP is not loaded with microcode before calling TempRamInit API, the call will fail with error No Valid Microcode Was Found. Change-Id: I9c55acaf3353a759bb0119f0a5402a704ffb2c4a Signed-off-by: David Guckian <david.guckian(a)intel.com> Reviewed-on: http://review.coreboot.org/12367 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: York Yang <york.yang(a)intel.com> See http://review.coreboot.org/12367 for details. -gerrit

1 0

Patch merged into coreboot/master: nb/amd/mct_ddr3: Fix RDIMM errors due to undefined number of slots
by gerrit＠coreboot.org 16 Nov '15

16 Nov '15

the following patch was just integrated into master: commit dc4cb05763fa029d7495f7aa37194f3ee5abaf05 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Jul 25 01:23:17 2015 -0500 nb/amd/mct_ddr3: Fix RDIMM errors due to undefined number of slots The current code did not define the number of DIMM slots on the mainboard, which lead to incorrect configuration values and occassional training failure. Add preliminary support for DIMM slot count configuration. Change-Id: I488511d6262ffa8207c442d133314aed0f75acfb Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12016 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/12016 for details. -gerrit

1 0

Patch set updated for coreboot: northbridge/amd/amdht: Add support for HT3 2.8GHz and up link frequencies
by Timothy Pearson 16 Nov '15

16 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12027 -gerrit commit b57567e22e944a289a4e369d65c5702b683617c0 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 2 21:36:24 2015 -0500 northbridge/amd/amdht: Add support for HT3 2.8GHz and up link frequencies Change-Id: Ifa1592d26ba7deb034046fd3f2a15149117d9a76 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/defaults.h | 8 ++- src/mainboard/asus/kgpe-d16/cmos.layout | 30 ++++----- src/northbridge/amd/amdht/h3ffeat.h | 6 +- src/northbridge/amd/amdht/h3finit.c | 93 +++++++++++++++++----------- src/northbridge/amd/amdht/h3finit.h | 18 ++++-- src/northbridge/amd/amdht/h3ncmn.c | 82 +++++++++++++++++------- src/northbridge/amd/amdht/h3ncmn.h | 3 +- 7 files changed, 155 insertions(+), 85 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index a3c7b1f..3e9ec09 100644 --- a/src/cpu/amd/family_10h-family_15h/defaults.h +++ b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -273,7 +273,13 @@ static const struct { /* Link Global Retry Control Register */ { 0, 0x150, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 0x00073900, 0x00073F00 }, + 0x00073900, 0x00073f70 }, /* TotalRetryAttempts = 0x7, + HtRetryCrcDatInsDynEn = 0x1, + HtRetryCrcCmdPackDynEn = 0x1, + HtRetryCrcDatIns = 0x4, + HtRetryCrcCmdPack = 0x1, + ForceErrType = 0x0, + MultRetryErr = 0x0 */ /* Errata 351 * System software should program the Link Extended Control Registers[LS2En] diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 21765e3..e17fec6 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -120,21 +120,21 @@ enumerations 10 21 42ms 10 22 84ms 11 0 Auto -11 1 2.6GHz -11 2 2.4GHz -11 3 2.2GHz -11 4 2.0GHz -11 5 1.8GHz -11 6 1.6GHz -11 7 1.4GHz -11 8 1.2GHz -11 9 1.0GHz -11 10 800MHz -11 11 600MHz -11 12 500MHz -11 13 400MHz -11 14 300MHz -11 15 200MHz +11 1 3.2GHz +11 2 3.0GHz +11 3 2.8GHz +11 4 2.6GHz +11 5 2.4GHz +11 6 2.2GHz +11 7 2.0GHz +11 8 1.8GHz +11 9 1.6GHz +11 10 1.4GHz +11 11 1.2GHz +11 12 1.0GHz +11 13 800MHz +11 14 600MHz +11 15 500MHz 12 0 1.5V 12 1 1.35V 12 2 1.25V diff --git a/src/northbridge/amd/amdht/h3ffeat.h b/src/northbridge/amd/amdht/h3ffeat.h index 52c4def..628b86e 100644 --- a/src/northbridge/amd/amdht/h3ffeat.h +++ b/src/northbridge/amd/amdht/h3ffeat.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -58,6 +59,7 @@ #define HTHOST_LINK_CAPABILITY_REG 0x00 #define HTHOST_LINK_CONTROL_REG 0x04 #define HTHOST_FREQ_REV_REG 0x08 +#define HTHOST_FREQ_REV_REG_2 0x1c #define HT_HOST_REV_REV3 0x60 #define HTHOST_FEATURE_CAP_REG 0x0C #define HTHOST_BUFFER_COUNT_REG 0x10 @@ -123,10 +125,10 @@ typedef struct /* This section is for keeping track of capabilities and possible configurations */ BOOL RegangCap; - u16 PrvFrequencyCap; + uint32_t PrvFrequencyCap; u8 PrvWidthInCap; u8 PrvWidthOutCap; - u16 CompositeFrequencyCap; + uint32_t CompositeFrequencyCap; } sPortDescriptor; diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index bcdcfa2..e4ce768 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -48,28 +48,32 @@ #define APIC_Base_BSP 8 #define APIC_Base 0x1b -#define NVRAM_LIMIT_HT_SPEED_200 0xf -#define NVRAM_LIMIT_HT_SPEED_300 0xe -#define NVRAM_LIMIT_HT_SPEED_400 0xd -#define NVRAM_LIMIT_HT_SPEED_500 0xc -#define NVRAM_LIMIT_HT_SPEED_600 0xb -#define NVRAM_LIMIT_HT_SPEED_800 0xa -#define NVRAM_LIMIT_HT_SPEED_1000 0x9 -#define NVRAM_LIMIT_HT_SPEED_1200 0x8 -#define NVRAM_LIMIT_HT_SPEED_1400 0x7 -#define NVRAM_LIMIT_HT_SPEED_1600 0x6 -#define NVRAM_LIMIT_HT_SPEED_1800 0x5 -#define NVRAM_LIMIT_HT_SPEED_2000 0x4 -#define NVRAM_LIMIT_HT_SPEED_2200 0x3 -#define NVRAM_LIMIT_HT_SPEED_2400 0x2 -#define NVRAM_LIMIT_HT_SPEED_2600 0x1 +#define NVRAM_LIMIT_HT_SPEED_200 0x12 +#define NVRAM_LIMIT_HT_SPEED_300 0x11 +#define NVRAM_LIMIT_HT_SPEED_400 0x10 +#define NVRAM_LIMIT_HT_SPEED_500 0xf +#define NVRAM_LIMIT_HT_SPEED_600 0xe +#define NVRAM_LIMIT_HT_SPEED_800 0xd +#define NVRAM_LIMIT_HT_SPEED_1000 0xc +#define NVRAM_LIMIT_HT_SPEED_1200 0xb +#define NVRAM_LIMIT_HT_SPEED_1400 0xa +#define NVRAM_LIMIT_HT_SPEED_1600 0x9 +#define NVRAM_LIMIT_HT_SPEED_1800 0x8 +#define NVRAM_LIMIT_HT_SPEED_2000 0x7 +#define NVRAM_LIMIT_HT_SPEED_2200 0x6 +#define NVRAM_LIMIT_HT_SPEED_2400 0x5 +#define NVRAM_LIMIT_HT_SPEED_2600 0x4 +#define NVRAM_LIMIT_HT_SPEED_2800 0x3 +#define NVRAM_LIMIT_HT_SPEED_3000 0x2 +#define NVRAM_LIMIT_HT_SPEED_3200 0x1 #define NVRAM_LIMIT_HT_SPEED_AUTO 0x0 -static const uint16_t ht_speed_limit[16] = - {0xFFFF, 0x7FFF, 0x3FFF, 0x1FFF, - 0x0FFF, 0x07FF, 0x03FF, 0x01FF, - 0x00FF, 0x007F, 0x003F, 0x001F, - 0x000F, 0x0007, 0x0003, 0x0001}; +static const uint32_t ht_speed_limit[20] = + {0xFFFFF, 0xFFFFF, 0x7FFFF, 0x3FFFF, + 0x0FFFF, 0x07FFF, 0x03FFF, 0x01FFF, + 0x00FFF, 0x007FF, 0x003FF, 0x001FF, + 0x000FF, 0x0007F, 0x0003F, 0x0001F, + 0x0000F, 0x00007, 0x00003, 0x00001}; static const struct ht_speed_limit_map_t { uint16_t mhz; @@ -91,9 +95,12 @@ static const struct ht_speed_limit_map_t { {2200, NVRAM_LIMIT_HT_SPEED_2200}, {2400, NVRAM_LIMIT_HT_SPEED_2400}, {2600, NVRAM_LIMIT_HT_SPEED_2600}, + {2800, NVRAM_LIMIT_HT_SPEED_2800}, + {3000, NVRAM_LIMIT_HT_SPEED_3000}, + {3200, NVRAM_LIMIT_HT_SPEED_3200}, }; -static const uint16_t ht_speed_mhz_to_hw(uint16_t mhz) +static const uint32_t ht_speed_mhz_to_hw(uint16_t mhz) { size_t i; for (i = 0; i < ARRAY_SIZE(ht_speed_limit_map); i++) @@ -452,7 +459,7 @@ static void htDiscoveryFloodFill(sMainData *pDat) /* Set currentNode's NodeID field to currentNode */ pDat->nb->writeNodeID(currentNode, currentNode, pDat->nb); - /* Enable routing tables on currentNode*/ + /* Enable routing tables on currentNode */ pDat->nb->enableRoutingTables(currentNode, pDat->nb); for (currentLinkID = 0; currentLinkID < pDat->nb->maxLinks; currentLinkID++) @@ -1427,19 +1434,30 @@ static void regangLinks(sMainData *pDat) static void selectOptimalWidthAndFrequency(sMainData *pDat) { u8 i, j; - u32 temp; - u16 cbPCBFreqLimit; - u16 cbPCBFreqLimit_NVRAM; + uint32_t temp; + uint32_t cbPCBFreqLimit; + uint32_t cbPCBFreqLimit_NVRAM; u8 cbPCBABDownstreamWidth; u8 cbPCBBAUpstreamWidth; - cbPCBFreqLimit_NVRAM = 0xFFFF; + cbPCBFreqLimit_NVRAM = 0xfffff; if (get_option(&temp, "hypertransport_speed_limit") == CB_SUCCESS) cbPCBFreqLimit_NVRAM = ht_speed_limit[temp & 0xf]; + if (!is_fam15h()) { + /* FIXME + * By default limit frequency to 2.6 GHz as there are residual + * problems with HT v3.1 implementation on at least some Socket G34 + * mainboards / Fam10h CPUs. + * Debug the issues and reenable this... + */ + if (cbPCBFreqLimit_NVRAM > 0xffff) + cbPCBFreqLimit_NVRAM = 0xffff; + } + for (i = 0; i < pDat->TotalLinks*2; i += 2) { - cbPCBFreqLimit = 0xFFFF; // Maximum allowed by autoconfiguration + cbPCBFreqLimit = 0xfffff; // Maximum allowed by autoconfiguration if (pDat->HtBlock->ht_link_configuration) cbPCBFreqLimit = ht_speed_mhz_to_hw(pDat->HtBlock->ht_link_configuration->ht_speed_limit); cbPCBFreqLimit = min(cbPCBFreqLimit, cbPCBFreqLimit_NVRAM); @@ -1484,17 +1502,18 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat) } } - temp = pDat->PortList[i].PrvFrequencyCap; temp &= pDat->PortList[i+1].PrvFrequencyCap; temp &= cbPCBFreqLimit; - pDat->PortList[i].CompositeFrequencyCap = (u16)temp; - pDat->PortList[i+1].CompositeFrequencyCap = (u16)temp; + pDat->PortList[i].CompositeFrequencyCap = temp; + pDat->PortList[i+1].CompositeFrequencyCap = temp; ASSERT (temp != 0); - for (j = 15; ; j--) + for (j = 19; ; j--) { - if (temp & ((u32)1 << j)) + if ((j == 16) || (j == 15)) + continue; + if (temp & ((uint32_t)1 << j)) break; } @@ -1638,12 +1657,14 @@ static void hammerSublinkFixup(sMainData *pDat) /* Remove hiFreq from the list of valid frequencies */ temp = temp & ~((uint32)1 << hiFreq); ASSERT (temp != 0); - pDat->PortList[hiIndex].CompositeFrequencyCap = (uint16)temp; - pDat->PortList[hiIndex+1].CompositeFrequencyCap = (uint16)temp; + pDat->PortList[hiIndex].CompositeFrequencyCap = temp; + pDat->PortList[hiIndex+1].CompositeFrequencyCap = temp; - for (k = 15; ; k--) + for (k = 19; ; k--) { - if (temp & ((u32)1 << k)) + if ((j == 16) || (j == 15)) + continue; + if (temp & ((uint32_t)1 << k)) break; } diff --git a/src/northbridge/amd/amdht/h3finit.h b/src/northbridge/amd/amdht/h3finit.h index f6ab010..1bd8616 100644 --- a/src/northbridge/amd/amdht/h3finit.h +++ b/src/northbridge/amd/amdht/h3finit.h @@ -49,6 +49,9 @@ #define HT_FREQUENCY_2200M 12 #define HT_FREQUENCY_2400M 13 #define HT_FREQUENCY_2600M 14 +#define HT_FREQUENCY_2800M 17 +#define HT_FREQUENCY_3000M 18 +#define HT_FREQUENCY_3200M 19 /* Frequency Limit equates for call backs which take a frequency supported mask. */ #define HT_FREQUENCY_LIMIT_200M 1 @@ -65,6 +68,9 @@ #define HT_FREQUENCY_LIMIT_2200M 0x1FFF #define HT_FREQUENCY_LIMIT_2400M 0x3FFF #define HT_FREQUENCY_LIMIT_2600M 0x7FFF +#define HT_FREQUENCY_LIMIT_2800M 0x3FFFF +#define HT_FREQUENCY_LIMIT_3000M 0x7FFFF +#define HT_FREQUENCY_LIMIT_3200M 0xFFFFF /* * Event Notify definitions @@ -220,7 +226,7 @@ typedef struct { * @param[in] u8 Link = The Device's link number (0 or 1) * @param[in,out] u8* LinkWidthIn = modify to change the Link Witdh In * @param[in,out] u8* LinkWidthOut = modify to change the Link Witdh Out - * @param[in,out] u16* FreqCap = modify to change the link's frequency capability + * @param[in,out] u32* FreqCap = modify to change the link's frequency capability * * --------------------------------------------------------------------------------------- */ @@ -235,7 +241,7 @@ typedef struct { u8 Link, u8 *LinkWidthIn, u8 *LinkWidthOut, - u16 *FreqCap + u32 *FreqCap ); /**---------------------------------------------------------------------------------------- @@ -258,7 +264,7 @@ typedef struct { * @param[in] u8 linkB = The link on that node * @param[in,out] u8* ABLinkWidthLimit = modify to change the Link Witdh In * @param[in,out] u8* BALinkWidthLimit = modify to change the Link Witdh Out - * @param[in,out] u16* PCBFreqCap = modify to change the link's frequency capability + * @param[in,out] u32* PCBFreqCap = modify to change the link's frequency capability * * --------------------------------------------------------------------------------------- */ @@ -269,7 +275,7 @@ typedef struct { u8 LinkB, u8 *ABLinkWidthLimit, u8 *BALinkWidthLimit, - u16 *PCBFreqCap + u32 *PCBFreqCap ); /**---------------------------------------------------------------------------------------- @@ -291,7 +297,7 @@ typedef struct { * @param[in] u8 Depth = The depth in the I/O chain from the Host * @param[in,out] u8* DownstreamLinkWidthLimit = modify to change the Link Witdh In * @param[in,out] u8* UpstreamLinkWidthLimit = modify to change the Link Witdh Out - * @param[in,out] u16* PCBFreqCap = modify to change the link's frequency capability + * @param[in,out] u32* PCBFreqCap = modify to change the link's frequency capability * * --------------------------------------------------------------------------------------- */ @@ -301,7 +307,7 @@ typedef struct { u8 Depth, u8 *DownstreamLinkWidthLimit, u8 *UpstreamLinkWidthLimit, - u16 *PCBFreqCap + u32 *PCBFreqCap ); /**---------------------------------------------------------------------------------------- diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index 8ee929d..29524af 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -1310,7 +1310,7 @@ static u8 convertWidthToBits(u8 value, cNorthBridge *nb) * @return Frequency mask * ******************************************************************************/ -static u16 ht1NorthBridgeFreqMask(u8 node, cNorthBridge *nb) +static uint32_t ht1NorthBridgeFreqMask(u8 node, cNorthBridge *nb) { /* only up to HT1 speeds */ return (HT_FREQUENCY_LIMIT_HT1_ONLY); @@ -1331,26 +1331,43 @@ static u16 ht1NorthBridgeFreqMask(u8 node, cNorthBridge *nb) * @return = Frequency mask * ******************************************************************************/ -static u16 fam10NorthBridgeFreqMask(u8 node, cNorthBridge *nb) +static uint32_t fam10NorthBridgeFreqMask(u8 node, cNorthBridge *nb) { u8 nbCOF; - u16 supported; + uint32_t supported; nbCOF = getMinNbCOF(); /* * nbCOF is minimum northbridge speed in hundreds of MHz. * HT can not go faster than the minimum speed of the northbridge. */ - if ((nbCOF >= 6) && (nbCOF <= 26)) + if ((nbCOF >= 6) && (nbCOF < 10)) { + /* Generation 1 HT link frequency */ /* Convert frequency to bit and all less significant bits, * by setting next power of 2 and subtracting 1. */ - supported = ((u16)1 << ((nbCOF >> 1) + 2)) - 1; + supported = ((uint32_t)1 << ((nbCOF >> 1) + 2)) - 1; } - else if (nbCOF > 26) + else if ((nbCOF >= 10) && (nbCOF <= 32)) { - supported = HT_FREQUENCY_LIMIT_2600M; + /* Generation 3 HT link frequency + * Assume error retry is enabled on all Gen 3 links + */ + if (is_gt_rev_d()) { + nbCOF *= 2; + if (nbCOF > 32) + nbCOF = 32; + } + + /* Convert frequency to bit and all less significant bits, + * by setting next power of 2 and subtracting 1. + */ + supported = ((uint32_t)1 << ((nbCOF >> 1) + 2)) - 1; + } + else if (nbCOF > 32) + { + supported = HT_FREQUENCY_LIMIT_3200M; } /* unlikely cases, but include as a defensive measure, also avoid trick above */ else if (nbCOF == 4) @@ -1405,8 +1422,13 @@ static void gatherLinkData(sMainData *pDat, cNorthBridge *nb) pDat->PortList[i].PrvWidthInCap = convertBitsToWidth((u8)temp, pDat->nb); AmdPCIReadBits(linkBase + HTHOST_FREQ_REV_REG, 31, 16, &temp); - pDat->PortList[i].PrvFrequencyCap = (u16)temp & 0x7FFF - & nb->northBridgeFreqMask(pDat->PortList[i].NodeID, pDat->nb); /* Mask off bit 15, reserved value */ + pDat->PortList[i].PrvFrequencyCap = temp & 0x7FFF /* Mask off bit 15, reserved value */ + & nb->northBridgeFreqMask(pDat->PortList[i].NodeID, pDat->nb); + if (is_gt_rev_d()) { + AmdPCIReadBits(linkBase + HTHOST_FREQ_REV_REG_2, 15, 1, &temp); + temp &= 0x7; /* Mask off reserved values */ + pDat->PortList[i].PrvFrequencyCap |= (temp << 17); + } } else { @@ -1463,7 +1485,7 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) { u8 i; SBDFO linkBase; - u32 temp, widthin, widthout, bits; + u32 temp, temp2, frequency_index, widthin, widthout, bits; for (i = 0; i < pDat->TotalLinks*2; i++) { @@ -1524,10 +1546,19 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) temp = pDat->PortList[i].SelFrequency; if (pDat->PortList[i].Type == PORTLIST_TYPE_CPU) { - ASSERT((temp >= HT_FREQUENCY_600M && temp <= HT_FREQUENCY_2600M) + ASSERT((temp >= HT_FREQUENCY_600M && temp <= HT_FREQUENCY_3200M) || (temp == HT_FREQUENCY_200M) || (temp == HT_FREQUENCY_400M)); + frequency_index = temp; + if (temp > 0xf) { + temp2 = (temp >> 4) & 0x1; + temp &= 0xf; + } else { + temp2 = 0x0; + } + if (is_gt_rev_d()) + AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG_2, 0, 0, &temp2); AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG, 11, 8, &temp); - if (temp > HT_FREQUENCY_1000M) /* Gen1 = 200MHz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz */ + if (frequency_index > HT_FREQUENCY_1000M) /* Gen1 = 200MHz -> 1000MHz, Gen3 = 1200MHz -> 3200MHz */ { /* Enable for Gen3 frequencies */ temp = 1; @@ -1537,27 +1568,27 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) /* Disable for Gen1 frequencies */ temp = 0; } - /* HT3 retry mode enable / disable */ - AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(pDat->PortList[i].NodeID), - makePCIBusFromNode(pDat->PortList[i].NodeID), - makePCIDeviceFromNode(pDat->PortList[i].NodeID), - CPU_HTNB_FUNC_00, - REG_HT_LINK_RETRY0_0X130 + 4*pDat->PortList[i].Link), - 0, 0, &temp); - /* and Scrambling enable / disable */ - AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(pDat->PortList[i].NodeID), + /* HT3 retry mode enable / disable */ + AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(pDat->PortList[i].NodeID), makePCIBusFromNode(pDat->PortList[i].NodeID), makePCIDeviceFromNode(pDat->PortList[i].NodeID), CPU_HTNB_FUNC_00, - REG_HT_LINK_EXT_CONTROL0_0X170 + 4*pDat->PortList[i].Link), - 3, 3, &temp); + REG_HT_LINK_RETRY0_0X130 + 4*pDat->PortList[i].Link), + 0, 0, &temp); + /* and Scrambling enable / disable */ + AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(pDat->PortList[i].NodeID), + makePCIBusFromNode(pDat->PortList[i].NodeID), + makePCIDeviceFromNode(pDat->PortList[i].NodeID), + CPU_HTNB_FUNC_00, + REG_HT_LINK_EXT_CONTROL0_0X170 + 4*pDat->PortList[i].Link), + 3, 3, &temp); } else { SBDFO currentPtr; BOOL isFound; - ASSERT(temp <= HT_FREQUENCY_2600M); + ASSERT(temp <= HT_FREQUENCY_3200M); /* Write the frequency setting */ AmdPCIWriteBits(linkBase + HTSLAVE_FREQ_REV_0_REG, 11, 8, &temp); @@ -1718,6 +1749,9 @@ static void fam0fWriteHTLinkCmdBufferAlloc(u8 node, u8 link, u8 req, u8 preq, u8 /* Probe Command Buffers */ temp = prb; AmdPCIWriteBits(currentPtr, 15, 12, &temp); + /* LockBc */ + temp = 1; + AmdPCIWriteBits(currentPtr, 31, 31, &temp); } #endif /* HT_BUILD_NC_ONLY */ diff --git a/src/northbridge/amd/amdht/h3ncmn.h b/src/northbridge/amd/amdht/h3ncmn.h index 328d909..3c8a346 100644 --- a/src/northbridge/amd/amdht/h3ncmn.h +++ b/src/northbridge/amd/amdht/h3ncmn.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -103,7 +104,7 @@ struct cNorthBridge /* Public Interfaces for northbridge clients, Optimization */ u8 (*convertBitsToWidth)(u8 value, cNorthBridge *nb); u8 (*convertWidthToBits)(u8 value, cNorthBridge *nb); - u16 (*northBridgeFreqMask)(u8 node, cNorthBridge *nb); + uint32_t (*northBridgeFreqMask)(u8 node, cNorthBridge *nb); void (*gatherLinkData)(sMainData *pDat, cNorthBridge *nb); void (*setLinkData)(sMainData *pDat, cNorthBridge *nb);

1 0

Patch set updated for coreboot: cpu/amd/family_10h-family_15h: Fix incorrect revision detection
by Timothy Pearson 16 Nov '15

16 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12026 -gerrit commit fc0e13af1fbca307d47ad8a2d6b1ec6033a1129c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 2 21:31:48 2015 -0500 cpu/amd/family_10h-family_15h: Fix incorrect revision detection Change-Id: I7a881a94d62ed455415f9dfc887fd698ac919429 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/fidvid.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 8a006cb..66bb3a2 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -371,7 +371,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) pci_write_config32(dev, 0xd8, dtemp); } -static u32 nb_clk_did(int node, u32 cpuRev,u8 procPkg) { +static u32 nb_clk_did(int node, uint64_t cpuRev, uint8_t procPkg) { u8 link0isGen3 = 0; u8 offset; if (AMD_CpuFindCapability(node, 0, &offset)) { @@ -442,7 +442,7 @@ static u32 power_up_down(int node, u8 procPkg) { return dword; } -static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { +static void config_clk_power_ctrl_reg0(int node, uint64_t cpuRev, uint8_t procPkg) { device_t dev = NODE_PCI(node, 3); /* Program fields in Clock Power/Control register0 (F3xD4) */ @@ -467,7 +467,7 @@ static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { } -static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { +static void config_power_ctrl_misc_reg(device_t dev, uint64_t cpuRev, uint8_t procPkg) { /* check PVI/SVI */ u32 dword = pci_read_config32(dev, 0xa0); @@ -500,7 +500,7 @@ static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { pci_write_config32(dev, 0xa0, dword); } -static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { +static void config_nb_syn_ptr_adj(device_t dev, uint64_t cpuRev) { /* Note the following settings are additional from the ported * function setFidVidRegs() */ @@ -522,7 +522,7 @@ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { pci_write_config32(dev, 0xdc, dword); } -static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) { +static void config_acpi_pwr_state_ctrl_regs(device_t dev, uint64_t cpuRev, uint8_t procPkg) { if (is_fam15h()) { /* Family 15h BKDG Rev. 3.14 D18F3x80 recommended settings */ pci_write_config32(dev, 0x80, 0xe20be281);

1 0

Patch set updated for coreboot: cpu/amd/fam10h-fam15h: Set northbridge throttle values
by Timothy Pearson 16 Nov '15

16 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12025 -gerrit commit 3a8166c60b4ad4ecddb548e8910f6d235a0c34e8 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 2 21:31:17 2015 -0500 cpu/amd/fam10h-fam15h: Set northbridge throttle values The existing code did not set the northbridge throttle values on Family 15h, leading to sporadic and random deadlocks in the crossbar per AMD notes. Properly set the northbridge throttle values on Family 15h. Change-Id: I6304b63708c65fedb9c2d46b8c862b7f0adf1102 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 21 +---------- .../amd/family_10h-family_15h/model_10xxx_init.c | 44 ++++++++++++++++++++++ 2 files changed, 45 insertions(+), 20 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index a6d8dc4..8bc0b6f 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -873,6 +873,7 @@ static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff) else linktype |= HTPHY_LINKTYPE_UNGANGED; } + return linktype; } @@ -967,26 +968,6 @@ void cpuSetAMDMSR(uint8_t node_id) } AMD_Errata298(); - if (revision & AMD_FAM15_ALL) { - uint32_t f5x80; - uint8_t enabled; - uint8_t compute_unit_count = 0; - f5x80 = pci_read_config32(NODE_PCI(node_id, 5), 0x80); - enabled = f5x80 & 0xf; - if (enabled == 0x1) - compute_unit_count = 1; - if (enabled == 0x3) - compute_unit_count = 2; - if (enabled == 0x7) - compute_unit_count = 3; - if (enabled == 0xf) - compute_unit_count = 4; - msr = rdmsr(BU_CFG2); - msr.lo &= ~(0x3 << 6); /* ThrottleNbInterface[1:0] */ - msr.lo |= (((compute_unit_count - 1) & 0x3) << 6); - wrmsr(BU_CFG2, msr); - } - /* Revision C0 and above */ if (revision & AMD_OR_C0) { uint32_t f3x1fc = pci_read_config32(NODE_PCI(node_id, 3), 0x1fc); diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index 4ccf79d..fe9fb9c 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -154,6 +154,50 @@ static void model_10xxx_init(device_t dev) printk(BIOS_DEBUG, "siblings = %02d, ", siblings); #endif + /* Set bus unit configuration */ + if (is_fam15h()) { + uint32_t f5x80; + uint8_t enabled; + uint8_t compute_unit_count = 0; + f5x80 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 5)), 0x80); + enabled = f5x80 & 0xf; + if (enabled == 0x1) + compute_unit_count = 1; + if (enabled == 0x3) + compute_unit_count = 2; + if (enabled == 0x7) + compute_unit_count = 3; + if (enabled == 0xf) + compute_unit_count = 4; + msr = rdmsr(BU_CFG2_MSR); + msr.lo &= ~(0x3 << 6); /* ThrottleNbInterface[1:0] */ + msr.lo |= (((compute_unit_count - 1) & 0x3) << 6); + wrmsr(BU_CFG2_MSR, msr); + } else { + uint32_t f0x60; + uint32_t f0x160; + uint8_t core_count = 0; + uint8_t node_count = 0; + f0x60 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x60); + core_count = (f0x60 >> 16) & 0x1f; + node_count = ((f0x60 >> 4) & 0x7) + 1; + if (is_gt_rev_d()) { + f0x160 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x160); + core_count |= ((f0x160 >> 16) & 0x7) << 5; + } + core_count++; + core_count /= node_count; + msr = rdmsr(BU_CFG2_MSR); + if (is_gt_rev_d()) { + msr.hi &= ~(0x3 << (36 - 32)); /* ThrottleNbInterface[3:2] */ + msr.hi |= ((((core_count - 1) >> 2) & 0x3) << (36 - 32)); + } + msr.lo &= ~(0x3 << 6); /* ThrottleNbInterface[1:0] */ + msr.lo |= (((core_count - 1) & 0x3) << 6); + msr.lo &= ~(0x1 << 24); /* WcPlusDis = 0 */ + wrmsr(BU_CFG2_MSR, msr); + } + /* Disable Cf8ExtCfg */ msr = rdmsr(NB_CFG_MSR); msr.hi &= ~(1 << (46 - 32));

1 0

Patch set updated for coreboot: mainboard/asus/kgpe-d16: Fix I/O link detection
by Timothy Pearson 16 Nov '15

16 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12024 -gerrit commit a8450d0c039b6949a7591103d88b6504289b5f66 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 2 21:28:31 2015 -0500 mainboard/asus/kgpe-d16: Fix I/O link detection Change-Id: Ibefc9dc2e1e0267389eb8d716408bae6026ce084 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/romstage.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index be91eaa..6503b90 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -551,7 +551,8 @@ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { /* Force BUID to 0 */ static const u8 swaplist[] = {0, 0, 0xFF, 0, 0xFF}; - if ((node == 0) && (link == 1)) { /* BSP SB link */ + if ((is_fam15h() && (node == 0) && (link == 1)) /* Family 15h BSP SB link */ + || (!is_fam15h() && (node == 0) && (link == 3))) { /* Family 10h BSP SB link */ *List = swaplist; return 1; }

1 0

Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Move K10D configuration into separate file
by Timothy Pearson 16 Nov '15

16 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12023 -gerrit commit c876ed4ae5fa43cee27fb79415f4c6c2abe830f5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 2 21:23:02 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Move K10D configuration into separate file Change-Id: Id45888f266fac7810a63fef43b8d7a0ee40cbf70 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/raminit_amdmct.c | 1 + src/northbridge/amd/amdmct/amddefs.h | 5 +- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 131 +++++++++++-------------- src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c | 4 +- src/northbridge/amd/amdmct/mct_ddr3/mctprod.c | 65 ++++++++++++ 5 files changed, 130 insertions(+), 76 deletions(-) diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index d8023f8..a40c5a1 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -373,6 +373,7 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8 #include "../amdmct/mct_ddr3/mctdqs_d.c" #include "../amdmct/mct_ddr3/mctsrc.c" #include "../amdmct/mct_ddr3/mctsdi.c" +#include "../amdmct/mct_ddr3/mctprod.c" #include "../amdmct/mct_ddr3/mctproc.c" #include "../amdmct/mct_ddr3/mctprob.c" #include "../amdmct/mct_ddr3/mcthwl.c" diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index d2dfbcc..10a50d9 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -111,7 +112,7 @@ /* * CPU HT PHY REGISTERS, FIELDS, AND MASKS */ -#define HTPHY_OFFSET_MASK 0xE00001FF +#define HTPHY_OFFSET_MASK 0xE000FFFF #define HTPHY_WRITE_CMD 0x40000000 #define HTPHY_IS_COMPLETE_MASK 0x80000000 #define HTPHY_DIRECT_MAP 0x20000000 @@ -160,4 +161,4 @@ #define AMD_PKGTYPE_S1gX 2 #define AMD_PKGTYPE_G34 3 #define AMD_PKGTYPE_ASB2 4 -#define AMD_PKGTYPE_C32 5 \ No newline at end of file +#define AMD_PKGTYPE_C32 5 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index bfe7515..283d897 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -178,6 +178,7 @@ static void SyncSetting(struct DCTStatStruc *pDCTstat); static uint8_t crcCheck(struct DCTStatStruc *pDCTstat, uint8_t dimm); static void mct_ExtMCTConfig_Bx(struct DCTStatStruc *pDCTstat); static void mct_ExtMCTConfig_Cx(struct DCTStatStruc *pDCTstat); +static void mct_ExtMCTConfig_Dx(struct DCTStatStruc *pDCTstat); static void read_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); @@ -2687,13 +2688,11 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { pDCTstat = pDCTstatA + Node; - /* Configure and enable prefetchers */ - if (is_fam15h()) - dword = 0x0ce00f41; /* BKDG recommended */ - else - dword = 0x0fe40fc0; /* BKDG recommended */ - dword |= MCCH_FlushWrOnStpGnt; /* Set for S3 */ - Set_NB32(pDCTstat->dev_dct, 0x11c, dword); + /* Enable prefetchers */ + dword = Get_NB32(pDCTstat->dev_dct, 0x11c); /* Memory Controller Configuration High */ + dword &= ~(0x1 << 13); /* PrefIoDis = 0 */ + dword &= ~(0x1 << 12); /* PrefCpuDis = 0 */ + Set_NB32(pDCTstat->dev_dct, 0x11c, dword); /* Memory Controller Configuration High */ } } @@ -4935,31 +4934,33 @@ static void Set_OtherTiming(struct MCTStatStruc *pMCTstat, Get_TrwtTO(pMCTstat, pDCTstat, dct); Get_TrwtWB(pMCTstat, pDCTstat); - reg = 0x8C; /* Dram Timing Hi */ - val = Get_NB32_DCT(dev, dct, reg); - val &= 0xffff0300; - dword = pDCTstat->TrwtTO; - val |= dword << 4; - dword = pDCTstat->Twrrd & 3; - val |= dword << 10; - dword = pDCTstat->Twrwr & 3; - val |= dword << 12; - dword = pDCTstat->Trdrd & 3; - val |= dword << 14; - dword = pDCTstat->TrwtWB; - val |= dword; - Set_NB32_DCT(dev, dct, reg, val); - - reg = 0x78; - val = Get_NB32_DCT(dev, dct, reg); - val &= 0xFFFFC0FF; - dword = pDCTstat->Twrrd >> 2; - val |= dword << 8; - dword = pDCTstat->Twrwr >> 2; - val |= dword << 10; - dword = pDCTstat->Trdrd >> 2; - val |= dword << 12; - Set_NB32_DCT(dev, dct, reg, val); + if (!is_fam15h()) { + reg = 0x8c; /* Dram Timing Hi */ + val = Get_NB32_DCT(dev, dct, reg); + val &= 0xffff0300; + dword = pDCTstat->TrwtTO; + val |= dword << 4; + dword = pDCTstat->Twrrd & 3; + val |= dword << 10; + dword = pDCTstat->Twrwr & 3; + val |= dword << 12; + dword = (pDCTstat->Trdrd - 0x3) & 3; + val |= dword << 14; + dword = pDCTstat->TrwtWB; + val |= dword; + Set_NB32_DCT(dev, dct, reg, val); + + reg = 0x78; + val = Get_NB32_DCT(dev, dct, reg); + val &= 0xffffc0ff; + dword = pDCTstat->Twrrd >> 2; + val |= dword << 8; + dword = pDCTstat->Twrwr >> 2; + val |= dword << 10; + dword = (pDCTstat->Trdrd - 0x3) >> 2; + val |= dword << 12; + Set_NB32_DCT(dev, dct, reg, val); + } } static void Get_Trdrd(struct MCTStatStruc *pMCTstat, @@ -4970,6 +4971,8 @@ static void Get_Trdrd(struct MCTStatStruc *pMCTstat, Trdrd = ((int8_t)(pDCTstat->DqsRcvEnGrossMax - pDCTstat->DqsRcvEnGrossMin) >> 1) + 1; if (Trdrd > 8) Trdrd = 8; + if (Trdrd < 3) + Trdrd = 3; pDCTstat->Trdrd = Trdrd; } @@ -5280,47 +5283,31 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, if (pDCTstat->NodePresent) { mct_PhyController_Config(pMCTstat, pDCTstat, 0); mct_PhyController_Config(pMCTstat, pDCTstat, 1); - } - if (!(pDCTstat->LogicalCPUID & AMD_DR_Dx)) { /* mct_checkForDxSupport */ - mct_ExtMCTConfig_Cx(pDCTstat); - mct_ExtMCTConfig_Bx(pDCTstat); - } else { /* For Dx CPU */ - val = 0x0CE00F00 | 1 << 29/* FlushWrOnStpGnt */; - if (!(pDCTstat->GangedMode)) - val |= 0x20; /* MctWrLimit = 8 for Unganged mode */ - else - val |= 0x40; /* MctWrLimit = 16 for ganged mode */ - Set_NB32(pDCTstat->dev_dct, 0x11C, val); - - val = Get_NB32(pDCTstat->dev_dct, 0x1B0); - val &= 0xFFFFF8C0; - val |= 0x101; /* BKDG recommended settings */ - val |= 0x0FC00000; /* Agesa V5 */ - if (!(pDCTstat->GangedMode)) - val |= 1 << 12; - else - val &= ~(1 << 12); - val &= 0x0FFFFFFF; if (!is_fam15h()) { - switch (pDCTstat->Speed) { - case 4: - val |= 0x50000000; /* 5 for DDR800 */ - break; - case 5: - val |= 0x60000000; /* 6 for DDR1066 */ - break; - case 6: - val |= 0x80000000; /* 8 for DDR800 */ - break; - default: - val |= 0x90000000; /* 9 for DDR1600 */ - break; - } - } - Set_NB32(pDCTstat->dev_dct, 0x1B0, val); + /* Family 10h CPUs */ + mct_ExtMCTConfig_Cx(pDCTstat); + mct_ExtMCTConfig_Bx(pDCTstat); + mct_ExtMCTConfig_Dx(pDCTstat); + } else { + /* Family 15h CPUs */ + val = 0x0ce00f00 | 0x1 << 29; /* FlushWrOnStpGnt */ + val |= 0x10 << 2; /* MctWrLimit = 16 */ + Set_NB32(pDCTstat->dev_dct, 0x11c, val); + + val = Get_NB32(pDCTstat->dev_dct, 0x1b0); + val &= ~0x3; /* AdapPrefMissRatio = 0x1 */ + val |= 0x1; + val &= ~(0x3 << 2); /* AdapPrefPositiveStep = 0x0 */ + val &= ~(0x3 << 4); /* AdapPrefNegativeStep = 0x0 */ + val &= ~(0x7 << 8); /* CohPrefPrbLmt = 0x1 */ + val |= (0x1 << 8); + val |= (0x1 << 12); /* EnSplitDctLimits = 0x1 */ + val |= (0x7 << 22); /* PrefFourConf = 0x7 */ + val |= (0x7 << 25); /* PrefFiveConf = 0x7 */ + val &= ~(0xf << 28); /* DcqBwThrotWm = 0x0 */ + Set_NB32(pDCTstat->dev_dct, 0x1b0, val); - if (is_fam15h()) { uint8_t wm1; uint8_t wm2; @@ -5351,11 +5338,11 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, break; } - val = Get_NB32(pDCTstat->dev_dct, 0x1B4); + val = Get_NB32(pDCTstat->dev_dct, 0x1b4); val &= ~(0x3ff); val |= ((wm2 & 0x1f) << 5); val |= (wm1 & 0x1f); - Set_NB32(pDCTstat->dev_dct, 0x1B4, val); + Set_NB32(pDCTstat->dev_dct, 0x1b4, val); } } } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c index 253a89f..da7ce16 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c @@ -98,7 +98,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, BitDelta = bsf(AddrHiMask) - bsf(AddrLoMask); for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel++) { - reg = 0x40+(ChipSel<<2); /*Dram CS Base 0 */ + reg = 0x40 + (ChipSel<<2); /* Dram CS Base 0 */ val = Get_NB32_DCT(dev, dct, reg); if (val & 3) { val_lo = val & AddrLoMask; @@ -114,7 +114,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, if(ChipSel & 1) continue; - reg = 0x60 + ((ChipSel>>1)<<2); /*Dram CS Mask 0 */ + reg = 0x60 + ((ChipSel>>1)<<2); /* Dram CS Mask 0 */ val = Get_NB32_DCT(dev, dct, reg); val_lo = val & AddrLoMask; val_hi = val & AddrHiMask; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctprod.c b/src/northbridge/amd/amdmct/mct_ddr3/mctprod.c new file mode 100644 index 0000000..2b62d4c --- /dev/null +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctprod.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +void mct_ExtMCTConfig_Dx(struct DCTStatStruc *pDCTstat) +{ + uint32_t dword; + + if (pDCTstat->LogicalCPUID & AMD_DR_Dx) { + dword = 0x0ce00f00 | 0x1 << 29; /* FlushWrOnStpGnt */ + if (!(pDCTstat->GangedMode)) + dword |= 0x18 << 2; /* MctWrLimit = 0x18 for unganged mode */ + else + dword |= 0x10 << 2; /* MctWrLimit = 0x10 for ganged mode */ + Set_NB32(pDCTstat->dev_dct, 0x11c, dword); + + dword = Get_NB32(pDCTstat->dev_dct, 0x1b0); + dword &= ~0x3; /* AdapPrefMissRatio = 0x1 */ + dword |= 0x1; + dword &= ~(0x3 << 2); /* AdapPrefPositiveStep = 0x0 */ + dword &= ~(0x3 << 4); /* AdapPrefNegativeStep = 0x0 */ + dword &= ~(0x7 << 8); /* CohPrefPrbLmt = 0x1 */ + dword |= (0x1 << 8); + dword |= (0x7 << 22); /* PrefFourConf = 0x7 */ + dword |= (0x7 << 25); /* PrefFiveConf = 0x7 */ + + if (!(pDCTstat->GangedMode)) + dword |= (0x1 << 12); /* EnSplitDctLimits = 0x1 */ + else + dword &= ~(0x1 << 12); /* EnSplitDctLimits = 0x0 */ + + dword &= ~(0xf << 28); /* DcqBwThrotWm = ... */ + switch (pDCTstat->Speed) { + case 4: + dword |= (0x5 << 28); /* ...5 for DDR800 */ + break; + case 5: + dword |= (0x6 << 28); /* ...6 for DDR1066 */ + break; + case 6: + dword |= (0x8 << 28); /* ...8 for DDR800 */ + break; + default: + dword |= (0x9 << 28); /* ...9 for DDR1600 */ + break; + } + Set_NB32(pDCTstat->dev_dct, 0x1b0, dword); + } +}

1 0

Patch set updated for coreboot: cpu/amd/fam10h-fam15h: Bring HT register configuration in line with BKDG
by Timothy Pearson 16 Nov '15

16 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12022 -gerrit commit c70b6e26e7dda69512d33df3520394757ac6a10f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 2 21:18:29 2015 -0500 cpu/amd/fam10h-fam15h: Bring HT register configuration in line with BKDG The existing HyperTransport register configuration values were incorrect in many spots. Apply the correct values from the BKDG on Family 10h and Family 15h processors. Change-Id: I009b6f478340e2dbfcda2b4534473d4397f9ecef Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/defaults.h | 168 +++++++++++++++++++++------ 1 file changed, 133 insertions(+), 35 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index b6c9bc4..a3c7b1f 100644 --- a/src/cpu/amd/family_10h-family_15h/defaults.h +++ b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -371,44 +371,140 @@ static const struct { [2] SyncOnUcEccEn = 1 */ /* XBAR buffer settings */ - { 3, 0x6c, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00018052, 0x700780f7 }, + { 3, 0x6c, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL, + 0x00018052, 0x700780f7 }, /* IsocRspDBC = 0x0, + UpRspDBC = 0x1, + DatBuf24 = 0x1, + DnRspDBC = 0x1, + DnReqDBC = 0x1, + UpReqDBC = 0x2 */ + + /* XBAR buffer settings */ + { 3, 0x6c, AMD_DR_Dx, AMD_PTYPE_ALL, + 0x00028052, 0x700780f7 }, /* IsocRspDBC = 0x0, + UpRspDBC = 0x2, + DatBuf24 = 0x1, + DnRspDBC = 0x1, + DnReqDBC = 0x1, + UpReqDBC = 0x2 */ /* XBAR buffer settings */ { 3, 0x6c, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x10010052, 0x700700f7 }, + 0x10010052, 0x700700f7 }, /* IsocRspDBC = 0x1, + UpRspDBC = 0x1, + DnRspDBC = 0x1, + DnReqDBC = 0x1, + UpReqDBC = 0x2 */ /* Errata 281 Workaround */ - { 3, 0x6C, ( AMD_DR_B0 | AMD_DR_B1), + { 3, 0x6c, (AMD_DR_B0 | AMD_DR_B1), AMD_PTYPE_SVR, 0x00010094, 0x700780F7 }, - { 3, 0x6C, AMD_FAM10_ALL, AMD_PTYPE_UMA, + { 3, 0x6c, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x60018051, 0x700780F7 }, - { 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00041153, 0x777777F7 }, + { 3, 0x70, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL, + 0x00041153, 0x777777f7 }, /* IsocRspCBC = 0x0, + IsocPreqCBC = 0x0, + IsocReqCBC = 0x0, + UpRspCBC = 0x4, + DnPreqCBC = 0x1, + UpPreqCBC = 0x1, + DnRspCBC = 0x1, + DnReqCBC = 0x1, + UpReqCBC = 0x3 */ + + { 3, 0x70, AMD_DR_Dx, AMD_PTYPE_ALL, + 0x00051153, 0x777777f7 }, /* IsocRspCBC = 0x0, + IsocPreqCBC = 0x0, + IsocReqCBC = 0x0, + UpRspCBC = 0x5, + DnPreqCBC = 0x1, + UpPreqCBC = 0x1, + DnRspCBC = 0x1, + DnReqCBC = 0x1, + UpReqCBC = 0x3 */ { 3, 0x70, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x10171155, 0x777777f7 }, + 0x10171155, 0x777777f7 }, /* IsocRspCBC = 0x1, + IsocPreqCBC = 0x0, + IsocReqCBC = 0x1, + UpRspCBC = 0x7, + DnPreqCBC = 0x1, + UpPreqCBC = 0x1, + DnRspCBC = 0x1, + DnReqCBC = 0x1, + UpReqCBC = 0x5 */ { 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_UMA, - 0x61221151, 0x777777F7 }, + 0x61221151, 0x777777f7 }, /* IsocRspCBC = 0x6, + IsocPreqCBC = 0x1, + IsocReqCBC = 0x2, + UpRspCBC = 0x2, + DnPreqCBC = 0x1, + UpPreqCBC = 0x1, + DnRspCBC = 0x1, + DnReqCBC = 0x1, + UpReqCBC = 0x1 */ + + { 3, 0x74, AMD_FAM10_ALL, ~AMD_PTYPE_UMA, + 0x00081111, 0xf7ff7777 }, /* DRReqCBC = 0x0, + IsocPreqCBC = 0x0, + IsocReqCBC = 0x0, + ProbeCBC = 0x8, + DnPreqCBC = 0x1, + UpPreqCBC = 0x1, + DnReqCBC = 0x1, + UpReqCBC = 0x1 */ { 3, 0x74, AMD_FAM10_ALL, AMD_PTYPE_UMA, - 0x00080101, 0x000F7777 }, + 0x00480101, 0xf7ff7777 }, /* DRReqCBC = 0x0, + IsocPreqCBC = 0x0, + IsocReqCBC = 0x4, + ProbeCBC = 0x8, + DnPreqCBC = 0x0, + UpPreqCBC = 0x1, + DnReqCBC = 0x0, + UpReqCBC = 0x1 */ { 3, 0x74, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00172111, 0x77ff7777 }, - - { 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00090914, 0x707FFF1F }, + 0x00172111, 0xf7ff7777 }, /* DRReqCBC = 0x0, + IsocPreqCBC = 0x0, + IsocReqCBC = 0x1, + ProbeCBC = 0x7, + DnPreqCBC = 0x2, + UpPreqCBC = 0x1, + DnReqCBC = 0x1, + UpReqCBC = 0x1 */ + + { 3, 0x7c, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL, + 0x00090914, 0x707fff1f }, /* XBar2SriFreeListCBInc = 0x0, + Sri2XbarFreeRspDBC = 0x0, + Sri2XbarFreeXreqDBC = 0x9, + Sri2XbarFreeRspCBC = 0x0, + Sri2XbarFreeXreqCBC = 0x9, + Xbar2SriFreeListCBC = 0x14 */ + + { 3, 0x7c, AMD_DR_Dx, AMD_PTYPE_ALL, + 0x00090a18, 0x707fff1f }, /* XBar2SriFreeListCBInc = 0x0, + Sri2XbarFreeRspDBC = 0x0, + Sri2XbarFreeXreqDBC = 0x9, + Sri2XbarFreeRspCBC = 0x0, + Sri2XbarFreeXreqCBC = 0x9, + Xbar2SriFreeListCBC = 0x14 */ /* Errata 281 Workaround */ { 3, 0x7C, ( AMD_DR_B0 | AMD_DR_B1), AMD_PTYPE_SVR, 0x00144514, 0x707FFF1F }, - { 3, 0x7C, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x040d0f16, 0x07ffff1f }, + { 3, 0x7c, AMD_FAM15_ALL, AMD_PTYPE_ALL, + 0x040d0f16, 0x77ffff1f }, /* XBar2SriFreeListCBInc = 0x0, + SrqExtFreeListBC = 0x8, + Sri2XbarFreeRspDBC = 0x0, + Sri2XbarFreeXreqDBC = 0xd, + Sri2XbarFreeRspCBC = 0x0, + Sri2XbarFreeXreqCBC = 0xf, + Xbar2SriFreeListCBC = 0x16 */ { 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x00070814, 0x007FFF1F }, @@ -630,18 +726,16 @@ static const struct { 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */ { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x00000000, 0x000000FF }, /* Provide clear setting for logical - completeness */ + 0x0000005a, 0x000000ff }, /* Use common "safe" setting for K10 */ { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x00000000, 0x000000FF }, /* Provide clear setting for logical - completeness */ + 0x0000005a, 0x000000ff }, /* Use common "safe" setting for K10 */ { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ + 0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ + 0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ /* Link Phy Receiver Loop Filter Registers */ { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, @@ -664,24 +758,29 @@ static const struct { 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h, [20:16] RttIndex = 04h */ -/* FIXME - * Causes lockups for some reason when more than one package is installed - * Debug and reactivate! - */ -// #if 0 { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x00000000, 0x000000FF }, /* Provide clear setting for logical - completeness */ + 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa, + P0XmtRdPtr = 0x2 + P1RcvRdPtr = 0xa + P1XmtRdPtr = 0x0 */ { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x00000000, 0x000000FF }, /* Provide clear setting for logical - completeness */ + 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa, + P0XmtRdPtr = 0x2 + P1RcvRdPtr = 0xa + P1XmtRdPtr = 0x0 */ { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ + 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd, + P0XmtRdPtr = 0x4 + P1RcvRdPtr = 0xd + P1XmtRdPtr = 0x0 */ { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ + 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd, + P0XmtRdPtr = 0x4 + P1RcvRdPtr = 0xd + P1XmtRdPtr = 0x0 */ /* Link Phy Receiver Loop Filter Registers */ { 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, @@ -702,6 +801,5 @@ static const struct { { 0xC0, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h, - [20:16] RttIndex = 04h */ -// #endif + [20:16] RttIndex = 04h */ };

1 0

Patch set updated for coreboot: northbridge/amd/amdfam10: Add probe filter support
by Timothy Pearson 16 Nov '15

16 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12021 -gerrit commit 005e15b1c92d1a699087ed0883821ecba41bdece Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 2 21:06:39 2015 -0500 northbridge/amd/amdfam10: Add probe filter support All modern Opteron processors support the HT probe filter, which helps to increase coherent fabric performance by reducing the number of HT transactions per cache probe. AMD recommends that the probe filter be enabled on all systems with more than two nodes, and it does not hurt to enable it on systems with 2 nodes. Change-Id: I00a27a828260be8685ae622cfa5a4995add95a8e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 13 ++ .../amd/family_10h-family_15h/model_10xxx_init.c | 22 ++++ src/northbridge/amd/amdfam10/northbridge.c | 144 ++++++++++++++++++++- src/northbridge/amd/amdht/h3ncmn.c | 22 ++++ 4 files changed, 200 insertions(+), 1 deletion(-) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index a421bfcc..a6d8dc4 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -441,6 +441,19 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) cpuSetAMDMSR(id.nodeid); + /* Set up probe filter support */ + if (is_gt_rev_d()) { + uint8_t node_count; + node_count = (pci_read_config32(NODE_PCI(id.nodeid, 0), 0x60) >> 4) & 0x7; + node_count++; + + if (node_count > 1) { + msr_t msr = rdmsr(BU_CFG2_MSR); + msr.hi |= 1 << (42 - 32); + wrmsr(BU_CFG2_MSR, msr); + } + } + #if CONFIG_SET_FIDVID #if CONFIG_LOGICAL_CPUS && CONFIG_SET_FIDVID_CORE0_ONLY // Run on all AP for proper FID/VID setup. diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index 0a86966..4ccf79d 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -50,6 +50,28 @@ static inline uint8_t is_fam15h(void) return fam15h; } +static inline uint8_t is_gt_rev_d(void) +{ + uint8_t fam15h = 0; + uint8_t rev_gte_d = 0; + uint32_t family; + uint32_t model; + + family = model = cpuid_eax(0x80000001); + model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + if ((model >= 0x8) || fam15h) + /* Revision D or later */ + rev_gte_d = 1; + + return rev_gte_d; +} + static volatile uint8_t fam15h_startup_flags[MAX_NODES_SUPPORTED][MAX_CORES_SUPPORTED] = {{ 0 }}; static void model_10xxx_init(device_t dev) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index a922496..8651ad0 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -26,10 +26,13 @@ #include <lib.h> #include <smbios.h> #include <cpu/cpu.h> +#include <delay.h> #include <cpu/x86/lapic.h> +#include <cpu/x86/cache.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> +#include <cpu/amd/model_10xxx_msr.h> #include <cpu/amd/family_10h-family_15h/ram_calc.h> #if CONFIG_LOGICAL_CPUS @@ -1523,7 +1526,7 @@ static void cpu_bus_scan(device_t dev) if(i>=32) { busn--; devn-=32; - pbus = pci_domain->link_list->next); + pbus = pci_domain->link_list->next; } #endif @@ -1643,8 +1646,147 @@ static void cpu_bus_scan(device_t dev) } } +static void detect_and_enable_probe_filter(device_t dev) +{ + uint32_t dword; + + uint8_t fam15h = 0; + uint8_t rev_gte_d = 0; + uint8_t dual_node = 0; + unsigned nb_cfg_54; + uint32_t f3xe8; + uint32_t family; + uint32_t model; + + family = model = cpuid_eax(0x80000001); + model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); + + if (is_fam15h()) { + /* Family 15h or later */ + fam15h = 1; + nb_cfg_54 = 1; + } + + if ((model >= 0x8) || fam15h) + /* Revision D or later */ + rev_gte_d = 1; + + if (rev_gte_d) + /* Check for dual node capability */ + if (f3xe8 & 0x20000000) + dual_node = 1; + + if (rev_gte_d && (sysconf.nodes > 1)) { + /* Enable the probe filter */ + uint8_t i; + uint8_t pfmode = 0x0; + + uint32_t f3x58[MAX_NODES_SUPPORTED]; + uint32_t f3x5c[MAX_NODES_SUPPORTED]; + + printk(BIOS_DEBUG, "Enabling probe filter\n"); + + /* Disable L3 and DRAM scrubbers and configure system for probe filter support */ + for (i = 0; i < sysconf.nodes; i++) { + device_t f2x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 2)); + device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); + + f3x58[i] = pci_read_config32(f3x_dev, 0x58); + f3x5c[i] = pci_read_config32(f3x_dev, 0x5c); + pci_write_config32(f3x_dev, 0x58, f3x58[i] & ~((0x1f << 24) | 0x1f)); + pci_write_config32(f3x_dev, 0x5c, f3x5c[i] & ~0x1); + + dword = pci_read_config32(f2x_dev, 0x1b0); + dword &= ~(0x7 << 8); /* CohPrefPrbLmt = 0x0 */ + pci_write_config32(f2x_dev, 0x1b0, dword); + + msr_t msr = rdmsr_amd(BU_CFG2_MSR); + msr.hi |= 1 << (42 - 32); + wrmsr_amd(BU_CFG2_MSR, msr); + + if (is_fam15h()) { + uint8_t subcache_size = 0x0; + uint8_t pref_so_repl = 0x0; + uint32_t f3x1c4 = pci_read_config32(f3x_dev, 0x1c4); + if ((f3x1c4 & 0xffff) == 0xcccc) { + subcache_size = 0x1; + pref_so_repl = 0x2; + pfmode = 0x3; + } else { + pfmode = 0x2; + } + + dword = pci_read_config32(f3x_dev, 0x1d4); + dword |= 0x1 << 29; /* PFLoIndexHashEn = 0x1 */ + dword &= ~(0x3 << 20); /* PFPreferredSORepl = pref_so_repl */ + dword |= (pref_so_repl & 0x3) << 20; + dword |= 0x1 << 17; /* PFWayHashEn = 0x1 */ + dword |= 0xf << 12; /* PFSubCacheEn = 0xf */ + dword &= ~(0x3 << 10); /* PFSubCacheSize3 = subcache_size */ + dword |= (subcache_size & 0x3) << 10; + dword &= ~(0x3 << 8); /* PFSubCacheSize2 = subcache_size */ + dword |= (subcache_size & 0x3) << 8; + dword &= ~(0x3 << 6); /* PFSubCacheSize1 = subcache_size */ + dword |= (subcache_size & 0x3) << 6; + dword &= ~(0x3 << 4); /* PFSubCacheSize0 = subcache_size */ + dword |= (subcache_size & 0x3) << 4; + dword &= ~(0x3 << 2); /* PFWayNum = 0x2 */ + dword |= 0x2 << 2; + pci_write_config32(f3x_dev, 0x1d4, dword); + } else { + pfmode = 0x2; + + dword = pci_read_config32(f3x_dev, 0x1d4); + dword |= 0x1 << 29; /* PFLoIndexHashEn = 0x1 */ + dword &= ~(0x3 << 20); /* PFPreferredSORepl = 0x2 */ + dword |= 0x2 << 20; + dword |= 0xf << 12; /* PFSubCacheEn = 0xf */ + dword &= ~(0x3 << 10); /* PFSubCacheSize3 = 0x0 */ + dword &= ~(0x3 << 8); /* PFSubCacheSize2 = 0x0 */ + dword &= ~(0x3 << 6); /* PFSubCacheSize1 = 0x0 */ + dword &= ~(0x3 << 4); /* PFSubCacheSize0 = 0x0 */ + dword &= ~(0x3 << 2); /* PFWayNum = 0x2 */ + dword |= 0x2 << 2; + pci_write_config32(f3x_dev, 0x1d4, dword); + } + } + + udelay(40); + + disable_cache(); + asm("wbinvd"); + for (i = 0; i < sysconf.nodes; i++) { + device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); + + dword = pci_read_config32(f3x_dev, 0x1c4); + dword |= (0x1 << 31); /* L3TagInit = 1 */ + pci_write_config32(f3x_dev, 0x1c4, dword); + do { + } while (pci_read_config32(f3x_dev, 0x1c4) & (0x1 << 31)); + + dword = pci_read_config32(f3x_dev, 0x1d4); + dword &= ~0x3; /* PFMode = pfmode */ + dword |= pfmode & 0x3; + pci_write_config32(f3x_dev, 0x1d4, dword); + do { + } while (!(pci_read_config32(f3x_dev, 0x1d4) & (0x1 << 19))); + } + enable_cache(); + + /* Reenable L3 and DRAM scrubbers */ + for (i = 0; i < sysconf.nodes; i++) { + device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); + + pci_write_config32(f3x_dev, 0x58, f3x58[i]); + pci_write_config32(f3x_dev, 0x5c, f3x5c[i]); + } + + } +} + static void cpu_bus_init(device_t dev) { + detect_and_enable_probe_filter(dev); initialize_cpus(dev->link_list); #if CONFIG_AMD_SB_CIMX sb_After_Pci_Init(); diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index 01c0e48..8ee929d 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -103,6 +103,28 @@ static inline uint8_t is_fam15h(void) return fam15h; } +static inline uint8_t is_gt_rev_d(void) +{ + uint8_t fam15h = 0; + uint8_t rev_gte_d = 0; + uint32_t family; + uint32_t model; + + family = model = cpuid_eax(0x80000001); + model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + if ((model >= 0x8) || fam15h) + /* Revision D or later */ + rev_gte_d = 1; + + return rev_gte_d; +} + /***************************************************************************//** * * SBDFO

1 0

Patch set updated for coreboot: cpu/amd/fam10h-fam15h: Update Fam15h APIC config and startup sequence
by Timothy Pearson 16 Nov '15

16 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12020 -gerrit commit dd0cbfd84723e77fb9495ded6ea3cf58f5f4924a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jul 30 14:07:15 2015 -0500 cpu/amd/fam10h-fam15h: Update Fam15h APIC config and startup sequence This fixes Family 15h multiple package support; the previous code hung in CAR setup and romstage when more than one CPU package was installed for a variety of loosely related reasons. TEST: Booted ASUS KGPE-D16 with two Opteron 6328 processors and several different RDIMM configurations. Change-Id: I171197c90f72d3496a385465937b7666cbf7e308 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/car/cache_as_ram.inc | 17 ++- src/cpu/amd/family_10h-family_15h/defaults.h | 88 +++++++++++--- src/cpu/amd/family_10h-family_15h/fidvid.c | 81 ++++++------- src/cpu/amd/family_10h-family_15h/init_cpus.c | 66 +++++++++-- src/cpu/amd/quadcore/quadcore.c | 19 +-- src/cpu/amd/quadcore/quadcore_id.c | 1 - src/mainboard/advansus/a785e-i/romstage.c | 2 +- src/mainboard/amd/bimini_fam10/romstage.c | 2 +- src/mainboard/amd/mahogany_fam10/romstage.c | 2 +- .../amd/serengeti_cheetah_fam10/romstage.c | 2 +- src/mainboard/amd/tilapia_fam10/romstage.c | 2 +- src/mainboard/asus/kfsn4-dre/romstage.c | 2 +- src/mainboard/asus/kgpe-d16/romstage.c | 46 +++++-- src/mainboard/asus/m4a78-em/romstage.c | 2 +- src/mainboard/asus/m4a785-m/romstage.c | 2 +- src/mainboard/asus/m5a88-v/romstage.c | 2 +- src/mainboard/avalue/eax-785e/romstage.c | 2 +- src/mainboard/gigabyte/ma785gm/romstage.c | 2 +- src/mainboard/gigabyte/ma785gmt/romstage.c | 2 +- src/mainboard/gigabyte/ma78gm/romstage.c | 2 +- src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 +- src/mainboard/iei/kino-780am2-fam10/romstage.c | 2 +- src/mainboard/jetway/pa78vm5/romstage.c | 2 +- src/mainboard/msi/ms9652_fam10/romstage.c | 2 +- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 2 +- src/mainboard/supermicro/h8qme_fam10/romstage.c | 2 +- src/mainboard/supermicro/h8scm_fam10/romstage.c | 2 +- src/mainboard/tyan/s2912_fam10/romstage.c | 2 +- src/northbridge/amd/amdht/h3finit.c | 57 ++++++++- src/northbridge/amd/amdht/h3ncmn.c | 30 ++++- src/northbridge/amd/amdht/ht_wrapper.c | 132 +++++++++++++++++++-- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 1 + 32 files changed, 457 insertions(+), 123 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index cbb1e39..5305603 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -548,8 +548,23 @@ CAR_FAM10_ap: /* Fam10h NB config bit 54 was not set */ rolb %cl, %bl roll_cfg: + jmp_if_not_fam15h(ap_apicid_ready) + cmp $0x5, %ecx + jne ap_apicid_ready - /* Calculate stack pointer. */ + /* This is a multi-node CPU + * Adjust the maximum APIC ID to a more reasonable value + * given that no 32-core Family 15h processors exist + */ + movl %ebx, %ecx + and $0x0f, %ecx /* Get lower 4 bits of CPU number */ + and $0x60, %ebx /* Get node ID */ + shrl $0x1, %ebx /* Shift node ID part of APIC ID down by 1 */ + or %ecx, %ebx /* Recombine node ID and CPU number */ + +ap_apicid_ready: + + /* Calculate stack pointer using adjusted APIC ID stored in ebx */ movl $CacheSizeAPStack, %eax mull %ebx movl $(CacheBase + (CacheSize - (CacheSizeBSPStack + CacheSizeBSPSlush))), %esp diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index 94468c5..b6c9bc4 100644 --- a/src/cpu/amd/family_10h-family_15h/defaults.h +++ b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -240,18 +240,37 @@ static const struct { { 0, 0x68, (AMD_DR_B0 | AMD_DR_B1), AMD_PTYPE_SVR, 0x00200000, 0x00600000 }, /* [22:21] DsNpReqLmt0 = 01b */ - { 0, 0x84, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, + { 0, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ - { 0, 0xA4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, + { 0, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ - { 0, 0xC4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, + { 0, 0xC4, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ - { 0, 0xE4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, + { 0, 0xE4, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ + /* FIXME + * Non-C32 packages only + */ + { 0, 0x84, AMD_FAM15_ALL, AMD_PTYPE_ALL, + 0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ + + { 0, 0xA4, AMD_FAM15_ALL, AMD_PTYPE_ALL, + 0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ + + { 0, 0xC4, AMD_FAM15_ALL, AMD_PTYPE_ALL, + 0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ + + { 0, 0xE4, AMD_FAM15_ALL, AMD_PTYPE_ALL, + 0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ + + /* FIXME + * C32 package is not supported at this time + */ + /* Link Global Retry Control Register */ { 0, 0x150, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, 0x00073900, 0x00073F00 }, @@ -610,38 +629,79 @@ static const struct { { 0x530A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */ - { 0xCF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + 0x00000000, 0x000000FF }, /* Provide clear setting for logical + completeness */ + + { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + 0x00000000, 0x000000FF }, /* Provide clear setting for logical + completeness */ + + { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ + + { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ + + /* Link Phy Receiver Loop Filter Registers */ + { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, + [21:14] LfcMin = 10h */ + + { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, + [21:14] LfcMin = 10h */ + + { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, + [21:14] LfcMin = 08h */ + + { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, + [21:14] LfcMin = 08h */ + + { 0xC0, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h, + [20:16] RttIndex = 04h */ + +/* FIXME + * Causes lockups for some reason when more than one package is installed + * Debug and reactivate! + */ +// #if 0 + { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, 0x00000000, 0x000000FF }, /* Provide clear setting for logical completeness */ - { 0xDF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, 0x00000000, 0x000000FF }, /* Provide clear setting for logical completeness */ - { 0xCF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ - { 0xDF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ /* Link Phy Receiver Loop Filter Registers */ - { 0xD1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + { 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, [21:14] LfcMin = 10h */ - { 0xC1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + { 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, [21:14] LfcMin = 10h */ - { 0xD1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + { 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, [21:14] LfcMin = 08h */ - { 0xC1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + { 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, [21:14] LfcMin = 08h */ - { 0xC0, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0xC0, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h, - [20:16] RttIndex = 04h */ + [20:16] RttIndex = 04h */ +// #endif }; diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 3af18bd..8a006cb 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -629,44 +629,45 @@ static void prep_fid_change(void) } static void waitCurrentPstate(u32 target_pstate) { - msr_t initial_msr = rdmsr(TSC_MSR); - msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR); - msr_t tsc_msr; - u8 timedout ; - - /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a - * P1 that is a copy of P0, therefore has the same NB DID but the - * TSC will count twice per tick, so we have to wait for twice the - * count to achieve the desired timeout. But I'm likely to - * misunderstand this... - */ - u32 corrected_timeout = ( (pstate_msr.lo==1) - && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ? - WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT ; - msr_t timeout; - - timeout.lo = initial_msr.lo + corrected_timeout ; - timeout.hi = initial_msr.hi; - if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) { - timeout.hi++; - } - - // assuming TSC ticks at 1.25 ns per tick (800 MHz) - do { - pstate_msr = rdmsr(CUR_PSTATE_MSR); - tsc_msr = rdmsr(TSC_MSR); - timedout = (tsc_msr.hi > timeout.hi) - || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo )); - } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ; - - if (pstate_msr.lo != target_pstate) { - msr_t limit_msr = rdmsr(0xc0010061); - printk(BIOS_ERR, "*** Time out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%08x %08x\n", target_pstate, pstate_msr.lo, limit_msr.hi, limit_msr.lo); - - do { // should we just go on instead ? - pstate_msr = rdmsr(CUR_PSTATE_MSR); - } while ( pstate_msr.lo != target_pstate ) ; - } + msr_t initial_msr = rdmsr(TSC_MSR); + msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR); + msr_t tsc_msr; + u8 timedout ; + + /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a + * P1 that is a copy of P0, therefore has the same NB DID but the + * TSC will count twice per tick, so we have to wait for twice the + * count to achieve the desired timeout. But I'm likely to + * misunderstand this... + */ + u32 corrected_timeout = ((pstate_msr.lo==1) + && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ? + WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT; + msr_t timeout; + + timeout.lo = initial_msr.lo + corrected_timeout ; + timeout.hi = initial_msr.hi; + if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) { + timeout.hi++; + } + + // assuming TSC ticks at 1.25 ns per tick (800 MHz) + do { + pstate_msr = rdmsr(CUR_PSTATE_MSR); + tsc_msr = rdmsr(TSC_MSR); + timedout = (tsc_msr.hi > timeout.hi) + || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo )); + } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ; + + if (pstate_msr.lo != target_pstate) { + msr_t limit_msr = rdmsr(0xc0010061); + printk(BIOS_ERR, "*** APIC ID %02x: timed out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%08x %08x\n", + cpuid_ebx(0x00000001) >> 24, target_pstate, pstate_msr.lo, limit_msr.hi, limit_msr.lo); + + do { // should we just go on instead ? + pstate_msr = rdmsr(CUR_PSTATE_MSR); + } while ( pstate_msr.lo != target_pstate ) ; + } } static void set_pstate(u32 nonBoostedPState) { @@ -1060,13 +1061,13 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) APs and BSP */ ap_apicidx.num = 0; - for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx); + for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, -1, store_ap_apicid, &ap_apicidx); for (i = 0; i < ap_apicidx.num; i++) { init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv); } #else - for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); + for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, -1, init_fidvid_bsp_stage1, &fv); #endif print_debug_fv("common_fid = ", fv.common_fid); diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index e4721a4..a421bfcc 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -55,6 +55,8 @@ static void set_EnableCf8ExtCfg(void) static void set_EnableCf8ExtCfg(void) { } #endif +// #define DEBUG_HT_SETUP 1 +// #define FAM10_AP_NODE_SEQUENTIAL_START 1 typedef void (*process_ap_t) (u32 apicid, void *gp); @@ -139,8 +141,8 @@ uint32_t get_boot_apic_id(uint8_t node, uint32_t core) { //core range = 1 : core 0 only //core range = 2 : cores other than core0 -static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap, - void *gp) +static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node, + process_ap_t process_ap, void *gp) { // here assume the OS don't change our apicid u32 ap_apicid; @@ -161,6 +163,9 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap, } for (i = 0; i < nodes; i++) { + if ((node >= 0) && (i != node)) + continue; + cores_found = get_core_num_in_bsp(i); u32 jstart, jend; @@ -276,7 +281,7 @@ void wait_all_other_cores_started(u32 bsp_apicid) { // all aps other than core0 printk(BIOS_DEBUG, "started ap apicid: "); - for_each_ap(bsp_apicid, 2, wait_ap_started, (void *)0); + for_each_ap(bsp_apicid, 2, -1, wait_ap_started, (void *)0); printk(BIOS_DEBUG, "\n"); } @@ -369,8 +374,10 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) /* NB_CFG MSR is shared between cores, so we need make sure core0 is done at first --- use wait_all_core0_started */ if (id.coreid == 0) { - set_apicid_cpuid_lo(); /* only set it on core0 */ - set_EnableCf8ExtCfg(); /* only set it on core0 */ + /* Set InitApicIdCpuIdLo / EnableCf8ExtCfg on core0 only */ + if (!is_fam15h()) + set_apicid_cpuid_lo(); + set_EnableCf8ExtCfg(); #if CONFIG_ENABLE_APIC_EXT_ID enable_apic_ext_id(id.nodeid); #endif @@ -423,6 +430,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) } // Mark the core as started. lapic_write(LAPIC_MSG_REG, (apicid << 24) | F10_APSTATE_STARTED); + printk(BIOS_DEBUG, "CPU APICID %02x start flag set\n", apicid); if (apicid != bsp_apicid) { /* Setup each AP's cores MSRs. @@ -584,6 +592,34 @@ static void setup_remote_node(u8 node) } #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */ +//it is running on core0 of node0 +static void start_other_cores(uint32_t bsp_apicid) +{ + u32 nodes; + u32 nodeid; + + // disable multi_core + if (read_option(multi_core, 0) != 0) { + printk(BIOS_DEBUG, "Skip additional core init\n"); + return; + } + + nodes = get_nodes(); + + for (nodeid = 0; nodeid < nodes; nodeid++) { + u32 cores = get_core_num_in_bsp(nodeid); + printk(BIOS_DEBUG, "init node: %02x cores: %02x pass 1\n", nodeid, cores); + if (cores > 0) { + real_start_other_core(nodeid, cores); +#ifdef FAM10_AP_NODE_SEQUENTIAL_START + printk(BIOS_DEBUG, "waiting for core start on node %d...\n", nodeid); + for_each_ap(bsp_apicid, 2, nodeid, wait_ap_started, (void *)0); + printk(BIOS_DEBUG, "...started\n"); +#endif + } + } +} + static void AMD_Errata281(u8 node, uint64_t revision, u32 platform) { /* Workaround for Transaction Scheduling Conflict in @@ -843,6 +879,10 @@ static void AMD_SetHtPhyRegister(u8 node, u8 link, u8 entry) phyBase = ((u32) link << 3) | 0x180; + /* Determine if link is connected and abort if not */ + if (!(pci_read_config32(NODE_PCI(node, 0), 0x98 + (link * 0x20)) & 0x1)) + return; + /* Get the portal control register's initial value * and update it to access the desired phy register */ @@ -1005,10 +1045,11 @@ static void cpuSetAMDPCI(u8 node) * Hypertransport initialization has taken place. Also note * that it is run for the first core on each node */ - u8 i, j; + uint8_t i; + uint8_t j; u32 platform; u32 val; - u8 offset; + uint8_t offset; uint32_t dword; uint64_t revision; @@ -1035,6 +1076,17 @@ static void cpuSetAMDPCI(u8 node) } } +#ifdef DEBUG_HT_SETUP + /* Dump link settings */ + for (i = 0; i < 4; i++) { + for (j = 0; j < 4; j++) { + printk(BIOS_DEBUG, "Node %d link %d: type register: %08x control register: %08x extended control sublink 0: %08x 1: %08x\n", i, j, + pci_read_config32(NODE_PCI(i, 0), 0x98 + (j * 0x20)), pci_read_config32(NODE_PCI(i, 0), 0x84 + (j * 0x20)), + pci_read_config32(NODE_PCI(i, 0), 0x170 + (j * 0x4)), pci_read_config32(NODE_PCI(i, 0), 0x180 + (j * 0x4))); + } + } +#endif + for (i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) { if ((fam10_htphy_default[i].revision & revision) && (fam10_htphy_default[i].platform & platform)) { diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c index 0f7c728..3ca7f3e 100644 --- a/src/cpu/amd/quadcore/quadcore.c +++ b/src/cpu/amd/quadcore/quadcore.c @@ -27,21 +27,6 @@ uint32_t get_boot_apic_id(uint8_t node, uint32_t core); uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2); -static inline uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - static u32 get_core_num_in_bsp(u32 nodeid) { u32 dword; @@ -137,6 +122,7 @@ static void real_start_other_core(uint32_t nodeid, uint32_t cores) } } +#if (!IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) //it is running on core0 of node0 static void start_other_cores(void) { @@ -153,9 +139,10 @@ static void start_other_cores(void) for (nodeid = 0; nodeid < nodes; nodeid++) { u32 cores = get_core_num_in_bsp(nodeid); - printk(BIOS_DEBUG, "init node: %02x cores: %02x pass 1 \n", nodeid, cores); + printk(BIOS_DEBUG, "init node: %02x cores: %02x pass 1\n", nodeid, cores); if (cores > 0) { real_start_other_core(nodeid, cores); } } } +#endif diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c index acfdb49..99e6d68 100644 --- a/src/cpu/amd/quadcore/quadcore_id.c +++ b/src/cpu/amd/quadcore/quadcore_id.c @@ -104,7 +104,6 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54) id.nodeid = apicid & 0x7; } } - if (fam15h && dual_node) { /* Coreboot expects each separate processor die to be on a different nodeid. * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed... diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index b17fb2b..55c94a6 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 11d5479..be381a1 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -143,7 +143,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 5b39bb7..3428aab 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 5131f36..0c84b6d 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -251,7 +251,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 0804b32..68281e7 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 8686be7..e7ad0b1 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -284,7 +284,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); } diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 3a68230..be91eaa 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -93,7 +93,18 @@ static void switch_spd_mux(uint8_t channel) pci_write_config8(PCI_DEV(0, 0x14, 0), 0x54, byte); } -static const uint8_t spd_addr[] = { +static const uint8_t spd_addr_fam15[] = { + // Socket 0 Node 0 ("Node 0") + RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, + // Socket 0 Node 1 ("Node 1") + RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, + // Socket 1 Node 0 ("Node 2") + RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, + // Socket 1 Node 1 ("Node 3") + RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, +}; + +static const uint8_t spd_addr_fam10[] = { // Socket 0 Node 0 ("Node 0") RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, // Socket 0 Node 1 ("Node 1") @@ -113,10 +124,10 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { switch_spd_mux(0x2); } else if (ctrl->node_id == 1) { printk(BIOS_DEBUG, "enable_spd_node1()\n"); - switch_spd_mux((sysinfo->nodes <= 2)?0x2:0x3); + switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x2:0x3); } else if (ctrl->node_id == 2) { printk(BIOS_DEBUG, "enable_spd_node2()\n"); - switch_spd_mux((sysinfo->nodes <= 2)?0x3:0x2); + switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x3:0x2); } else if (ctrl->node_id == 3) { printk(BIOS_DEBUG, "enable_spd_node3()\n"); switch_spd_mux(0x3); @@ -303,18 +314,25 @@ static void execute_memory_test(void) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { + uint32_t esp; + __asm__ volatile ( + "movl %%esp, %0" + : "=r" (esp) + ); + struct sys_info *sysinfo = &sysinfo_car; uint32_t bsp_apicid = 0, val; uint8_t byte; msr_t msr; - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - int s3resume = acpi_is_wakeup_s3(); if (!cpu_init_detectedx && boot_cpu()) { + /* Initial timestamp */ + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ set_bsp_node_CHtExtNodeCfgEn(); @@ -338,6 +356,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pci_write_config8(PCI_DEV(0, 0x14, 3), 0x78, byte); } + printk(BIOS_SPEW, "Initial stack pointer: %08x\n", esp); + post_code(0x30); if (bist == 0) @@ -396,7 +416,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); } @@ -454,7 +474,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* It's the time to set ctrl in sysinfo now; */ printk(BIOS_DEBUG, "fill_mem_ctrl() detected %d nodes\n", sysinfo->nodes); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + if (is_fam15h()) + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam15); + else + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam10); post_code(0x3D); #if 0 @@ -526,5 +549,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { + /* Force BUID to 0 */ + static const u8 swaplist[] = {0, 0, 0xFF, 0, 0xFF}; + if ((node == 0) && (link == 1)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + return 0; } diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index f717ed8..844fc93 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 47d884c..e43dbbc 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index b69fd80..1630497 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -148,7 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index ed85c82..ff1aa9e 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index c5a0433..baf49af 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 743463d..b8ab282 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index aee7fbe..43bae3c 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index bf1b734..84e28f7 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index bb0ba57..7b00176 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 9144f32..8c87563 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -150,7 +150,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index cb4d02f..f4413ed 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); printk(BIOS_DEBUG, "wait_all_other_cores_started()\n"); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index c29470f..bf5093f 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -167,7 +167,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index eacc87f..13a1011 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -234,7 +234,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 6e34f0a..7312683 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 9f25d27..ed211d9 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -169,7 +169,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index c9a310b..bcdcfa2 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -385,13 +385,49 @@ static u8 convertNodeToLink(u8 srcNode, u8 targetNode, sMainData *pDat) */ static void htDiscoveryFloodFill(sMainData *pDat) { - u8 currentNode = 0; - u8 currentLink; + uint8_t currentNode = 0; + uint8_t currentLink; + uint8_t currentLinkID; + + /* NOTE + * Each node inside a dual node (socket G34) processor must share + * an adjacent node ID. Alter the link scan order such that the + * other internal node is always scanned first... + */ + uint8_t currentLinkScanOrder_Default[8] = {0, 1, 2, 3, 4, 5, 6, 7}; + uint8_t currentLinkScanOrder_G34_Fam10[8] = {1, 0, 2, 3, 4, 5, 6, 7}; + uint8_t currentLinkScanOrder_G34_Fam15[8] = {2, 0, 1, 3, 4, 5, 6, 7}; + + uint8_t fam15h = 0; + uint8_t rev_gte_d = 0; + uint8_t dual_node = 0; + uint32_t f3xe8; + uint32_t family; + uint32_t model; + + f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8); + + family = model = cpuid_eax(0x80000001); + model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) { + /* Family 15h or later */ + fam15h = 1; + } + + if ((model >= 0x8) || fam15h) + /* Revision D or later */ + rev_gte_d = 1; + + if (rev_gte_d) + /* Check for dual node capability */ + if (f3xe8 & 0x20000000) + dual_node = 1; /* Entries are always added in pairs, the even indices are the 'source' * side closest to the BSP, the odd indices are the 'destination' side */ - while (currentNode <= pDat->NodesDiscovered) { u32 temp; @@ -419,11 +455,24 @@ static void htDiscoveryFloodFill(sMainData *pDat) /* Enable routing tables on currentNode*/ pDat->nb->enableRoutingTables(currentNode, pDat->nb); - for (currentLink = 0; currentLink < pDat->nb->maxLinks; currentLink++) + for (currentLinkID = 0; currentLinkID < pDat->nb->maxLinks; currentLinkID++) { BOOL linkfound; u8 token; + if (currentLinkID < 8) { + if (dual_node) { + if (fam15h) + currentLink = currentLinkScanOrder_G34_Fam15[currentLinkID]; + else + currentLink = currentLinkScanOrder_G34_Fam10[currentLinkID]; + } else { + currentLink = currentLinkScanOrder_Default[currentLinkID]; + } + } else { + currentLink = currentLinkID; + } + if (pDat->HtBlock->AMD_CB_IgnoreLink && pDat->HtBlock->AMD_CB_IgnoreLink(currentNode, currentLink)) continue; diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index ac7d393..01c0e48 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -47,8 +47,9 @@ #define REG_NODE_ID_0X60 0x60 #define REG_UNIT_ID_0X64 0x64 #define REG_LINK_TRANS_CONTROL_0X68 0x68 -#define REG_LINK_INIT_CONTROL_0X6C 0x6C +#define REG_LINK_INIT_CONTROL_0X6C 0x6c #define REG_HT_CAP_BASE_0X80 0x80 +#define REG_NORTHBRIDGE_CFG_3X8C 0x8c #define REG_HT_LINK_RETRY0_0X130 0x130 #define REG_HT_TRAFFIC_DIST_0X164 0x164 #define REG_HT_LINK_EXT_CONTROL0_0X170 0x170 @@ -87,6 +88,21 @@ *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS *** ***************************************************************************/ +static inline uint8_t is_fam15h(void) +{ + uint8_t fam15h = 0; + uint32_t family; + + family = cpuid_eax(0x80000001); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + return fam15h; +} + /***************************************************************************//** * * SBDFO @@ -215,8 +231,18 @@ static void writeRoutingTable(u8 node, u8 target, u8 link, cNorthBridge *nb) static void writeNodeID(u8 node, u8 nodeID, cNorthBridge *nb) { - u32 temp = nodeID; + u32 temp; ASSERT((node < nb->maxNodes) && (nodeID < nb->maxNodes)); + if (is_fam15h()) { + temp = 1; + AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(node), + makePCIBusFromNode(node), + makePCIDeviceFromNode(node), + CPU_NB_FUNC_03, + REG_NORTHBRIDGE_CFG_3X8C), + 22, 22, &temp); + } + temp = nodeID; AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(node), makePCIBusFromNode(node), makePCIDeviceFromNode(node), diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 1f38b0c..18c0ac4 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -82,22 +82,129 @@ static u32 get_nodes(void) return nodes; } +static const char * event_class_string_decodes[] = { + [HT_EVENT_CLASS_CRITICAL] = "CRITICAL", + [HT_EVENT_CLASS_ERROR] = "ERROR", + [HT_EVENT_CLASS_HW_FAULT] = "HARDWARE FAULT", + [HT_EVENT_CLASS_WARNING] = "WARNING", + [HT_EVENT_CLASS_INFO] = "INFO" +}; + +static const char * event_string_decodes[] = { + [HT_EVENT_COH_EVENTS] = "HT_EVENT_COH_EVENTS", + [HT_EVENT_COH_NO_TOPOLOGY] = "HT_EVENT_COH_NO_TOPOLOGY", + [HT_EVENT_COH_LINK_EXCEED] = "HT_EVENT_COH_LINK_EXCEED", + [HT_EVENT_COH_FAMILY_FEUD] = "HT_EVENT_COH_FAMILY_FEUD", + [HT_EVENT_COH_NODE_DISCOVERED] = "HT_EVENT_COH_NODE_DISCOVERED", + [HT_EVENT_COH_MPCAP_MISMATCH] = "HT_EVENT_COH_MPCAP_MISMATCH", + [HT_EVENT_NCOH_EVENTS] = "HT_EVENT_NCOH_EVENTS", + [HT_EVENT_NCOH_BUID_EXCEED] = "HT_EVENT_NCOH_BUID_EXCEED", + [HT_EVENT_NCOH_LINK_EXCEED] = "HT_EVENT_NCOH_LINK_EXCEED", + [HT_EVENT_NCOH_BUS_MAX_EXCEED] = "HT_EVENT_NCOH_BUS_MAX_EXCEED", + [HT_EVENT_NCOH_CFG_MAP_EXCEED] = "HT_EVENT_NCOH_CFG_MAP_EXCEED", + [HT_EVENT_NCOH_DEVICE_FAILED] = "HT_EVENT_NCOH_DEVICE_FAILED", + [HT_EVENT_NCOH_AUTO_DEPTH] = "HT_EVENT_NCOH_AUTO_DEPTH", + [HT_EVENT_OPT_EVENTS] = "HT_EVENT_OPT_EVENTS", + [HT_EVENT_OPT_REQUIRED_CAP_RETRY] = "HT_EVENT_OPT_REQUIRED_CAP_RETRY", + [HT_EVENT_OPT_REQUIRED_CAP_GEN3] = "HT_EVENT_OPT_REQUIRED_CAP_GEN3", + [HT_EVENT_HW_EVENTS] = "HT_EVENT_HW_EVENTS", + [HT_EVENT_HW_SYNCHFLOOD] = "HT_EVENT_HW_SYNCHFLOOD", + [HT_EVENT_HW_HTCRC] = "HT_EVENT_HW_HTCRC" +}; /** * void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) */ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) { - u8 i; + uint8_t i; + uint8_t log_level; + uint8_t dump_event_detail; - printk(BIOS_DEBUG, "AMD_CB_EventNotify()\n"); - printk(BIOS_DEBUG, " event class: %02x\n event: %04x\n data: ", evtClass, event); + printk(BIOS_DEBUG, "AMD_CB_EventNotify(): "); - for (i = 0; i < *pEventData0; i++) { - printk(BIOS_DEBUG, " %02x ", *(pEventData0 + i)); + /* Decode event */ + dump_event_detail = 1; + switch (evtClass) { + case HT_EVENT_CLASS_CRITICAL: + case HT_EVENT_CLASS_ERROR: + case HT_EVENT_CLASS_HW_FAULT: + case HT_EVENT_CLASS_WARNING: + case HT_EVENT_CLASS_INFO: + log_level = BIOS_DEBUG; + printk(log_level, event_class_string_decodes[evtClass]); + break; + default: + log_level = BIOS_DEBUG; + printk(log_level, "UNKNOWN"); + break; } - printk(BIOS_DEBUG, "\n"); + printk(log_level, ": "); + switch(event) { + case HT_EVENT_COH_EVENTS: + case HT_EVENT_COH_NO_TOPOLOGY: + case HT_EVENT_COH_LINK_EXCEED: + case HT_EVENT_COH_FAMILY_FEUD: + printk(log_level, event_string_decodes[event]); + break; + case HT_EVENT_COH_NODE_DISCOVERED: + { + printk(log_level, "HT_EVENT_COH_NODE_DISCOVERED"); + sHtEventCohNodeDiscovered *evt = (sHtEventCohNodeDiscovered*)pEventData0; + printk(log_level, ": node %d link %d new node: %d", + evt->node, evt->link, evt->newNode); + dump_event_detail = 0; + break; + } + case HT_EVENT_COH_MPCAP_MISMATCH: + case HT_EVENT_NCOH_EVENTS: + case HT_EVENT_NCOH_BUID_EXCEED: + case HT_EVENT_NCOH_LINK_EXCEED: + case HT_EVENT_NCOH_BUS_MAX_EXCEED: + case HT_EVENT_NCOH_CFG_MAP_EXCEED: + printk(log_level, event_string_decodes[event]); + break; + case HT_EVENT_NCOH_DEVICE_FAILED: + { + printk(log_level, event_string_decodes[event]); + sHtEventNcohDeviceFailed *evt = (sHtEventNcohDeviceFailed*)pEventData0; + printk(log_level, ": node %d link %d depth: %d attemptedBUID: %d", + evt->node, evt->link, evt->depth, evt->attemptedBUID); + dump_event_detail = 0; + break; + } + case HT_EVENT_NCOH_AUTO_DEPTH: + { + printk(log_level, event_string_decodes[event]); + sHtEventNcohAutoDepth *evt = (sHtEventNcohAutoDepth*)pEventData0; + printk(log_level, ": node %d link %d depth: %d", + evt->node, evt->link, evt->depth); + dump_event_detail = 0; + break; + } + case HT_EVENT_OPT_EVENTS: + case HT_EVENT_OPT_REQUIRED_CAP_RETRY: + case HT_EVENT_OPT_REQUIRED_CAP_GEN3: + case HT_EVENT_HW_EVENTS: + case HT_EVENT_HW_SYNCHFLOOD: + case HT_EVENT_HW_HTCRC: + printk(log_level, event_string_decodes[event]); + break; + default: + printk(log_level, "HT_EVENT_UNKNOWN"); + break; + } + printk(log_level, "\n"); + + if (dump_event_detail) { + printk(BIOS_DEBUG, " event class: %02x\n event: %04x\n data: ", evtClass, event); + + for (i = 0; i < *pEventData0; i++) { + printk(BIOS_DEBUG, " %02x ", *(pEventData0 + i)); + } + printk(BIOS_DEBUG, "\n"); + } } /** @@ -206,9 +313,10 @@ void amd_ht_fixup(struct sys_info *sysinfo) { for (node = 0; node < node_count; node++) { f3xe8 = pci_read_config32(NODE_PCI(node, 3), 0xe8); uint8_t internal_node_number = ((f3xe8 & 0xc0000000) >> 30); - printk(BIOS_DEBUG, "amd_ht_fixup(): node %d (internal node ID %d): disabling defective HT link\n", node, internal_node_number); + printk(BIOS_DEBUG, "amd_ht_fixup(): node %d (internal node ID %d): disabling defective HT link", node, internal_node_number); if (internal_node_number == 0) { uint8_t package_link_3_connected = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x98:0xd8) & 0x1; + printk(BIOS_DEBUG, " (L3 connected: %d)\n", package_link_3_connected); if (package_link_3_connected) { /* Set WidthIn and WidthOut to 0 */ dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x84:0xc4); @@ -230,15 +338,21 @@ void amd_ht_fixup(struct sys_info *sysinfo) { } } else if (internal_node_number == 1) { uint8_t package_link_3_connected = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0xf8:0xb8) & 0x1; + printk(BIOS_DEBUG, " (L3 connected: %d)\n", package_link_3_connected); if (package_link_3_connected) { /* Set WidthIn and WidthOut to 0 */ dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0xe4:0xa4); dword &= ~0x77000000; pci_write_config32(NODE_PCI(node, 0), (fam15h)?0xe4:0xa4, dword); /* Set Ganged to 1 */ - dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x18c:0x174); + /* WARNING + * The Family 15h BKDG states that 0x18c should be set, + * however this is in error. 0x17c is the correct control + * register (sublink 0) for these processors... + */ + dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x17c:0x174); dword |= 0x00000001; - pci_write_config32(NODE_PCI(node, 0), (fam15h)?0x18c:0x174, dword); + pci_write_config32(NODE_PCI(node, 0), (fam15h)?0x17c:0x174, dword); } else { /* Set ConnDly to 1 */ dword = pci_read_config32(NODE_PCI(node, 0), 0x16c); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 25c4042..bfe7515 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -5451,6 +5451,7 @@ static void mct_InitialMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc cpu_divisor = (0x1 << cpu_did); pMCTstat->TSCFreq = (100 * (cpu_fid + 0x10)) / cpu_divisor; + printk(BIOS_DEBUG, "mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15\n"); mct_ForceNBPState0_En_Fam15(pMCTstat, pDCTstat); } else { /* K10 BKDG v3.62 section 2.8.9.2 */

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2015