coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: google/lars: Enable wake from touch pad
by Patrick Georgi 16 Nov '15

16 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12449 -gerrit commit fa847b301b9114c7897c8958885b8d44e4477b02 Author: david <david_wu(a)quantatw.com> Date: Tue Nov 10 15:00:18 2015 +0800 google/lars: Enable wake from touch pad This patch enables GPP_B5 as ACPI_SCI for wake. It also defines touchpad wake device in ACPI with GPE0_DW0_05 for _PRW. BUG=none BRANCH=none TEST=emerge-lars coreboot Change-Id: I2b65f6a37783ecdbdbc32ebe613243e042c865e9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ec5b629f920984564f12f2c09458ed300d031f69 Original-Change-Id: I9bd2b3595ae833fa5d07d97a7cda4a29041be837 Original-Signed-off-by: David Wu <David_Wu(a)quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311890 Original-Commit-Ready: David Wu <david_wu(a)quantatw.com> Original-Tested-by: David Wu <david_wu(a)quantatw.com> Original-Reviewed-by: Shawn N <shawnn(a)chromium.org> --- src/mainboard/google/lars/acpi/mainboard.asl | 2 ++ src/mainboard/google/lars/gpio.h | 5 ++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/lars/acpi/mainboard.asl b/src/mainboard/google/lars/acpi/mainboard.asl index 8ac349b..a5a90c6 100644 --- a/src/mainboard/google/lars/acpi/mainboard.asl +++ b/src/mainboard/google/lars/acpi/mainboard.asl @@ -124,6 +124,8 @@ Scope (\_SB.PCI0.I2C1) } }) + Name (_PRW, Package() { GPE_TOUCHPAD_WAKE, 0x3 }) + Method (_STA) { Return (0xF) diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/lars/gpio.h index 80a97fd..7ebeb5d 100755 --- a/src/mainboard/google/lars/gpio.h +++ b/src/mainboard/google/lars/gpio.h @@ -38,6 +38,9 @@ /* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */ #define GPE_WLAN_WAKE GPE0_DW0_16 +/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */ +#define GPE_TOUCHPAD_WAKE GPE0_DW0_05 + /* Input device interrupt configuration */ #define TOUCHPAD_INT_L GPP_B3_IRQ #define TOUCHSCREEN_INT_L GPP_E7_IRQ @@ -79,7 +82,7 @@ static const struct pad_config gpio_table[] = { /* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP), /* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 0, DEEP), -/* SRCCLKREQ0# */ /* GPP_B5 */ +/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* SRCCLKREQ3# */ /* GPP_B8 */

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New patch to review for coreboot: google/chell: Turn on keyboard backlight in romstage
by Patrick Georgi 16 Nov '15

16 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12448 -gerrit commit 05bb5840975ab1cf0b2693e8a4461f88b936e0c7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Nov 12 16:39:36 2015 -0800 google/chell: Turn on keyboard backlight in romstage Use the keyboard backlight to provide indication that the system is booting. This is useful for determining that a system is in S0 and is running BIOS code. BUG=chrome-os-partner:47435 BRANCH=none TEST=boot on chell and see keyboard backlight come on early Change-Id: I43e699bcc2f34998d3d6ce33ce72c7b04b55c146 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a3a0147b6de681365a9c995175076d5f397016fb Original-Change-Id: I2441c28431e71b13b70e6533e175d29ccfd8d7e9 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312358 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/chell/romstage.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/chell/romstage.c b/src/mainboard/google/chell/romstage.c index 6aac80f..ecaae3a 100644 --- a/src/mainboard/google/chell/romstage.c +++ b/src/mainboard/google/chell/romstage.c @@ -39,6 +39,10 @@ void mainboard_romstage_entry(struct romstage_params *params) /* Ensure the EC and PD are in the right mode for recovery */ google_chromeec_early_init(); + /* Turn on keyboard backlight to indicate we are booting */ + if (params->power_state->prev_sleep_state != SLEEP_STATE_S3) + google_chromeec_kbbacklight(100); + early_config_gpio(); /* Fill out PEI DATA */

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New patch to review for coreboot: google/chell: Set USB current limit to 2A
by Patrick Georgi 16 Nov '15

16 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12447 -gerrit commit 9843d9ebe83e09400a097963a2707847941b8e0c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Nov 12 08:33:37 2015 -0800 google/chell: Set USB current limit to 2A The GPIO for USBA_1_ILIM_SEL_L should be low to enable 2A charging from the Type-A port. BUG=chrome-os-partner:47172 BRANCH=none TEST=emerge-glados coreboot Change-Id: I1bbcdd467684e7c1372c8ca862d498fb6cbb966c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c8a8fbed6d0fd7aea0a41db2bde104fe7a05cabe Original-Change-Id: I3b18cbb204cfa19e50f34ea9533018e286342513 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312451 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/chell/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h index 20880cd..a347454 100644 --- a/src/mainboard/google/chell/gpio.h +++ b/src/mainboard/google/chell/gpio.h @@ -141,7 +141,7 @@ static const struct pad_config gpio_table[] = { /* ISH_I2C1_SDA */ /* GPP_D7 */ /* ISH_I2C1_SCL */ /* GPP_D8 */ /* ISH_SPI_CS# */ /* GPP_D9 */ -/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* USBA_1_ILIM_SEL_L */ +/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USBA_1_ILIM_SEL_L */ /* ISH_SPI_MISO */ /* GPP_D11 */ /* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ /* ISH_UART0_RXD */ /* GPP_D13 */

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New patch to review for coreboot: google/chell: disable power rails in sleep path
by Patrick Georgi 16 Nov '15

16 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12446 -gerrit commit c1a3aa6bb5f38b6cf662b8147f28124c688003fc Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Nov 11 16:50:52 2015 -0600 google/chell: disable power rails in sleep path For the rails controllable by the host processor through gpios turn them off in the sleep paths. The result is that S3 and S5 will turn off those rails. BUG=chrome-os-partner:47228 BRANCH=None TEST=Built for chell. Change-Id: I5843f13be43a6ec143600585a5a0c47563e533dd Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ddd5860dc0cfee68ec2f77f4931665740bede08c Original-Change-Id: Ife0e2fb11373dd129e20b914b45cd5b56c3493f7 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312321 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/chell/gpio.h | 7 +++++++ src/mainboard/google/chell/smihandler.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 34 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h index cb10be4..20880cd 100644 --- a/src/mainboard/google/chell/gpio.h +++ b/src/mainboard/google/chell/gpio.h @@ -49,6 +49,13 @@ #define EC_SCI_GPI GPE0_DW2_16 #define EC_SMI_GPI GPP_E15 +/* Power rail control signals. */ +#define EN_PP3300_KEPLER GPP_C11 +#define EN_PP3300_DX_TOUCH GPP_C22 +#define EN_PP3300_DX_EMMC GPP_D5 +#define EN_PP1800_DX_EMMC GPP_D6 +#define EN_PP3300_DX_CAM GPP_D12 + #ifndef __ACPI__ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { diff --git a/src/mainboard/google/chell/smihandler.c b/src/mainboard/google/chell/smihandler.c index 7e34712..cd0cc19 100644 --- a/src/mainboard/google/chell/smihandler.c +++ b/src/mainboard/google/chell/smihandler.c @@ -19,6 +19,7 @@ #include <cpu/x86/smm.h> #include <elog.h> #include <ec/google/chromeec/ec.h> +#include <gpio.h> #include <soc/iomap.h> #include <soc/nvs.h> #include <soc/pm.h> @@ -80,9 +81,8 @@ void mainboard_smi_gpi_handler(const struct gpi_status *sts) } } -void mainboard_smi_sleep(u8 slp_typ) +static void google_ec_smi_sleep(u8 slp_typ) { -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) switch (slp_typ) { case 3: /* Enable wake events */ @@ -101,7 +101,31 @@ void mainboard_smi_sleep(u8 slp_typ) /* Clear pending events that may trigger immediate wake */ while (google_chromeec_get_event() != 0) ; -#endif +} + +static void mainboard_gpio_smi_sleep(u8 slp_typ) +{ + int i; + + /* Power down the rails on any sleep type. */ + gpio_t active_high_signals[] = { + EN_PP3300_KEPLER, + EN_PP3300_DX_TOUCH, + EN_PP3300_DX_EMMC, + EN_PP1800_DX_EMMC, + EN_PP3300_DX_CAM, + }; + + for (i = 0; i < ARRAY_SIZE(active_high_signals); i++) + gpio_set(active_high_signals[i], 0); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + google_ec_smi_sleep(slp_typ); + + mainboard_gpio_smi_sleep(slp_typ); } int mainboard_smi_apmc(u8 apmc)

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New patch to review for coreboot: google/glados: disable power rails in sleep path
by Patrick Georgi 16 Nov '15

16 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12445 -gerrit commit 5d891c778c9463e0c9356c2e386e1c41b2dd4be4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Nov 11 16:46:27 2015 -0600 google/glados: disable power rails in sleep path For the rails controllable by the host processor through gpios turn them off in the sleep paths. The result is that S3 and S5 will turn off those rails. BUG=chrome-os-partner:47228 BRANCH=None TEST=Built and booted glados. Suspended and resumed. Change-Id: I6d45683b64ca5f7c3c47e11f95951bd2d9abf31e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ed432e2b5535da6f872a53b76886d983f00b4e8e Original-Change-Id: I94d7e0b00bf7e7da8dc59f299e41b72e8fcb64f4 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312320 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/glados/gpio.h | 7 +++++++ src/mainboard/google/glados/smihandler.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 34 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h index 14f49eb..d42b711 100644 --- a/src/mainboard/google/glados/gpio.h +++ b/src/mainboard/google/glados/gpio.h @@ -46,6 +46,13 @@ #define EC_SCI_GPI GPE0_DW2_16 #define EC_SMI_GPI GPP_E15 +/* Power rail control signals. */ +#define EN_PP3300_KEPLER GPP_C11 +#define EN_PP3300_DX_TOUCH GPP_C22 +#define EN_PP3300_DX_EMMC GPP_D5 +#define EN_PP1800_DX_EMMC GPP_D6 +#define EN_PP3300_DX_CAM GPP_D12 + #ifndef __ACPI__ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c index 7e34712..cd0cc19 100644 --- a/src/mainboard/google/glados/smihandler.c +++ b/src/mainboard/google/glados/smihandler.c @@ -19,6 +19,7 @@ #include <cpu/x86/smm.h> #include <elog.h> #include <ec/google/chromeec/ec.h> +#include <gpio.h> #include <soc/iomap.h> #include <soc/nvs.h> #include <soc/pm.h> @@ -80,9 +81,8 @@ void mainboard_smi_gpi_handler(const struct gpi_status *sts) } } -void mainboard_smi_sleep(u8 slp_typ) +static void google_ec_smi_sleep(u8 slp_typ) { -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) switch (slp_typ) { case 3: /* Enable wake events */ @@ -101,7 +101,31 @@ void mainboard_smi_sleep(u8 slp_typ) /* Clear pending events that may trigger immediate wake */ while (google_chromeec_get_event() != 0) ; -#endif +} + +static void mainboard_gpio_smi_sleep(u8 slp_typ) +{ + int i; + + /* Power down the rails on any sleep type. */ + gpio_t active_high_signals[] = { + EN_PP3300_KEPLER, + EN_PP3300_DX_TOUCH, + EN_PP3300_DX_EMMC, + EN_PP1800_DX_EMMC, + EN_PP3300_DX_CAM, + }; + + for (i = 0; i < ARRAY_SIZE(active_high_signals); i++) + gpio_set(active_high_signals[i], 0); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + google_ec_smi_sleep(slp_typ); + + mainboard_gpio_smi_sleep(slp_typ); } int mainboard_smi_apmc(u8 apmc)

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New patch to review for coreboot: edid: Don't half parse (and wrongly print) more detailed timings
by Patrick Georgi 16 Nov '15

16 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12444 -gerrit commit 91e35c9e0c1766a80b0bfdd601a5c2122b99e095 Author: Douglas Anderson <dianders(a)chromium.org> Date: Wed Oct 28 09:18:28 2015 -0700 edid: Don't half parse (and wrongly print) more detailed timings The EDID parsing code continued to update _some_ fields of the output edid but not others if "did_detailed_timing" was already set. It also then went on to print out this halfway mix of modes each time, despite the fact that it didn't really update everything. Let's fix that. We'll reduce code changes by using a temporary copy of data in detailed_block() and then we'll copy it back if we decide we should update. BRANCH=none BUG=chrome-os-partner:46998 TEST=No more bogus printouts Change-Id: Idbfa233e0997244c22ef21c892c4473a91621821 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4d69999cdd7ce3cd2c9332ab3f22ea8eb4b6f2e9 Original-Change-Id: Ia72cac7fda2772f26477e43237678fa30feca584 Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309541 Original-Reviewed-on: https://chromium-review.googlesource.com/309609 Original-Commit-Ready: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/lib/edid.c | 125 +++++++++++++++++++++++++++++++-------------------------- 1 file changed, 67 insertions(+), 58 deletions(-) diff --git a/src/lib/edid.c b/src/lib/edid.c index 8c8ab6f..3aebc65 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -91,6 +91,8 @@ static struct { const char *stereo; } extra_info; +static struct edid tmp_edid; + static int vbe_valid; static struct lb_framebuffer edid_fb; @@ -197,9 +199,10 @@ extract_string(unsigned char *x, int *valid_termination, int len) /* 1 means valid data */ static int -detailed_block(struct edid *out, unsigned char *x, int in_extension, +detailed_block(struct edid *result_edid, unsigned char *x, int in_extension, struct edid_context *c) { + struct edid *out = &tmp_edid; int i; #if 1 printk(BIOS_SPEW, "Hex of detail: "); @@ -208,6 +211,9 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension, printk(BIOS_SPEW, "\n"); #endif + /* Result might already have some valid fields like mode_is_supported */ + *out = *result_edid; + if (x[0] == 0 && x[1] == 0) { /* Monitor descriptor block, not detailed timing descriptor. */ if (x[2] != 0) { @@ -443,63 +449,59 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension, c->has_valid_descriptor_ordering = 0; } - if (! c->did_detailed_timing){ - /* Edid contains pixel clock in terms of 10KHz */ - out->mode.pixel_clock = (x[0] + (x[1] << 8)) * 10; - /* - LVDS supports following pixel clocks - 25000...112000 kHz: single channel - 80000...224000 kHz: dual channel - There is some overlap in theoretically supported - pixel clock between single-channel and dual-channel. - In practice with current panels all panels - <= 75200 kHz: single channel - >= 97750 kHz: dual channel - We have no samples between those values, so put a - threshold at 95000 kHz. If we get anything over - 95000 kHz with single channel, we can make this - more sofisticated but it's currently not needed. - */ - out->mode.lvds_dual_channel = (out->mode.pixel_clock >= 95000); - extra_info.x_mm = (x[12] + ((x[14] & 0xF0) << 4)); - extra_info.y_mm = (x[13] + ((x[14] & 0x0F) << 8)); - out->mode.ha = (x[2] + ((x[4] & 0xF0) << 4)); - out->mode.hbl = (x[3] + ((x[4] & 0x0F) << 8)); - out->mode.hso = (x[8] + ((x[11] & 0xC0) << 2)); - out->mode.hspw = (x[9] + ((x[11] & 0x30) << 4)); - out->mode.hborder = x[15]; - out->mode.va = (x[5] + ((x[7] & 0xF0) << 4)); - out->mode.vbl = (x[6] + ((x[7] & 0x0F) << 8)); - out->mode.vso = ((x[10] >> 4) + ((x[11] & 0x0C) << 2)); - out->mode.vspw = ((x[10] & 0x0F) + ((x[11] & 0x03) << 4)); - out->mode.vborder = x[16]; - /* set up some reasonable defaults for payloads. - * We observe that most modern chipsets we work with - * tend to support rgb888 without regard to the - * panel bits per color or other settings. The rgb888 - * is a convenient layout for software because - * it avoids the messy bit stuffing of rgb565 or rgb444. - * It makes a reasonable trade of memory for speed. - * So, set up the default for - * 32 bits per pixel - * rgb888 (i.e. no alpha, but pixels on 32-bit boundaries) - * The mainboard can modify these if needed, though - * we have yet to see a case where that will happen. - * The existing ARM mainboards don't even call this function - * so this will not affect them. - */ - out->framebuffer_bits_per_pixel = 32; - - out->x_resolution = ALIGN(out->mode.ha * - ((out->framebuffer_bits_per_pixel + 7) / 8), - 64) / (out->framebuffer_bits_per_pixel/8); - out->y_resolution = out->mode.va; - out->bytes_per_line = ALIGN(out->mode.ha * - ((out->framebuffer_bits_per_pixel + 7)/8), - 64); - printk(BIOS_SPEW, "Did detailed timing\n"); - } - c->did_detailed_timing = 1; + /* Edid contains pixel clock in terms of 10KHz */ + out->mode.pixel_clock = (x[0] + (x[1] << 8)) * 10; + /* + LVDS supports following pixel clocks + 25000...112000 kHz: single channel + 80000...224000 kHz: dual channel + There is some overlap in theoretically supported + pixel clock between single-channel and dual-channel. + In practice with current panels all panels + <= 75200 kHz: single channel + >= 97750 kHz: dual channel + We have no samples between those values, so put a + threshold at 95000 kHz. If we get anything over + 95000 kHz with single channel, we can make this + more sofisticated but it's currently not needed. + */ + out->mode.lvds_dual_channel = (out->mode.pixel_clock >= 95000); + extra_info.x_mm = (x[12] + ((x[14] & 0xF0) << 4)); + extra_info.y_mm = (x[13] + ((x[14] & 0x0F) << 8)); + out->mode.ha = (x[2] + ((x[4] & 0xF0) << 4)); + out->mode.hbl = (x[3] + ((x[4] & 0x0F) << 8)); + out->mode.hso = (x[8] + ((x[11] & 0xC0) << 2)); + out->mode.hspw = (x[9] + ((x[11] & 0x30) << 4)); + out->mode.hborder = x[15]; + out->mode.va = (x[5] + ((x[7] & 0xF0) << 4)); + out->mode.vbl = (x[6] + ((x[7] & 0x0F) << 8)); + out->mode.vso = ((x[10] >> 4) + ((x[11] & 0x0C) << 2)); + out->mode.vspw = ((x[10] & 0x0F) + ((x[11] & 0x03) << 4)); + out->mode.vborder = x[16]; + /* set up some reasonable defaults for payloads. + * We observe that most modern chipsets we work with + * tend to support rgb888 without regard to the + * panel bits per color or other settings. The rgb888 + * is a convenient layout for software because + * it avoids the messy bit stuffing of rgb565 or rgb444. + * It makes a reasonable trade of memory for speed. + * So, set up the default for + * 32 bits per pixel + * rgb888 (i.e. no alpha, but pixels on 32-bit boundaries) + * The mainboard can modify these if needed, though + * we have yet to see a case where that will happen. + * The existing ARM mainboards don't even call this function + * so this will not affect them. + */ + out->framebuffer_bits_per_pixel = 32; + + out->x_resolution = ALIGN(out->mode.ha * + ((out->framebuffer_bits_per_pixel + 7) / 8), + 64) / (out->framebuffer_bits_per_pixel/8); + out->y_resolution = out->mode.va; + out->bytes_per_line = ALIGN(out->mode.ha * + ((out->framebuffer_bits_per_pixel + 7)/8), + 64); switch ((x[17] & 0x18) >> 3) { case 0x00: extra_info.syncmethod = " analog composite"; @@ -556,6 +558,13 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension, out->mode.phsync, out->mode.pvsync, extra_info.syncmethod, x[17] & 0x80 ?" interlaced" : "", extra_info.stereo); + + if (! c->did_detailed_timing) { + printk(BIOS_SPEW, "Did detailed timing\n"); + c->did_detailed_timing = 1; + *result_edid = *out; + } + return 1; }

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New patch to review for coreboot: edid: Use a better mode for 640x480
by Patrick Georgi 16 Nov '15

16 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12443 -gerrit commit 95d48085721d8458e186bf9a446d5eea69163a6a Author: Douglas Anderson <dianders(a)chromium.org> Date: Wed Oct 28 09:52:22 2015 -0700 edid: Use a better mode for 640x480 The hardcoded clock value for 640x480 was 25.175 MHz. That's a valid clock to use, but is quite hard to make a non-jittery clock from PLLs. It's much easier to make 25.200 MHz, so let's do that. The difference between the two modes is 59.9 Hz vs. 60 Hz and it seems better to make a non-jittery 60 Hz rather than a very jittery 59.9 Hz. BRANCH=none BUG=chrome-os-partner:46256 TEST=Insignia monitor works, so do others Change-Id: I8aa124d04a90f5dcf9cfa923ed3b693fbb4a06d8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e32ce13462101dc60cfed60b6948b7597e93525a Original-Change-Id: Ia9804afe8011a915e4bec306e863d34ad7e27be5 Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309540 Original-Reviewed-by: Stphane Marchesin <marcheu(a)chromium.org> Original-(cherry picked from commit 7f32c9f460991e5e3b947117d6ae4080e630a532) Original-Reviewed-on: https://chromium-review.googlesource.com/309576 Original-Commit-Ready: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/lib/edid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/edid.c b/src/lib/edid.c index 6663d1c..8c8ab6f 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -1003,7 +1003,7 @@ static void dump_breakdown(unsigned char *edid) */ static struct edid_mode known_modes[NUM_KNOWN_MODES] = { [EDID_MODE_640x480_60Hz] = { - .name = "640x480@60Hz", .pixel_clock = 25175, .refresh = 60, + .name = "640x480@60Hz", .pixel_clock = 25200, .refresh = 60, .ha = 640, .hbl = 160, .hso = 16, .hspw = 96, .va = 480, .vbl = 45, .vso = 10, .vspw = 2, .phsync = '-', .pvsync = '-' },

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New patch to review for coreboot: edid: Don't set standard timings as supported if they're not
by Patrick Georgi 16 Nov '15

16 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12442 -gerrit commit 6671cb682a537eba6919b86e4716ba67d6c871a1 Author: Douglas Anderson <dianders(a)chromium.org> Date: Wed Oct 28 10:19:52 2015 -0700 edid: Don't set standard timings as supported if they're not The set to say that a standard timing was supported was not properly in the "if" test. That meant that even when standard timings weren't supported, we thought that they were. That had the side effect of never using the detailed mode. BRANCH=none BUG=chrome-os-partner:46998 TEST=Adafruit panel works now Change-Id: Ide3ed6c5682840f808d854755dac58e9057e6bda Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c99d3ee8d163fc6be207c5a7df2a7aecd7af7849 Original-Change-Id: Ib67735219fd28516857d9b63f1ba156573f1bea3 Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309521 Original-(cherry picked from commit 4e4c2816e2239299bc02e3a57fb18056db62b56c) Original-Reviewed-on: https://chromium-review.googlesource.com/309552 Original-Commit-Ready: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/lib/edid.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/lib/edid.c b/src/lib/edid.c index e94720e..6663d1c 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -1272,13 +1272,13 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) if (edid[0x23 + i / 8] & (1 << (7 - i % 8))) { printk(BIOS_SPEW, " %dx%d@%dHz\n", established_timings[i].x, established_timings[i].y, established_timings[i].refresh); - } - for (j = 0; j < NUM_KNOWN_MODES; j++) { - if (known_modes[j].ha == established_timings[i].x && - known_modes[j].va == established_timings[i].y && - known_modes[j].refresh == established_timings[i].refresh) + for (j = 0; j < NUM_KNOWN_MODES; j++) { + if (known_modes[j].ha == established_timings[i].x && + known_modes[j].va == established_timings[i].y && + known_modes[j].refresh == established_timings[i].refresh) out->mode_is_supported[j] = 1; + } } }

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New patch to review for coreboot: edid: Remove useless parameter from detailed_cvt_descriptor()
by Patrick Georgi 16 Nov '15

16 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12441 -gerrit commit 2f2cde9863626fa46f50a2b1de5d01170721eb45 Author: Douglas Anderson <dianders(a)chromium.org> Date: Wed Oct 28 11:19:57 2015 -0700 edid: Remove useless parameter from detailed_cvt_descriptor() The detailed_cvt_descriptor() function takes a parameter "out" for no good reason. Remove it. BRANCH=none BUG=chrome-os-partner:46998 TEST=Build and boot Change-Id: I1042dba9ddf2b4b543bd07615013088be5055950 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5c3474c9b1f9fb73f44d64d3a0592f92339da2df Original-Change-Id: I4d695a6dba6606d2132578ce0ab4cb612c83d0f4 Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309598 Original-(cherry picked from commit 39122e242e808d71a4e274e8a23e9a63f4984388) Original-Reviewed-on: https://chromium-review.googlesource.com/309496 Original-Commit-Ready: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/lib/edid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/lib/edid.c b/src/lib/edid.c index 0f5643d..e94720e 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -110,7 +110,7 @@ static char *manufacturer_name(unsigned char *x) } static int -detailed_cvt_descriptor(struct edid *out, unsigned char *x, int first) +detailed_cvt_descriptor(unsigned char *x, int first) { const unsigned char empty[3] = { 0, 0, 0 }; const char *names[] = { "50", "60", "75", "85" }; @@ -253,7 +253,7 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension, return 0; } for (i = 0; i < 4; i++) - valid_cvt &= detailed_cvt_descriptor(out, x + 6 + (i * 3), (i == 0)); + valid_cvt &= detailed_cvt_descriptor(x + 6 + (i * 3), (i == 0)); c->has_valid_cvt &= valid_cvt; return 1; }

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Patch merged into coreboot/master: amd/model_fxx: Check FID&VID Support for the BSP (too)
by gerrit＠coreboot.org 15 Nov '15

15 Nov '15

the following patch was just integrated into master: commit 3ca41166d7d8fa36b58735ce5e36354279795f78 Author: Urja Rannikko <urjaman(a)gmail.com> Date: Sat Nov 7 15:43:06 2015 +0200 amd/model_fxx: Check FID&VID Support for the BSP (too) Tested: Avoids crash with Sempron 2800+ on K8V-X. Change-Id: I76196176635bb0f6ac284c8cb3b72212774fdfe4 Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> Reviewed-on: http://review.coreboot.org/12336 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> See http://review.coreboot.org/12336 for details. -gerrit

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coreboot-gerrit November 2015