coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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1236 discussions

New patch to review for coreboot: 39c8246 amd/amdfam10: Fix AP crash during microcode version lookup
by Timothy Pearson 31 Jan '15

31 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8310 -gerrit commit 39c8246d2475b4997339c188aaab4305335c29dd Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 30 23:47:45 2015 -0600 amd/amdfam10: Fix AP crash during microcode version lookup This resolves a failure to initialize APs on Istanbul devices Change-Id: I9e2554b50ad60a8d02ef4bd3fbee6fddb238d83f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/update_microcode.c | 49 +++++++++++------------------- 1 file changed, 18 insertions(+), 31 deletions(-) diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c index 95624e9..6a919b2 100644 --- a/src/cpu/amd/model_10xxx/update_microcode.c +++ b/src/cpu/amd/model_10xxx/update_microcode.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -56,38 +57,24 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = { 0x0, 0x0, 0x0, 0x0, }; -static u32 get_equivalent_processor_rev_id(u32 orig_id) { - static unsigned id_mapping_table[] = { - 0x100f00, 0x1000, - 0x100f01, 0x1000, - 0x100f02, 0x1000, - 0x100f20, 0x1020, - 0x100f21, 0x1020, - 0x100f2A, 0x1020, - 0x100f22, 0x1022, - 0x100f23, 0x1022, - 0x100f42, 0x1041, - 0x100f43, 0x1043, - 0x100f62, 0x1062, - 0x100f63, 0x1043, - 0x100f81, 0x1081, - 0x100fa0, 0x10A0, - }; - - u32 new_id; - int i; - - new_id = 0; - - for (i = 0; i < sizeof(id_mapping_table); i += 2 ) { - if(id_mapping_table[i]==orig_id) { - new_id = id_mapping_table[i + 1]; - break; - } - } - - return new_id; +u32 get_equivalent_processor_rev_id(u32 orig_id); +u32 get_equivalent_processor_rev_id(u32 orig_id) { + if (orig_id == 0x100f00) return 0x1000; + else if (orig_id == 0x100f01) return 0x1000; + else if (orig_id == 0x100f02) return 0x1000; + else if (orig_id == 0x100f20) return 0x1020; + else if (orig_id == 0x100f21) return 0x1020; + else if (orig_id == 0x100f2A) return 0x1020; + else if (orig_id == 0x100f22) return 0x1022; + else if (orig_id == 0x100f23) return 0x1022; + else if (orig_id == 0x100f42) return 0x1041; + else if (orig_id == 0x100f43) return 0x1043; + else if (orig_id == 0x100f62) return 0x1062; + else if (orig_id == 0x100f63) return 0x1043; + else if (orig_id == 0x100f81) return 0x1081; + else if (orig_id == 0x100fa0) return 0x10A0; + return 0; } void update_microcode(u32 cpu_deviceid)

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New patch to review for coreboot: 1f1c483 amd/amdfam10: Update name table with Opteron 2400/8400 series codes
by Timothy Pearson 31 Jan '15

31 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8309 -gerrit commit 1f1c48304956f583a301f516a4135063fa94b965 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 30 23:47:12 2015 -0600 amd/amdfam10: Update name table with Opteron 2400/8400 series codes Change-Id: I52587c0c0dffd814d39087475b8f14c500a68933 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/processor_name.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/cpu/amd/model_10xxx/processor_name.c b/src/cpu/amd/model_10xxx/processor_name.c index 40b73b0..11f4f8b 100644 --- a/src/cpu/amd/model_10xxx/processor_name.c +++ b/src/cpu/amd/model_10xxx/processor_name.c @@ -4,6 +4,7 @@ * Copyright (C) 2007 Advanced Micro Devices, Inc. * Copyright (C) 2008 Peter Stuge * Copyright (C) 2010 Marc Jones <marcj303(a)gmail.com> + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -51,6 +52,8 @@ static const struct str_s String1_socket_F[] = { {0x00, 0x01, 0x01, "Dual-Core AMD Opteron(tm) Processor 23"}, {0x00, 0x03, 0x00, "Quad-Core AMD Opteron(tm) Processor 83"}, {0x00, 0x03, 0x01, "Quad-Core AMD Opteron(tm) Processor 23"}, + {0x00, 0x05, 0x00, "Six-Core AMD Opteron(tm) Processor 84"}, + {0x00, 0x05, 0x01, "Six-Core AMD Opteron(tm) Processor 24"}, {0x00, 0x03, 0x02, "Embedded AMD Opteron(tm) Processor 83"}, {0x00, 0x03, 0x03, "Embedded AMD Opteron(tm) Processor 23"}, {0x00, 0x03, 0x04, "Embedded AMD Opteron(tm) Processor 13"}, @@ -60,6 +63,7 @@ static const struct str_s String1_socket_F[] = { }; static const struct str_s String2_socket_F[] = { + {0x00, 0xFF, 0x02, " EE"}, {0x00, 0xFF, 0x0A, " SE"}, {0x00, 0xFF, 0x0B, " HE"}, {0x00, 0xFF, 0x0C, " EE"},

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New patch to review for coreboot: 8b16a9d fsp_baytrail: Get FSP reserved memory from the FSP HOB list
by Martin Roth 31 Jan '15

31 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8308 -gerrit commit 8b16a9d9c0e6b32de6c685329e64c0a1247de194 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jan 30 20:56:05 2015 -0700 fsp_baytrail: Get FSP reserved memory from the FSP HOB list Because the pointer to the FSP HOB list is now being saved, we can use that to find the top of usable memory. This eliminates the need to hardcode the size of the FSP reserved memory area. Tested on minnowboard max for baytrail. The HOB structure used does not seem to be present for the rangeley or ivybridge/pantherpoint FSPs. At the very least, the GUID is not documented in the integration guides. Change-Id: I643e57655f55bfada60075b55aad2ce010ec4f67 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/drivers/intel/fsp/fsp_util.c | 19 +++++++++++++++++++ src/drivers/intel/fsp/fsp_util.h | 9 +++++++-- src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h | 2 -- src/soc/intel/fsp_baytrail/memmap.c | 15 +++++++-------- src/soc/intel/fsp_baytrail/northcluster.c | 7 +------ 5 files changed, 34 insertions(+), 18 deletions(-) diff --git a/src/drivers/intel/fsp/fsp_util.c b/src/drivers/intel/fsp/fsp_util.c index 0844b37..b59330f 100644 --- a/src/drivers/intel/fsp/fsp_util.c +++ b/src/drivers/intel/fsp/fsp_util.c @@ -195,6 +195,25 @@ void * find_saved_temp_mem(void *hob_list_ptr) return (void *) ((char *) saved_mem_hob + sizeof(EFI_HOB_GUID_TYPE)); } +/** @brief locates the HOB containing the location of the fsp reserved mem area + * + * @param hob_list_ptr pointer to the start of the hob list + * @return pointer to the start of the FSP reserved memory or NULL if not found. + */ +void * find_fsp_reserved_mem(void *hob_list_ptr) +{ + EFI_GUID fsp_reserved_guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; + EFI_HOB_RESOURCE_DESCRIPTOR *fsp_reserved_mem = + (EFI_HOB_RESOURCE_DESCRIPTOR *) find_hob_by_guid( + hob_list_ptr, &fsp_reserved_guid); + + if (fsp_reserved_mem == NULL) + return NULL; + + return (void *)((uintptr_t)fsp_reserved_mem->PhysicalStart); +} + + #ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */ void print_fsp_info(void) { diff --git a/src/drivers/intel/fsp/fsp_util.h b/src/drivers/intel/fsp/fsp_util.h index a39f5a2..8b86ee9 100644 --- a/src/drivers/intel/fsp/fsp_util.h +++ b/src/drivers/intel/fsp/fsp_util.h @@ -20,6 +20,9 @@ #ifndef FSP_UTIL_H #define FSP_UTIL_H +#define SIG_32_BIT(a,b,c,d) ((a<<0)|(b<<8)|(c<<16)|(d<<24)) +#define SIG_64_BIT(a,b,c,d,e,f,g,h) ((u64)SIG_32_BIT(a,b,c,d) | (u64)SIG_32_BIT(e,f,g,h)<<32) + #include <chipset_fsp_util.h> #include "fsp_values.h" @@ -38,6 +41,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, FSP_INFO_HEADER *fsp_ptr); void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr); void * find_saved_temp_mem(void *hob_list_ptr); +void * find_fsp_reserved_mem(void *hob_list_ptr); /* functions in hob.c */ void print_hob_mem_attributes(void *Hobptr); @@ -66,7 +70,7 @@ void printguid(EFI_GUID *guid); #if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) #define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) +#define MRC_DATA_SIGNATURE SIG_32_BIT('M','R','C','D') struct mrc_data_container { u32 mrc_signature; // "MRCD" @@ -89,7 +93,8 @@ void update_mrc_cache(void *unused); #define FSP_IMAGE_ID_LOC 16 #define FSP_IMAGE_BASE_LOC 28 -#define FSP_SIG 0x48505346 /* 'FSPH' */ +#define FSP_SIG SIG_32_BIT('F','S','P','H') +#define FIRMWARE_VOLUME_SIGNATURE SIG_32_BIT('_','F','V','H') #define ERROR_NO_FV_SIG 1 #define ERROR_NO_FFS_GUID 2 diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h index 1f4fa74..29309bf 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h @@ -32,8 +32,6 @@ #include <fspvpd.h> #include <azalia.h> -#define FSP_RESERVE_MEMORY_SIZE 0x200000 - #define FSP_INFO_HEADER_GUID \ { \ 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c index 615916b..8a10ac8 100644 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ b/src/soc/intel/fsp_baytrail/memmap.c @@ -29,18 +29,17 @@ uintptr_t smm_region_start(void) return (iosf_bunit_read(BUNIT_SMRRL) << 20); } -/* - * Calculate the top of usable (low) DRAM. - * The FSP's reserved memory sits just below the SMM region, - * allowing calculation of the top of usable memory. +/** @brief get the top of usable low memory from the FSP's HOB list + * + * The FSP's reserved memory sits just below the SMM region. The memory + * region below it is usable memory. * * The entire memory map is shown in northcluster.c + * + * @return pointer to the first byte of reserved memory */ void *cbmem_top(void) { - uintptr_t tom = smm_region_start(); - if (!tom) - tom = iosf_bunit_read(BUNIT_BMBOUND); - return (void *) tom - FSP_RESERVE_MEMORY_SIZE; + return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 838e554..b288388 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -149,8 +149,7 @@ static void mc_add_dram_resources(device_t dev) uint32_t fsp_mem_base = 0; GetHighMemorySize(&highmem_size); - GetLowMemorySize(&fsp_mem_base); - + fsp_mem_base=(uint32_t)cbmem_top(); bmbound = iosf_bunit_read(BUNIT_BMBOUND); bsmmrrl = iosf_bunit_read(BUNIT_SMRRL) << 20; @@ -162,10 +161,6 @@ static void mc_add_dram_resources(device_t dev) printk(BIOS_DEBUG, "FSP memory location: 0x%x\nFSP memory size: %dM\n", fsp_mem_base, (bsmmrrl - fsp_mem_base) >> 20); - - if ((bsmmrrl - fsp_mem_base ) != FSP_RESERVE_MEMORY_SIZE) - printk(BIOS_WARNING, "Warning: Fsp memory size does not match " - "expected memory size (%x).\n", FSP_RESERVE_MEMORY_SIZE); } printk(BIOS_INFO, "Available memory below 4GB: 0x%08x (%dM)\n",

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Patch set updated for coreboot: e6414e3 intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP
by York Yang 31 Jan '15

31 Jan '15

York Yang (york.yang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8107 -gerrit commit e6414e3f08f0419b42e134117f16d7dbfb18b803 Author: York Yang <york.yang(a)intel.com> Date: Mon Jan 5 10:04:45 2015 -0700 intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration by UPD input. Update UPD_DATA_REGION structure for matching up this FSP change. PcdCustomerRevision is a debugging aid that will be output to debug message in FSP. When needed, it can be customized by BCT tool for tracking BCT configurations. Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b Signed-off-by: York Yang <york.yang(a)intel.com> --- src/northbridge/intel/fsp_rangeley/chip.h | 10 ++++++++++ src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c | 7 +++++++ src/vendorcode/intel/fsp/rangeley/include/fspvpd.h | 15 ++++++++++----- 3 files changed, 27 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h index 80a22bf..d3828c7 100644 --- a/src/northbridge/intel/fsp_rangeley/chip.h +++ b/src/northbridge/intel/fsp_rangeley/chip.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -57,6 +58,15 @@ struct northbridge_intel_fsp_rangeley_config { #define BIFURCATION_8_8 3 #define BIFURCATION_16 4 uint8_t Bifurcation; + + /* PCIe port de-emphasis control */ + #define DE_EMPHASIS_DEFAULT 0 + #define DE_EMPHASIS_MINUS_6_0_DB 1 + #define DE_EMPHASIS_MINUS_3_5_DB 2 + uint8_t PcdPcieRootPort1DeEmphasis; + uint8_t PcdPcieRootPort2DeEmphasis; + uint8_t PcdPcieRootPort3DeEmphasis; + uint8_t PcdPcieRootPort4DeEmphasis; }; #endif diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index ae95087..3f8690a 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -143,6 +144,12 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) break; } } + + /* Set PCIe de-emphasis */ + UPD_DEFAULT_CHECK(PcdPcieRootPort1DeEmphasis); + UPD_DEFAULT_CHECK(PcdPcieRootPort2DeEmphasis); + UPD_DEFAULT_CHECK(PcdPcieRootPort3DeEmphasis); + UPD_DEFAULT_CHECK(PcdPcieRootPort4DeEmphasis); } /* Set up the Rangeley specific structures for the call into the FSP */ diff --git a/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h b/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h index 12ac2be..fba38a0 100644 --- a/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h +++ b/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (C) 2013, Intel Corporation +Copyright (C) 2013-2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -57,16 +57,21 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdEnableIQAT; /* Offset 0x0033 */ UINT8 PcdEnableUsb20; /* Offset 0x0034 */ UINT8 PcdBifurcation; /* Offset 0x0035 */ - UINT8 UnusedUpdSpace2[10]; /* Offset 0x0036 */ + UINT8 PcdPcieRootPort1DeEmphasis; /* Offset 0x0036 */ + UINT8 PcdPcieRootPort2DeEmphasis; /* Offset 0x0037 */ + UINT8 PcdPcieRootPort3DeEmphasis; /* Offset 0x0038 */ + UINT8 PcdPcieRootPort4DeEmphasis; /* Offset 0x0039 */ + UINT8 UnusedUpdSpace2[6]; /* Offset 0x003A */ UINT8 PcdPrintDebugMessages; /* Offset 0x0040 */ UINT8 PcdFastboot; /* Offset 0x0041 */ UINT8 PcdEccSupport; /* Offset 0x0042 */ - UINT8 UnusedUpdSpace3[13]; /* Offset 0x0043 */ - UINT16 PcdRegionTerminator; /* Offset 0x0050 */ + UINT8 PcdCustomerRevision[32]; /* Offset 0x0043 */ + UINT8 UnusedUpdSpace3[13]; /* Offset 0x0063 */ + UINT16 PcdRegionTerminator; /* Offset 0x0070 */ } UPD_DATA_REGION; #define VPD_IMAGE_ID 0x562D474E524E5641 /* 'AVNRNG-V' */ -#define VPD_IMAGE_REV 0x00000101 +#define VPD_IMAGE_REV 0x00000102 typedef struct _VPD_DATA_REGION { UINT64 PcdVpdRegionSign; /* Offset 0x0000 */

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Patch set updated for coreboot: d6ff2a3 intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP
by York Yang 30 Jan '15

30 Jan '15

York Yang (york.yang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8107 -gerrit commit d6ff2a3c3132a12859917109d51615702f084c9b Author: York Yang <york.yang(a)intel.com> Date: Mon Jan 5 10:04:45 2015 -0700 intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration by UPD input. Update UPD_DATA_REGION structure for matching up this FSP change. PcdCustomerRevision is a debugging aid that will be output to debug message in FSP. When need, it can be customized by BCT tool for tracking BCT configurations. Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b Signed-off-by: York Yang <york.yang(a)intel.com> --- src/northbridge/intel/fsp_rangeley/chip.h | 10 ++++++++++ src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c | 7 +++++++ src/vendorcode/intel/fsp/rangeley/include/fspvpd.h | 15 ++++++++++----- 3 files changed, 27 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h index 80a22bf..d3828c7 100644 --- a/src/northbridge/intel/fsp_rangeley/chip.h +++ b/src/northbridge/intel/fsp_rangeley/chip.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -57,6 +58,15 @@ struct northbridge_intel_fsp_rangeley_config { #define BIFURCATION_8_8 3 #define BIFURCATION_16 4 uint8_t Bifurcation; + + /* PCIe port de-emphasis control */ + #define DE_EMPHASIS_DEFAULT 0 + #define DE_EMPHASIS_MINUS_6_0_DB 1 + #define DE_EMPHASIS_MINUS_3_5_DB 2 + uint8_t PcdPcieRootPort1DeEmphasis; + uint8_t PcdPcieRootPort2DeEmphasis; + uint8_t PcdPcieRootPort3DeEmphasis; + uint8_t PcdPcieRootPort4DeEmphasis; }; #endif diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index ae95087..3f8690a 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -143,6 +144,12 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) break; } } + + /* Set PCIe de-emphasis */ + UPD_DEFAULT_CHECK(PcdPcieRootPort1DeEmphasis); + UPD_DEFAULT_CHECK(PcdPcieRootPort2DeEmphasis); + UPD_DEFAULT_CHECK(PcdPcieRootPort3DeEmphasis); + UPD_DEFAULT_CHECK(PcdPcieRootPort4DeEmphasis); } /* Set up the Rangeley specific structures for the call into the FSP */ diff --git a/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h b/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h index 12ac2be..fba38a0 100644 --- a/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h +++ b/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (C) 2013, Intel Corporation +Copyright (C) 2013-2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -57,16 +57,21 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdEnableIQAT; /* Offset 0x0033 */ UINT8 PcdEnableUsb20; /* Offset 0x0034 */ UINT8 PcdBifurcation; /* Offset 0x0035 */ - UINT8 UnusedUpdSpace2[10]; /* Offset 0x0036 */ + UINT8 PcdPcieRootPort1DeEmphasis; /* Offset 0x0036 */ + UINT8 PcdPcieRootPort2DeEmphasis; /* Offset 0x0037 */ + UINT8 PcdPcieRootPort3DeEmphasis; /* Offset 0x0038 */ + UINT8 PcdPcieRootPort4DeEmphasis; /* Offset 0x0039 */ + UINT8 UnusedUpdSpace2[6]; /* Offset 0x003A */ UINT8 PcdPrintDebugMessages; /* Offset 0x0040 */ UINT8 PcdFastboot; /* Offset 0x0041 */ UINT8 PcdEccSupport; /* Offset 0x0042 */ - UINT8 UnusedUpdSpace3[13]; /* Offset 0x0043 */ - UINT16 PcdRegionTerminator; /* Offset 0x0050 */ + UINT8 PcdCustomerRevision[32]; /* Offset 0x0043 */ + UINT8 UnusedUpdSpace3[13]; /* Offset 0x0063 */ + UINT16 PcdRegionTerminator; /* Offset 0x0070 */ } UPD_DATA_REGION; #define VPD_IMAGE_ID 0x562D474E524E5641 /* 'AVNRNG-V' */ -#define VPD_IMAGE_REV 0x00000101 +#define VPD_IMAGE_REV 0x00000102 typedef struct _VPD_DATA_REGION { UINT64 PcdVpdRegionSign; /* Offset 0x0000 */

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Patch set updated for coreboot: 05bca04 intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP
by York Yang 30 Jan '15

30 Jan '15

York Yang (york.yang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8107 -gerrit commit 05bca047ef952ca19c8138211aa05628f47f0816 Author: York Yang <york.yang(a)intel.com> Date: Mon Jan 5 10:04:45 2015 -0700 intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration by UPD input. Update UPD_DATA_REGION structure for matching up this FSP change. PcdCustomerRevision is a debugging aid that will be output to debug message in FSP. It intend to be customized by BCT tool for tracking BCT configurations. Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b Signed-off-by: York Yang <york.yang(a)intel.com> --- src/northbridge/intel/fsp_rangeley/chip.h | 10 ++++++++++ src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c | 7 +++++++ src/vendorcode/intel/fsp/rangeley/include/fspvpd.h | 15 ++++++++++----- 3 files changed, 27 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h index 80a22bf..d3828c7 100644 --- a/src/northbridge/intel/fsp_rangeley/chip.h +++ b/src/northbridge/intel/fsp_rangeley/chip.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -57,6 +58,15 @@ struct northbridge_intel_fsp_rangeley_config { #define BIFURCATION_8_8 3 #define BIFURCATION_16 4 uint8_t Bifurcation; + + /* PCIe port de-emphasis control */ + #define DE_EMPHASIS_DEFAULT 0 + #define DE_EMPHASIS_MINUS_6_0_DB 1 + #define DE_EMPHASIS_MINUS_3_5_DB 2 + uint8_t PcdPcieRootPort1DeEmphasis; + uint8_t PcdPcieRootPort2DeEmphasis; + uint8_t PcdPcieRootPort3DeEmphasis; + uint8_t PcdPcieRootPort4DeEmphasis; }; #endif diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index ae95087..3f8690a 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -143,6 +144,12 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) break; } } + + /* Set PCIe de-emphasis */ + UPD_DEFAULT_CHECK(PcdPcieRootPort1DeEmphasis); + UPD_DEFAULT_CHECK(PcdPcieRootPort2DeEmphasis); + UPD_DEFAULT_CHECK(PcdPcieRootPort3DeEmphasis); + UPD_DEFAULT_CHECK(PcdPcieRootPort4DeEmphasis); } /* Set up the Rangeley specific structures for the call into the FSP */ diff --git a/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h b/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h index 12ac2be..fba38a0 100644 --- a/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h +++ b/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (C) 2013, Intel Corporation +Copyright (C) 2013-2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -57,16 +57,21 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdEnableIQAT; /* Offset 0x0033 */ UINT8 PcdEnableUsb20; /* Offset 0x0034 */ UINT8 PcdBifurcation; /* Offset 0x0035 */ - UINT8 UnusedUpdSpace2[10]; /* Offset 0x0036 */ + UINT8 PcdPcieRootPort1DeEmphasis; /* Offset 0x0036 */ + UINT8 PcdPcieRootPort2DeEmphasis; /* Offset 0x0037 */ + UINT8 PcdPcieRootPort3DeEmphasis; /* Offset 0x0038 */ + UINT8 PcdPcieRootPort4DeEmphasis; /* Offset 0x0039 */ + UINT8 UnusedUpdSpace2[6]; /* Offset 0x003A */ UINT8 PcdPrintDebugMessages; /* Offset 0x0040 */ UINT8 PcdFastboot; /* Offset 0x0041 */ UINT8 PcdEccSupport; /* Offset 0x0042 */ - UINT8 UnusedUpdSpace3[13]; /* Offset 0x0043 */ - UINT16 PcdRegionTerminator; /* Offset 0x0050 */ + UINT8 PcdCustomerRevision[32]; /* Offset 0x0043 */ + UINT8 UnusedUpdSpace3[13]; /* Offset 0x0063 */ + UINT16 PcdRegionTerminator; /* Offset 0x0070 */ } UPD_DATA_REGION; #define VPD_IMAGE_ID 0x562D474E524E5641 /* 'AVNRNG-V' */ -#define VPD_IMAGE_REV 0x00000101 +#define VPD_IMAGE_REV 0x00000102 typedef struct _VPD_DATA_REGION { UINT64 PcdVpdRegionSign; /* Offset 0x0000 */

1 0

Patch set updated for coreboot: 012fd4e FSP & CBMEM: Fix broken cbmem CAR transition.
by Martin Roth 30 Jan '15

30 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8196 -gerrit commit 012fd4e6c5683697dbe5c81bfc0d494e3f534ae1 Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jan 11 14:29:29 2015 -0700 FSP & CBMEM: Fix broken cbmem CAR transition. 1) Save the pointer to the FSP HOB list to low memory at address 0x614. This is the same location as CBMEM_RESUME_BACKUP - the two aren't used in the same platform, so overlapping should be OK. I didn't see any documentation that actually said that this location was free to use, and didn't need to be restored after use in S3 resume, but it looks like the DOS boot vector gets loaded juat above this location, so it SHOULD be ok. The alternative is to copy the memory out and store it in cbmem until we're ready to restore it. 2) When a request for the pointer to a CAR variable comes in, pass back the location inside the FSP hob structure. 3) Skip the memcopy of the CAR Data. The CAR variables do not get transitioned back into cbmem, but used out of the HOB structure. 4) Remove the BROKEN_CAR_MIGRATE Kconfig option from the FSP platform. Change-Id: Iaf566dce1b41a3bcb17e4134877f68262b5e113f Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 1 - src/cpu/intel/fsp_model_406dx/Kconfig | 1 - src/cpu/x86/car.c | 23 +++++++++++++++------- src/include/cbmem.h | 1 + .../intel/fsp_rangeley/fsp/chipset_fsp_util.c | 2 ++ .../intel/fsp_sandybridge/fsp/chipset_fsp_util.c | 1 + src/soc/intel/fsp_baytrail/Kconfig | 1 - src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 2 ++ 8 files changed, 22 insertions(+), 10 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index ea99ee0..05bdce4 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -41,7 +41,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER - select BROKEN_CAR_MIGRATE config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index c3acc78..ec4be84 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -36,7 +36,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER - select BROKEN_CAR_MIGRATE choice prompt "Rangeley CPU Stepping" diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index cca9afd..9f1a26e 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -23,6 +23,9 @@ #include <cbmem.h> #include <arch/early_variables.h> +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP) +#include <drivers/intel/fsp/fsp_util.h> +#endif typedef void (* const car_migration_func_t)(void); extern car_migration_func_t _car_migrate_start; @@ -41,10 +44,13 @@ extern char _car_data_end[]; */ static int car_migrated CAR_GLOBAL; - +/** @brief returns pointer to a CAR variable, before or after migration. + * + * @param var pointer to the CAR variable + */ void *car_get_var_ptr(void *var) { - char *migrated_base; + char *migrated_base = NULL; int offset; void * _car_start = &_car_data_start; void * _car_end = &_car_data_end; @@ -61,12 +67,15 @@ void *car_get_var_ptr(void *var) return var; } +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP) + migrated_base=(char *)find_saved_temp_mem( + *(void **)CBMEM_FSP_HOB_PTR); +#else migrated_base = cbmem_find(CBMEM_ID_CAR_GLOBALS); +#endif - if (migrated_base == NULL) { - printk(BIOS_ERR, "CAR: Could not find migration base!\n"); - return var; - } + if (migrated_base == NULL) + die( "CAR: Could not find migration base!\n"); offset = (char *)var - (char *)_car_start; @@ -140,7 +149,7 @@ static void do_car_migrate_hooks(void) void car_migrate_variables(void) { - if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE)) + if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE) && !IS_ENABLED(PLATFORM_USES_FSP)) do_car_migrate_variables(); if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE)) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ca7a5f4..2f86b85 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -40,6 +40,7 @@ */ #define CBMEM_BOOT_MODE 0x610 #define CBMEM_RESUME_BACKUP 0x614 +#define CBMEM_FSP_HOB_PTR 0x614 #define CBMEM_ID_FREESPACE 0x46524545 #define CBMEM_ID_GDT 0x4c474454 diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index ae95087..18c947f 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -167,6 +167,8 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; + if (Status == 0xFFFFFFFF) { soft_reset(); } diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c index a666d70..716873c 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c @@ -107,6 +107,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; if (Status == 0xFFFFFFFF) { hard_reset(); } diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index b05def2..0ebb5c7 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -50,7 +50,6 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS if INCLUDE_MICROCODE_IN_BUILD select CPU_MICROCODE_ADDED_DURING_BUILD if INCLUDE_MICROCODE_IN_BUILD select ROMSTAGE_RTC_INIT - select BROKEN_CAR_MIGRATE config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c6b5f9c..b8c1bf6 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -329,6 +329,8 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; + if (Status == 0xFFFFFFFF) { warm_reset(); }

1 0

Patch set updated for coreboot: 88cd30c FSP platforms: Clear area in CAR for cbmem
by Martin Roth 30 Jan '15

30 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8195 -gerrit commit 88cd30cb727fa86426bfc73fac688ac2e2b15515 Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jan 11 14:58:47 2015 -0700 FSP platforms: Clear area in CAR for cbmem This patch clears the CAR area. The FSP loads the entire CAR area with a pattern instead of clearing it. At least the cbmem area needs to be cleared or cbmem will not use it. Change-Id: I829ddc26133353a784dfc01729af9b3bf427e889 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/drivers/intel/fsp/cache_as_ram.inc | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/fsp/cache_as_ram.inc b/src/drivers/intel/fsp/cache_as_ram.inc index 9e8b2a2..8604c3b 100644 --- a/src/drivers/intel/fsp/cache_as_ram.inc +++ b/src/drivers/intel/fsp/cache_as_ram.inc @@ -91,14 +91,22 @@ CAR_init_done: * ecx: stack base * edx: stack top */ - lea -4(%edx), %esp + mov %edx, %esp movl %esp, %ebp - pushl %ebx + + /* Clear the cbmem CAR memory region. */ + movl %ecx, %edi + movl %edx, %ecx + sub %edi, %ecx + shr $2, %ecx + xorl %eax, %eax + rep stosl before_romstage: post_code(0x23) /* Call romstage.c main function. */ + pushl %ebx /* main takes FSP_INFO_HEADER as its argument */ call main /* does not return */ movb $0xB8, %ah jmp .Lhlt

1 0

Patch set updated for coreboot: 8b668f2 intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP
by York Yang 30 Jan '15

30 Jan '15

York Yang (york.yang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8107 -gerrit commit 8b668f2f2318f8d8f5162e247c20115fb6969158 Author: York Yang <york.yang(a)intel.com> Date: Mon Jan 5 10:04:45 2015 -0700 intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration by UPD input. Update UPD_DATA_REGION structure for matching up this FSP change. PcdCustomerRevision is a debugging aid that will be output to debug message in FSP. It intend to be customized by BCT tool for tracking BCT configurations. Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b Signed-off-by: York Yang <york.yang(a)intel.com> --- src/northbridge/intel/fsp_rangeley/chip.h | 10 ++++++++++ src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c | 7 +++++++ src/southbridge/intel/fsp_rangeley/chip.h | 0 src/vendorcode/intel/fsp/rangeley/include/fspvpd.h | 15 ++++++++++----- 4 files changed, 27 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h old mode 100644 new mode 100755 index 80a22bf..d3828c7 --- a/src/northbridge/intel/fsp_rangeley/chip.h +++ b/src/northbridge/intel/fsp_rangeley/chip.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -57,6 +58,15 @@ struct northbridge_intel_fsp_rangeley_config { #define BIFURCATION_8_8 3 #define BIFURCATION_16 4 uint8_t Bifurcation; + + /* PCIe port de-emphasis control */ + #define DE_EMPHASIS_DEFAULT 0 + #define DE_EMPHASIS_MINUS_6_0_DB 1 + #define DE_EMPHASIS_MINUS_3_5_DB 2 + uint8_t PcdPcieRootPort1DeEmphasis; + uint8_t PcdPcieRootPort2DeEmphasis; + uint8_t PcdPcieRootPort3DeEmphasis; + uint8_t PcdPcieRootPort4DeEmphasis; }; #endif diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c old mode 100644 new mode 100755 index ae95087..3f8690a --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -143,6 +144,12 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) break; } } + + /* Set PCIe de-emphasis */ + UPD_DEFAULT_CHECK(PcdPcieRootPort1DeEmphasis); + UPD_DEFAULT_CHECK(PcdPcieRootPort2DeEmphasis); + UPD_DEFAULT_CHECK(PcdPcieRootPort3DeEmphasis); + UPD_DEFAULT_CHECK(PcdPcieRootPort4DeEmphasis); } /* Set up the Rangeley specific structures for the call into the FSP */ diff --git a/src/southbridge/intel/fsp_rangeley/chip.h b/src/southbridge/intel/fsp_rangeley/chip.h old mode 100644 new mode 100755 diff --git a/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h b/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h old mode 100644 new mode 100755 index 12ac2be..fba38a0 --- a/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h +++ b/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (C) 2013, Intel Corporation +Copyright (C) 2013-2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -57,16 +57,21 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdEnableIQAT; /* Offset 0x0033 */ UINT8 PcdEnableUsb20; /* Offset 0x0034 */ UINT8 PcdBifurcation; /* Offset 0x0035 */ - UINT8 UnusedUpdSpace2[10]; /* Offset 0x0036 */ + UINT8 PcdPcieRootPort1DeEmphasis; /* Offset 0x0036 */ + UINT8 PcdPcieRootPort2DeEmphasis; /* Offset 0x0037 */ + UINT8 PcdPcieRootPort3DeEmphasis; /* Offset 0x0038 */ + UINT8 PcdPcieRootPort4DeEmphasis; /* Offset 0x0039 */ + UINT8 UnusedUpdSpace2[6]; /* Offset 0x003A */ UINT8 PcdPrintDebugMessages; /* Offset 0x0040 */ UINT8 PcdFastboot; /* Offset 0x0041 */ UINT8 PcdEccSupport; /* Offset 0x0042 */ - UINT8 UnusedUpdSpace3[13]; /* Offset 0x0043 */ - UINT16 PcdRegionTerminator; /* Offset 0x0050 */ + UINT8 PcdCustomerRevision[32]; /* Offset 0x0043 */ + UINT8 UnusedUpdSpace3[13]; /* Offset 0x0063 */ + UINT16 PcdRegionTerminator; /* Offset 0x0070 */ } UPD_DATA_REGION; #define VPD_IMAGE_ID 0x562D474E524E5641 /* 'AVNRNG-V' */ -#define VPD_IMAGE_REV 0x00000101 +#define VPD_IMAGE_REV 0x00000102 typedef struct _VPD_DATA_REGION { UINT64 PcdVpdRegionSign; /* Offset 0x0000 */

1 0

Patch set updated for coreboot: 96185f6 drivers/pc80/mc146818rtc: Reduce superfluous preprocessor use
by Alexandru Gagniuc 30 Jan '15

30 Jan '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8306 -gerrit commit 96185f629723caa80472f8826e193158034253f8 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 30 00:07:12 2015 -0600 drivers/pc80/mc146818rtc: Reduce superfluous preprocessor use cmos_init() had layers of preprocessor directives, which resulted in a complete mess. Refactor it to make use of the IS_ENABLED() macro. This improves readability significantly. One of the changes is to remove in inline stub declaration of (get|set)_option. Although that provided the ability for the compiler to optimize out code when USE_OPTION_TABLE is not selected, there is no evidence that such savings are measureable. Change-Id: I07f00084d809adbb55031b2079f71136ade3028e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/pc80/Makefile.inc | 4 +- src/drivers/pc80/mc146818rtc.c | 99 ++++++++++++++++++++++-------------------- src/include/pc80/mc146818rtc.h | 14 ++---- 3 files changed, 57 insertions(+), 60 deletions(-) diff --git a/src/drivers/pc80/Makefile.inc b/src/drivers/pc80/Makefile.inc index 1d28152..9715949 100644 --- a/src/drivers/pc80/Makefile.inc +++ b/src/drivers/pc80/Makefile.inc @@ -7,9 +7,7 @@ ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-y += keyboard.c ramstage-$(CONFIG_SPKMODEM) += spkmodem.c -ifeq ($(CONFIG_DRIVERS_MC146818),y) -romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c -endif +romstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_early.c romstage-$(CONFIG_LPC_TPM) += tpm.c romstage-$(CONFIG_SPKMODEM) += spkmodem.c diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index fc3adf0..b18f22f 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -26,9 +26,15 @@ #include <boot/coreboot_tables.h> #include <rtc.h> #include <string.h> +#include <cbfs.h> + +/* There's no way around this include guard. option_table.h is autogenerated */ #if CONFIG_USE_OPTION_TABLE #include "option_table.h" -#include <cbfs.h> +#else +#define LB_CKS_RANGE_START 0 +#define LB_CKS_RANGE_END 0 +#define LB_CKS_LOC 0 #endif @@ -48,7 +54,6 @@ static void cmos_reset_date(void) rtc_set(&time); } -#if CONFIG_USE_OPTION_TABLE static int cmos_checksum_valid(int range_start, int range_end, int cks_loc) { int i; @@ -71,19 +76,18 @@ static void cmos_set_checksum(int range_start, int range_end, int cks_loc) cmos_write(((sum >> 8) & 0x0ff), cks_loc); cmos_write(((sum >> 0) & 0x0ff), cks_loc + 1); } -#endif #define RTC_CONTROL_DEFAULT (RTC_24H) #define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ) #ifndef __SMM__ -void cmos_init(int invalid) +void cmos_init(bool invalid) { - int cmos_invalid = 0; - int checksum_invalid = 0; -#if CONFIG_USE_OPTION_TABLE - unsigned char x; -#endif + bool cmos_invalid = false; + bool checksum_invalid = false; + bool clear_cmos; + size_t i; + uint8_t x; #ifndef __PRE_RAM__ /* @@ -98,38 +102,37 @@ void cmos_init(int invalid) printk(BIOS_DEBUG, "RTC Init\n"); -#if CONFIG_USE_OPTION_TABLE - /* See if there has been a CMOS power problem. */ - x = cmos_read(RTC_VALID); - cmos_invalid = !(x & RTC_VRT); + if (IS_ENABLED(CONFIG_USE_OPTION_TABLE)) { + /* See if there has been a CMOS power problem. */ + x = cmos_read(RTC_VALID); + cmos_invalid = !(x & RTC_VRT); - /* See if there is a CMOS checksum error */ - checksum_invalid = !cmos_checksum_valid(PC_CKS_RANGE_START, - PC_CKS_RANGE_END,PC_CKS_LOC); + /* See if there is a CMOS checksum error */ + checksum_invalid = !cmos_checksum_valid(PC_CKS_RANGE_START, + PC_CKS_RANGE_END, PC_CKS_LOC); -#define CLEAR_CMOS 0 -#else -#define CLEAR_CMOS 1 -#endif + clear_cmos = false; + } else { + clear_cmos = true; + } if (invalid || cmos_invalid || checksum_invalid) { -#if CLEAR_CMOS - int i; - - cmos_write(0, 0x01); - cmos_write(0, 0x03); - cmos_write(0, 0x05); - for (i = 10; i < 128; i++) - cmos_write(0, i); -#endif + if (clear_cmos) { + cmos_write(0, 0x01); + cmos_write(0, 0x03); + cmos_write(0, 0x05); + for (i = 10; i < 128; i++) + cmos_write(0, i); + } + if (cmos_invalid) cmos_reset_date(); printk(BIOS_WARNING, "RTC:%s%s%s%s\n", - invalid?" Clear requested":"", - cmos_invalid?" Power Problem":"", - checksum_invalid?" Checksum invalid":"", - CLEAR_CMOS?" zeroing cmos":""); + invalid ? " Clear requested":"", + cmos_invalid ? " Power Problem":"", + checksum_invalid ? " Checksum invalid":"", + clear_cmos ? " zeroing cmos":""); } /* Setup the real time clock */ @@ -139,24 +142,23 @@ void cmos_init(int invalid) /* Ensure all reserved bits are 0 in register D */ cmos_write(RTC_VRT, RTC_VALID); -#if CONFIG_USE_OPTION_TABLE - /* See if there is a LB CMOS checksum error */ - checksum_invalid = !cmos_checksum_valid(LB_CKS_RANGE_START, - LB_CKS_RANGE_END,LB_CKS_LOC); - if (checksum_invalid) - printk(BIOS_DEBUG, "RTC: coreboot checksum invalid\n"); - - /* Make certain we have a valid checksum */ - cmos_set_checksum(PC_CKS_RANGE_START, PC_CKS_RANGE_END, PC_CKS_LOC); -#endif + if (IS_ENABLED(CONFIG_USE_OPTION_TABLE)) { + /* See if there is a LB CMOS checksum error */ + checksum_invalid = !cmos_checksum_valid(LB_CKS_RANGE_START, + LB_CKS_RANGE_END,LB_CKS_LOC); + if (checksum_invalid) + printk(BIOS_DEBUG, "RTC: coreboot checksum invalid\n"); + + /* Make certain we have a valid checksum */ + cmos_set_checksum(PC_CKS_RANGE_START, PC_CKS_RANGE_END, PC_CKS_LOC); + } /* Clear any pending interrupts */ cmos_read(RTC_INTR_FLAGS); } -#endif +#endif /* __SMM__ */ -#if CONFIG_USE_OPTION_TABLE /* * This routine returns the value of the requested bits. * input bit = bit count from the beginning of the cmos image @@ -200,6 +202,9 @@ enum cb_err get_option(void *dest, const char *name) size_t namelen; int found = 0; + if (!IS_ENABLED(CONFIG_USE_OPTION_TABLE)) + return CB_CMOS_OTABLE_DISABLED; + /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); @@ -280,6 +285,9 @@ enum cb_err set_option(const char *name, void *value) size_t namelen; int found = 0; + if (!IS_ENABLED(CONFIG_USE_OPTION_TABLE)) + return CB_CMOS_OTABLE_DISABLED; + /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); @@ -318,7 +326,6 @@ enum cb_err set_option(const char *name, void *value) return CB_SUCCESS; } -#endif /* CONFIG_USE_OPTION_TABLE */ /* * If the CMOS is cleared, the rtc_reg has the invalid date. That diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 90ae7ae..c74af66 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -169,21 +169,13 @@ static inline void cmos_write32(u8 offset, u32 value) #endif #if !defined(__ROMCC__) -void cmos_init(int invalid); +void cmos_init(bool invalid); void cmos_check_update_date(void); -#if CONFIG_USE_OPTION_TABLE + enum cb_err set_option(const char *name, void *val); enum cb_err get_option(void *dest, const char *name); unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def); -#else -static inline enum cb_err set_option(const char *name __attribute__((unused)), - void *val __attribute__((unused))) - { return CB_CMOS_OTABLE_DISABLED; }; -static inline enum cb_err get_option(void *dest __attribute__((unused)), - const char *name __attribute__((unused))) - { return CB_CMOS_OTABLE_DISABLED; } -#define read_option_lowlevel(start, size, def) def -#endif + #else /* defined(__ROMCC__) */ #include <drivers/pc80/mc146818rtc_early.c> #endif /* !defined(__ROMCC__) */

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coreboot-gerrit January 2015