January 2015 - coreboot-gerrit

Patch set updated for coreboot: 7f474d3 FSP chipsets: Use macro for 32 & 64 bit signatures

by Martin Roth

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8064 -gerrit commit 7f474d375152b602fb43645a04e36c71e2de3cfe Author: Martin Roth <martin.roth(a)se-eng.com> Date: Fri Jan 2 19:02:44 2015 -0700 FSP chipsets: Use macro for 32 & 64 bit signatures This takes what was already being done for the MRC_DATA_SIGNATURE and turns it into a macro, then uses that macro in all of the other places a 32-bit signature is needed. The macro is extended to 64-bits to use for all of the 64-bit signatures. This just makes things easier to read and understand. Change-Id: Ie5579056dbc4d10650ed77f91d5351615d394644 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/drivers/intel/fsp/fsp_util.c | 5 ++--- src/drivers/intel/fsp/fsp_util.h | 9 +++++++-- src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h | 3 +-- src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.h | 6 ++---- src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h | 3 +-- 5 files changed, 13 insertions(+), 13 deletions(-) diff --git a/src/drivers/intel/fsp/fsp_util.c b/src/drivers/intel/fsp/fsp_util.c index 2a53c25..c2a03b6 100644 --- a/src/drivers/intel/fsp/fsp_util.c +++ b/src/drivers/intel/fsp/fsp_util.c @@ -126,7 +126,7 @@ volatile u8 * find_fsp () fsp_ptr = (u8 *) CONFIG_FSP_LOC; /* Check the FV signature, _FVH */ - if (((EFI_FIRMWARE_VOLUME_HEADER *)fsp_ptr)->Signature == 0x4856465F) { + if (((EFI_FIRMWARE_VOLUME_HEADER *)fsp_ptr)->Signature == FIRMWARE_VOLUME_SIGNATURE) { /* Go to the end of the FV header and align the address. */ fsp_ptr += ((EFI_FIRMWARE_VOLUME_HEADER *)fsp_ptr)->ExtHeaderOffset; fsp_ptr += ((EFI_FIRMWARE_VOLUME_EXT_HEADER *)fsp_ptr)->ExtHeaderSize; @@ -169,8 +169,7 @@ volatile u8 * find_fsp () /* Verify the FSP ID */ if (((u32)fsp_ptr > 0xff) && - ((*(u32 *)(fsp_ptr + FSP_IMAGE_ID_LOC) != FSP_IMAGE_ID_DWORD0) || - (*(u32 *)(fsp_ptr + (FSP_IMAGE_ID_LOC + 4)) != FSP_IMAGE_ID_DWORD1))) { + (*(u64 *)(fsp_ptr + FSP_IMAGE_ID_LOC) != FSP_IMAGE_ID)) { fsp_ptr = (u8 *)ERROR_FSP_SIG_MISMATCH; } diff --git a/src/drivers/intel/fsp/fsp_util.h b/src/drivers/intel/fsp/fsp_util.h index d65b842..fd065fb 100644 --- a/src/drivers/intel/fsp/fsp_util.h +++ b/src/drivers/intel/fsp/fsp_util.h @@ -20,6 +20,10 @@ #ifndef FSP_UTIL_H #define FSP_UTIL_H +#define SIG_32_BIT(a,b,c,d) ((a << 0) | (b << 8) | (c << 16) | (d << 24)) +#define SIG_64_BIT(a,b,c,d,e,f,g,h) ((u64)SIG_32_BIT(a,b,c,d) | \ + ((u64)SIG_32_BIT(e,f,g,h) << 32)) + #include <chipset_fsp_util.h> #include "fsp_values.h" @@ -67,7 +71,7 @@ void printguid(EFI_GUID *guid); #if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) #define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) +#define MRC_DATA_SIGNATURE SIG_32_BIT('M','R','C','D') struct mrc_data_container { u32 mrc_signature; // "MRCD" @@ -90,7 +94,8 @@ void update_mrc_cache(void *unused); #define FSP_IMAGE_ID_LOC 16 #define FSP_IMAGE_BASE_LOC 28 -#define FSP_SIG 0x48505346 /* 'FSPH' */ +#define FSP_SIG SIG_32_BIT('F','S','P','H') +#define FIRMWARE_VOLUME_SIGNATURE SIG_32_BIT('_','F','V','H') #define ERROR_NO_FV_SIG 1 #define ERROR_NO_FFS_GUID 2 diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h index 3057865..7e07c9a 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h @@ -46,7 +46,6 @@ * can be used to verify that the right FSP binary is loaded. * For the Rangeley FSP, the Image Id is "AVN-FSP0". */ -#define FSP_IMAGE_ID_DWORD0 0x2d4e5641 /* 'AVN-' */ -#define FSP_IMAGE_ID_DWORD1 0x30505346 /* 'FSP0' */ +#define FSP_IMAGE_ID SIG_64_BIT('A','V','N','-','F','S','P','0') #endif /* CHIPSET_FSP_UTIL_H */ diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.h b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.h index f05b0fc..0018313 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.h +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.h @@ -52,12 +52,10 @@ #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) /* ST2-FSP0 */ -#define FSP_IMAGE_ID_DWORD0 0x2D325453 -#define FSP_IMAGE_ID_DWORD1 0x30505346 +#define FSP_IMAGE_ID SIG_64_BIT('S','T','2','-','F','S','P','0') #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X) /* CC2-FSP\0 */ -#define FSP_IMAGE_ID_DWORD0 0x2D324343 -#define FSP_IMAGE_ID_DWORD1 0x00505346 +#define FSP_IMAGE_ID SIG_64_BIT('C','C','2','-','F','S','P',0) #endif #ifdef __PRE_RAM__ diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h index 29309bf..f89169e 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h @@ -42,8 +42,7 @@ * can be used to verify that the right FSP binary is loaded. * For the Bay Trail FSP, the Image Id is "VLYVIEW0". */ -#define FSP_IMAGE_ID_DWORD0 0x56594C56 /* 'VLYV' */ -#define FSP_IMAGE_ID_DWORD1 0x30574549 /* 'IEW0' */ +#define FSP_IMAGE_ID SIG_64_BIT('V','L','Y','V','I','E','W','0') /* Revision of the FSP binary */ #define FSP_GOLD3_REV_ID 0x00000303

6 years, 7 months

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Patch set updated for coreboot: 91f63bf fsp_baytrail: Get FSP reserved memory from the FSP HOB list

by Martin Roth

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8308 -gerrit commit 91f63bf3d1f75a135e1a016c668eba279901bb6e Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jan 30 20:56:05 2015 -0700 fsp_baytrail: Get FSP reserved memory from the FSP HOB list Because the pointer to the FSP HOB list is now being saved, we can use that to find the top of usable memory. This eliminates the need to hardcode the size of the FSP reserved memory area. Tested on minnowboard max for baytrail. The HOB structure used does not seem to be present for the rangeley or ivybridge/pantherpoint FSPs. At the very least, the GUID is not documented in the integration guides. Change-Id: I643e57655f55bfada60075b55aad2ce010ec4f67 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/drivers/intel/fsp/fsp_util.c | 20 ++++++++++++++++++++ src/drivers/intel/fsp/fsp_util.h | 1 + src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h | 2 -- src/soc/intel/fsp_baytrail/memmap.c | 15 +++++++-------- src/soc/intel/fsp_baytrail/northcluster.c | 7 +------ 5 files changed, 29 insertions(+), 16 deletions(-) diff --git a/src/drivers/intel/fsp/fsp_util.c b/src/drivers/intel/fsp/fsp_util.c index 0844b37..2a53c25 100644 --- a/src/drivers/intel/fsp/fsp_util.c +++ b/src/drivers/intel/fsp/fsp_util.c @@ -195,6 +195,26 @@ void * find_saved_temp_mem(void *hob_list_ptr) return (void *) ((char *) saved_mem_hob + sizeof(EFI_HOB_GUID_TYPE)); } +#ifndef FSP_RESERVE_MEMORY_SIZE +/** @brief locates the HOB containing the location of the fsp reserved mem area + * + * @param hob_list_ptr pointer to the start of the hob list + * @return pointer to the start of the FSP reserved memory or NULL if not found. + */ +void * find_fsp_reserved_mem(void *hob_list_ptr) +{ + EFI_GUID fsp_reserved_guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; + EFI_HOB_RESOURCE_DESCRIPTOR *fsp_reserved_mem = + (EFI_HOB_RESOURCE_DESCRIPTOR *) find_hob_by_guid( + hob_list_ptr, &fsp_reserved_guid); + + if (fsp_reserved_mem == NULL) + return NULL; + + return (void *)((uintptr_t)fsp_reserved_mem->PhysicalStart); +} +#endif /* FSP_RESERVE_MEMORY_SIZE */ + #ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */ void print_fsp_info(void) { diff --git a/src/drivers/intel/fsp/fsp_util.h b/src/drivers/intel/fsp/fsp_util.h index a39f5a2..d65b842 100644 --- a/src/drivers/intel/fsp/fsp_util.h +++ b/src/drivers/intel/fsp/fsp_util.h @@ -38,6 +38,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, FSP_INFO_HEADER *fsp_ptr); void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr); void * find_saved_temp_mem(void *hob_list_ptr); +void * find_fsp_reserved_mem(void *hob_list_ptr); /* functions in hob.c */ void print_hob_mem_attributes(void *Hobptr); diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h index 1f4fa74..29309bf 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h @@ -32,8 +32,6 @@ #include <fspvpd.h> #include <azalia.h> -#define FSP_RESERVE_MEMORY_SIZE 0x200000 - #define FSP_INFO_HEADER_GUID \ { \ 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c index 615916b..8a10ac8 100644 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ b/src/soc/intel/fsp_baytrail/memmap.c @@ -29,18 +29,17 @@ uintptr_t smm_region_start(void) return (iosf_bunit_read(BUNIT_SMRRL) << 20); } -/* - * Calculate the top of usable (low) DRAM. - * The FSP's reserved memory sits just below the SMM region, - * allowing calculation of the top of usable memory. +/** @brief get the top of usable low memory from the FSP's HOB list + * + * The FSP's reserved memory sits just below the SMM region. The memory + * region below it is usable memory. * * The entire memory map is shown in northcluster.c + * + * @return pointer to the first byte of reserved memory */ void *cbmem_top(void) { - uintptr_t tom = smm_region_start(); - if (!tom) - tom = iosf_bunit_read(BUNIT_BMBOUND); - return (void *) tom - FSP_RESERVE_MEMORY_SIZE; + return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 838e554..b288388 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -149,8 +149,7 @@ static void mc_add_dram_resources(device_t dev) uint32_t fsp_mem_base = 0; GetHighMemorySize(&highmem_size); - GetLowMemorySize(&fsp_mem_base); - + fsp_mem_base=(uint32_t)cbmem_top(); bmbound = iosf_bunit_read(BUNIT_BMBOUND); bsmmrrl = iosf_bunit_read(BUNIT_SMRRL) << 20; @@ -162,10 +161,6 @@ static void mc_add_dram_resources(device_t dev) printk(BIOS_DEBUG, "FSP memory location: 0x%x\nFSP memory size: %dM\n", fsp_mem_base, (bsmmrrl - fsp_mem_base) >> 20); - - if ((bsmmrrl - fsp_mem_base ) != FSP_RESERVE_MEMORY_SIZE) - printk(BIOS_WARNING, "Warning: Fsp memory size does not match " - "expected memory size (%x).\n", FSP_RESERVE_MEMORY_SIZE); } printk(BIOS_INFO, "Available memory below 4GB: 0x%08x (%dM)\n",

6 years, 7 months

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New patch to review for coreboot: 3f595aa lenovo/x230: Set usb2_3_os_switchable_map.

by Vladimir Serbinenko

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8313 -gerrit commit 3f595aa13f6a25d2327ab9e25f356b0e8a8505b0 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 31 17:46:29 2015 +0100 lenovo/x230: Set usb2_3_os_switchable_map. Fixes USB3 ports degraded to USB2 speeds. Change-Id: Ie71c9fb6e52a3e72bb1e61351ad1cc0492d93cbc Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x230/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 5130410..8930813 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -67,6 +67,8 @@ chip northbridge/intel/sandybridge register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "usb2_3_os_switchable_map" = "0xf" + # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported

6 years, 7 months

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New patch to review for coreboot: 859f412 bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.

by Vladimir Serbinenko

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8312 -gerrit commit 859f4127a39496d850d2dd8bc6999d4d42947d47 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 31 17:45:50 2015 +0100 bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3. Change-Id: Ica1cc90715c1810668e3f4f7282e5757a5688483 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/bd82x6x/chip.h | 2 ++ src/southbridge/intel/bd82x6x/usb_xhci.c | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 290bb05..e4453d1 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -89,6 +89,8 @@ struct southbridge_intel_bd82x6x_config { int docking_supported; uint8_t pcie_hotplug_map[8]; + + uint32_t usb2_3_os_switchable_map; }; #endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index 19c419f..1956f8a 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -29,6 +29,7 @@ static void usb_xhci_init(struct device *dev) { u32 reg32; + struct southbridge_intel_bd82x6x_config *config = dev->chip_info; printk(BIOS_DEBUG, "XHCI: Setting up controller.. "); @@ -37,6 +38,9 @@ static void usb_xhci_init(struct device *dev) reg32 |= 1; pci_write_config32(dev, 0x44, reg32); + pci_write_config32(dev, 0xd4, config->usb2_3_os_switchable_map); + pci_write_config32(dev, 0xdc, config->usb2_3_os_switchable_map); + /* Enable clock gating */ reg32 = pci_read_config32(dev, 0x40); reg32 &= ~((1 << 20) | (1 << 21));

6 years, 7 months

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Patch set updated for coreboot: 049cce2 intel/nehalem: use nehalem smi finalizer instead of sandybridges

by Alexander Couzens

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8292 -gerrit commit 049cce2c291fd174ab6c9bcac877b4a7c212861c Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Tue Jan 27 11:57:43 2015 +0100 intel/nehalem: use nehalem smi finalizer instead of sandybridges The nehalem smi finalize handler was just copied from sandybridge. This patch prepares the usage of nehalem finalizer it's renaming the actual function and using it. So nehalem/finalize.c was unused before. TEST=Built and tested on x201t with additional patch to use finalizers Change-Id: Ifb44eeaaa6e03556deeb5d12ed1147e02d6d6eb9 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/mainboard/lenovo/x201/smihandler.c | 4 ++-- src/mainboard/packardbell/ms2290/smihandler.c | 4 ++-- src/northbridge/intel/nehalem/finalize.c | 2 +- src/northbridge/intel/nehalem/nehalem.h | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 7af613b..d8e7807 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -25,7 +25,7 @@ #include "southbridge/intel/ibexpeak/nvs.h" #include "southbridge/intel/ibexpeak/pch.h" #include "southbridge/intel/ibexpeak/me.h" -#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/nehalem/nehalem.h> #include <cpu/intel/model_2065x/model_2065x.h> #include <ec/acpi/ec.h> #include <pc80/mc146818rtc.h> @@ -164,7 +164,7 @@ int mainboard_smi_apmc(u8 data) intel_me_finalize_smm(); intel_pch_finalize_smm(); - intel_sandybridge_finalize_smm(); + intel_nehalem_finalize_smm(); intel_model_2065x_finalize_smm(); mainboard_finalized = 1; diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index f04ff90..bbe1597 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -25,7 +25,7 @@ #include "southbridge/intel/ibexpeak/nvs.h" #include "southbridge/intel/ibexpeak/pch.h" #include "southbridge/intel/ibexpeak/me.h" -#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/nehalem/nehalem.h> #include <cpu/intel/model_2065x/model_2065x.h> #include <ec/acpi/ec.h> #include <pc80/mc146818rtc.h> @@ -88,7 +88,7 @@ int mainboard_smi_apmc(u8 data) intel_me_finalize_smm(); intel_pch_finalize_smm(); - intel_sandybridge_finalize_smm(); + intel_nehalem_finalize_smm(); intel_model_2065x_finalize_smm(); mainboard_finalized = 1; diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c index 401d9ec..72baa48 100644 --- a/src/northbridge/intel/nehalem/finalize.c +++ b/src/northbridge/intel/nehalem/finalize.c @@ -24,7 +24,7 @@ #define PCI_DEV_SNB PCI_DEV(0, 0, 0) -void intel_sandybridge_finalize_smm(void) +void intel_nehalem_finalize_smm(void) { pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index 73137b2..d79b0b7 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -588,7 +588,7 @@ struct ied_header { #define PCI_DEVICE_ID_IB 0x0154 #ifdef __SMM__ -void intel_sandybridge_finalize_smm(void); +void intel_nehalem_finalize_smm(void); #else /* !__SMM__ */ int bridge_silicon_revision(void); void nehalem_early_initialization(int chipset_type);

6 years, 7 months

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Patch set updated for coreboot: 470b1c4 cpu/amd (non-AGESA): Remove terminator from microcode blob

by Kyösti Mälkki

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4534 -gerrit commit 470b1c4b905b6ae3cf31522d958e7668460e5558 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 16 07:19:09 2013 +0200 cpu/amd (non-AGESA): Remove terminator from microcode blob Change-Id: I6370e971922dee5e8d476a883c5f0f32fbbc8911 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/microcode/microcode.c | 14 +++++--------- src/cpu/amd/model_10xxx/microcode_blob.c | 6 ------ src/cpu/amd/model_fxx/microcode_blob.c | 6 ------ 3 files changed, 5 insertions(+), 21 deletions(-) diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index c9e2dcf..7278bf6 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -55,24 +55,20 @@ struct microcode { static void amd_update_microcode(const void *microcode_updates, u32 microcode_len, u32 equivalent_processor_rev_id) { u32 new_patch_id; - const struct microcode *m; - const char *c; msr_t msr; + const void *c = microcode_updates; + const void *ucode_end = microcode_updates + microcode_len; - m = microcode_updates; - - for(c = microcode_updates; m->date_code; m = (struct microcode *)c) { - + while ((c < ucode_end) && (c + 2048 <= ucode_end)) { + const struct microcode *m = c; if (m->processor_rev_id == equivalent_processor_rev_id) { //apply patch + printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", m->patch_id); msr.hi = 0; msr.lo = (u32)m; - wrmsr(0xc0010020, msr); - printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", m->patch_id); - //read the patch_id again msr = rdmsr(0x8b); new_patch_id = msr.lo; diff --git a/src/cpu/amd/model_10xxx/microcode_blob.c b/src/cpu/amd/model_10xxx/microcode_blob.c index 6544a2a..b99bb6b 100644 --- a/src/cpu/amd/model_10xxx/microcode_blob.c +++ b/src/cpu/amd/model_10xxx/microcode_blob.c @@ -25,10 +25,4 @@ unsigned char microcode[] __attribute__ ((aligned(16))) = { #include "mc_patch_010000b6.h" #include "mc_patch_010000bf.h" #include "mc_patch_010000c4.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/cpu/amd/model_fxx/microcode_blob.c b/src/cpu/amd/model_fxx/microcode_blob.c index 3210f62..b4c4bf1 100644 --- a/src/cpu/amd/model_fxx/microcode_blob.c +++ b/src/cpu/amd/model_fxx/microcode_blob.c @@ -25,10 +25,4 @@ unsigned char microcode[] __attribute__ ((aligned(16))) = { #include "microcode_rev_d.h" #include "microcode_rev_e.h" #endif - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, };

6 years, 7 months

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Patch set updated for coreboot: ee7b45b cpu/amd (non-AGESA): Load microcode updates from CBFS

by Kyösti Mälkki

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4502 -gerrit commit ee7b45bc915eae6458efde426cc579288b1c1599 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 8 07:21:05 2013 +0200 cpu/amd (non-AGESA): Load microcode updates from CBFS Change-Id: Ic67856414ea2fea9a9eb95d72136cb05da9483fa Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/microcode/microcode.c | 41 +++++++++++++++++----- src/cpu/amd/model_10xxx/Makefile.inc | 2 ++ src/cpu/amd/model_10xxx/microcode_blob.c | 28 +++++++++++++++ src/cpu/amd/model_10xxx/update_microcode.c | 27 ++------------ src/cpu/amd/model_fxx/Makefile.inc | 2 ++ src/cpu/amd/model_fxx/microcode_blob.c | 34 ++++++++++++++++++ src/cpu/amd/model_fxx/model_fxx_init.c | 2 +- src/cpu/amd/model_fxx/model_fxx_update_microcode.c | 29 ++------------- src/include/cpu/amd/microcode.h | 8 ++--- 9 files changed, 107 insertions(+), 66 deletions(-) diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index cdc6e4a..c9e2dcf 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -21,6 +21,7 @@ #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/amd/microcode.h> +#include <cbfs.h> struct microcode { u32 date_code; @@ -51,18 +52,13 @@ struct microcode { u8 x86_code_entry[191]; }; -void amd_update_microcode(void *microcode_updates, u32 equivalent_processor_rev_id) +static void amd_update_microcode(const void *microcode_updates, u32 microcode_len, u32 equivalent_processor_rev_id) { - u32 patch_id, new_patch_id; - struct microcode *m; - char *c; + u32 new_patch_id; + const struct microcode *m; + const char *c; msr_t msr; - msr = rdmsr(0x8b); - patch_id = msr.lo; - - printk(BIOS_DEBUG, "microcode: equivalent rev id = 0x%04x, current patch id = 0x%08x\n", equivalent_processor_rev_id, patch_id); - m = microcode_updates; for(c = microcode_updates; m->date_code; m = (struct microcode *)c) { @@ -88,3 +84,30 @@ void amd_update_microcode(void *microcode_updates, u32 equivalent_processor_rev_ } } + +#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" + +void amd_update_microcode_from_cbfs(u32 equivalent_processor_rev_id) +{ + struct cbfs_file *microcode_file; + const void *microcode_updates; + u32 microcode_len, patch_id; + msr_t msr; + + msr = rdmsr(0x8b); + patch_id = msr.lo; + + printk(BIOS_DEBUG, "microcode: equivalent rev id = 0x%04x, current patch id = 0x%08x\n", equivalent_processor_rev_id, patch_id); + if (equivalent_processor_rev_id == 0) { + printk(BIOS_DEBUG, "microcode: rev id not found. Skipping microcode patch!\n"); + return; + } + + microcode_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, MICROCODE_CBFS_FILE); + if (!microcode_file) + return; + + microcode_updates = CBFS_SUBHEADER(microcode_file); + microcode_len = ntohl(microcode_file->len); + amd_update_microcode(microcode_updates, microcode_len, equivalent_processor_rev_id); +} diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc index 5cfcc97..7d216ab 100644 --- a/src/cpu/amd/model_10xxx/Makefile.inc +++ b/src/cpu/amd/model_10xxx/Makefile.inc @@ -4,3 +4,5 @@ ramstage-y += processor_name.c romstage-$(CONFIG_UPDATE_CPU_MICROCODE) += update_microcode.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/amd/model_10xxx/microcode_blob.c b/src/cpu/amd/model_10xxx/microcode_blob.c new file mode 100644 index 0000000..c697cea --- /dev/null +++ b/src/cpu/amd/model_10xxx/microcode_blob.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned char microcode[] __attribute__ ((aligned(16))) = { +#include CONFIG_AMD_UCODE_PATCH_FILE + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c index dcaaf18..99fc23a 100644 --- a/src/cpu/amd/model_10xxx/update_microcode.c +++ b/src/cpu/amd/model_10xxx/update_microcode.c @@ -19,13 +19,8 @@ #include <stdint.h> #include <stdlib.h> -#include <console/console.h> #include <cpu/amd/microcode.h> -static const u8 microcode_updates[] __attribute__ ((aligned(16))) = { - -#ifdef __PRE_RAM__ - /* From the Revision Guide : * Equivalent Processor Table for AMD Family 10h Processors * @@ -47,16 +42,6 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = { * 00100FA0h (PH-E0) 10A0h 010000bfh */ -#include CONFIG_AMD_UCODE_PATCH_FILE - -#endif - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static const u32 id_mapping_table[] = { 0x100f00, 0x1000, 0x100f01, 0x1000, @@ -91,14 +76,6 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) void update_microcode(u32 cpu_deviceid) { - u32 equivalent_processor_rev_id; - - /* Update the microcode */ - equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid ); - if (equivalent_processor_rev_id != 0) { - amd_update_microcode((void *) microcode_updates, equivalent_processor_rev_id); - } else { - printk(BIOS_DEBUG, "microcode: rev id not found. Skipping microcode patch!\n"); - } - + u32 equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid); + amd_update_microcode_from_cbfs(equivalent_processor_rev_id); } diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc index cf4ac21..19a6255 100644 --- a/src/cpu/amd/model_fxx/Makefile.inc +++ b/src/cpu/amd/model_fxx/Makefile.inc @@ -5,3 +5,5 @@ ramstage-y += model_fxx_init.c ramstage-y += model_fxx_update_microcode.c ramstage-y += processor_name.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/amd/model_fxx/microcode_blob.c b/src/cpu/amd/model_fxx/microcode_blob.c new file mode 100644 index 0000000..3210f62 --- /dev/null +++ b/src/cpu/amd/model_fxx/microcode_blob.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned char microcode[] __attribute__ ((aligned(16))) = { +#if !CONFIG_K8_REV_F_SUPPORT + #include "microcode_rev_c.h" + #include "microcode_rev_d.h" + #include "microcode_rev_e.h" +#endif + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 260e83e..33226d4 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -468,7 +468,7 @@ static void model_fxx_init(device_t dev) x86_mtrr_check(); /* Update the microcode */ - model_fxx_update_microcode(dev->device); + update_microcode(dev->device); disable_cache(); diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c index 3e3afc6..eafb311 100644 --- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c +++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c @@ -21,27 +21,8 @@ #include <stdint.h> #include <stdlib.h> -#include <console/console.h> #include <cpu/amd/microcode.h> -static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = { - -#if !CONFIG_K8_REV_F_SUPPORT - #include "microcode_rev_c.h" - #include "microcode_rev_d.h" - #include "microcode_rev_e.h" -#endif - -#if CONFIG_K8_REV_F_SUPPORT -// #include "microcode_rev_f.h" -#endif - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static const u32 id_mapping_table[] = { #if !CONFIG_K8_REV_F_SUPPORT 0x0f48, 0x0048, @@ -82,12 +63,8 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) return new_id; } -void model_fxx_update_microcode(unsigned cpu_deviceid) +void update_microcode(u32 cpu_deviceid) { - unsigned equivalent_processor_rev_id; - - /* Update the microcode */ - equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid ); - if(equivalent_processor_rev_id != 0) - amd_update_microcode(microcode_updates, equivalent_processor_rev_id); + u32 equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid); + amd_update_microcode_from_cbfs(equivalent_processor_rev_id); } diff --git a/src/include/cpu/amd/microcode.h b/src/include/cpu/amd/microcode.h index e6d686c..9876a24 100644 --- a/src/include/cpu/amd/microcode.h +++ b/src/include/cpu/amd/microcode.h @@ -1,11 +1,9 @@ #ifndef CPU_AMD_MICROCODE_H #define CPU_AMD_MICROCODE_H -void amd_update_microcode(void *microcode_updates, unsigned processor_rev_id); -void model_fxx_update_microcode(unsigned cpu_deviceid); - -#if CONFIG_UPDATE_CPU_MICROCODE -void update_microcode(u32 processor_rev_id); +#if CONFIG_UPDATE_CPU_MICROCODE || CONFIG_NORTHBRIDGE_AMD_AMDK8 +void update_microcode(u32 cpu_deviceid); +void amd_update_microcode_from_cbfs(u32 equivalent_processor_rev_id); #else #define update_microcode(x) #endif

6 years, 7 months

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Patch set updated for coreboot: d8ebd57 cpu/amd (non-AGESA): Replace UPDATE_CPU_MICROCODE with SUPPORT_UCODE_IN_CBFS

by Kyösti Mälkki

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4503 -gerrit commit d8ebd578a93a75554311961ff3c7c0126c9e1361 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 8 07:56:34 2013 +0200 cpu/amd (non-AGESA): Replace UPDATE_CPU_MICROCODE with SUPPORT_UCODE_IN_CBFS Change-Id: I71e5b19bf451cef857cad2e2bb4bd8cc19d0ddd0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/microcode/Makefile.inc | 4 ++-- src/cpu/amd/model_10xxx/Kconfig | 33 +-------------------------------- src/cpu/amd/model_10xxx/Makefile.inc | 2 +- src/cpu/amd/model_fxx/Kconfig | 1 + src/cpu/amd/model_fxx/Makefile.inc | 2 +- src/include/cpu/amd/microcode.h | 2 +- 6 files changed, 7 insertions(+), 37 deletions(-) diff --git a/src/cpu/amd/microcode/Makefile.inc b/src/cpu/amd/microcode/Makefile.inc index 48f1d0d..6da939e 100644 --- a/src/cpu/amd/microcode/Makefile.inc +++ b/src/cpu/amd/microcode/Makefile.inc @@ -1,2 +1,2 @@ -ramstage-y += microcode.c -romstage-$(CONFIG_UPDATE_CPU_MICROCODE) += microcode.c +ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c +romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index cf5748c..1b79eb0 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -9,6 +9,7 @@ config CPU_AMD_MODEL_10XXX select MMCONF_SUPPORT_DEFAULT select TSC_SYNC_LFENCE select UDELAY_LAPIC + select SUPPORT_CPU_UCODE_IN_CBFS if CPU_AMD_MODEL_10XXX @@ -70,36 +71,4 @@ config UDELAY_LAPIC_FIXED_FSB int default 200 -config UPDATE_CPU_MICROCODE - bool - default y - -config UPDATE_CPU_MICROCODE - bool "Update CPU microcode" - default y - depends on EXPERT && CPU_AMD_MODEL_10XXX - help - Select this to apply patches to the CPU microcode provided by - AMD without source, and distributed with coreboot, to address - issues in the CPU post production. - - Microcode updates distributed with coreboot are not necessarily - the latest version available from AMD. Updates are only applied - if they are newer than the microcode already in your CPU. - - Unselect this to let Fam10h CPUs run with microcode as shipped - from factory. No binary microcode patches will be included in the - coreboot image in that case, which can help with creating an image - for which complete source code is available, which in turn might - simplify license compliance. - - Microcode updates intend to solve issues that have been discovered - after CPU production. The common case is that systems work as - intended with updated microcode, but we have also seen cases where - issues were solved by not applying the microcode updates. - - Note that some operating system include these same microcode - patches, so you may need to also disable microcode updates in - your operating system in order for this option to matter. - endif # CPU_AMD_MODEL_10XXX diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc index 7d216ab..4dbfd4b 100644 --- a/src/cpu/amd/model_10xxx/Makefile.inc +++ b/src/cpu/amd/model_10xxx/Makefile.inc @@ -2,7 +2,7 @@ romstage-y += ../../x86/mtrr/earlymtrr.c ramstage-y += model_10xxx_init.c ramstage-y += processor_name.c -romstage-$(CONFIG_UPDATE_CPU_MICROCODE) += update_microcode.c +romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += update_microcode.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index bdcf5bb..9ee2bf7 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -9,6 +9,7 @@ config CPU_AMD_MODEL_FXX select SSE2 select TSC_SYNC_LFENCE select UDELAY_LAPIC + select SUPPORT_CPU_UCODE_IN_CBFS if CPU_AMD_MODEL_FXX config UDELAY_IO diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc index 19a6255..c059de5 100644 --- a/src/cpu/amd/model_fxx/Makefile.inc +++ b/src/cpu/amd/model_fxx/Makefile.inc @@ -2,7 +2,7 @@ romstage-y += ../../x86/mtrr/earlymtrr.c # no conditionals here. If you include this file from a socket, then you get all the binaries. ramstage-y += model_fxx_init.c -ramstage-y += model_fxx_update_microcode.c +ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += model_fxx_update_microcode.c ramstage-y += processor_name.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c diff --git a/src/include/cpu/amd/microcode.h b/src/include/cpu/amd/microcode.h index 9876a24..cec5e58 100644 --- a/src/include/cpu/amd/microcode.h +++ b/src/include/cpu/amd/microcode.h @@ -1,7 +1,7 @@ #ifndef CPU_AMD_MICROCODE_H #define CPU_AMD_MICROCODE_H -#if CONFIG_UPDATE_CPU_MICROCODE || CONFIG_NORTHBRIDGE_AMD_AMDK8 +#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS void update_microcode(u32 cpu_deviceid); void amd_update_microcode_from_cbfs(u32 equivalent_processor_rev_id); #else

6 years, 7 months

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Patch set updated for coreboot: 99e7cb4 cpu/amd (non-AGESA): Fix CPU id_mapping_table

by Kyösti Mälkki

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4522 -gerrit commit 99e7cb4f1d685c5887642a3e523d1fa705e61f9a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Dec 12 06:50:21 2013 +0200 cpu/amd (non-AGESA): Fix CPU id_mapping_table In case a matching item is not in the array, the invalid use of sizeof will cause access beyond the end of array. Change-Id: I2be6d8f046d06702be21ed0155529c1bf41ede26 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/model_10xxx/update_microcode.c | 47 +++++++-------- src/cpu/amd/model_fxx/model_fxx_update_microcode.c | 70 ++++++++++------------ 2 files changed, 56 insertions(+), 61 deletions(-) diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c index 95624e9..dcaaf18 100644 --- a/src/cpu/amd/model_10xxx/update_microcode.c +++ b/src/cpu/amd/model_10xxx/update_microcode.c @@ -18,6 +18,7 @@ */ #include <stdint.h> +#include <stdlib.h> #include <console/console.h> #include <cpu/amd/microcode.h> @@ -56,38 +57,36 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = { 0x0, 0x0, 0x0, 0x0, }; -static u32 get_equivalent_processor_rev_id(u32 orig_id) { - static unsigned id_mapping_table[] = { - 0x100f00, 0x1000, - 0x100f01, 0x1000, - 0x100f02, 0x1000, - 0x100f20, 0x1020, - 0x100f21, 0x1020, - 0x100f2A, 0x1020, - 0x100f22, 0x1022, - 0x100f23, 0x1022, - 0x100f42, 0x1041, - 0x100f43, 0x1043, - 0x100f62, 0x1062, - 0x100f63, 0x1043, - 0x100f81, 0x1081, - 0x100fa0, 0x10A0, - }; +static const u32 id_mapping_table[] = { + 0x100f00, 0x1000, + 0x100f01, 0x1000, + 0x100f02, 0x1000, + 0x100f20, 0x1020, + 0x100f21, 0x1020, + 0x100f2A, 0x1020, + 0x100f22, 0x1022, + 0x100f23, 0x1022, + 0x100f42, 0x1041, + 0x100f43, 0x1043, + 0x100f62, 0x1062, + 0x100f63, 0x1043, + 0x100f81, 0x1081, + 0x100fa0, 0x10A0, +}; +#define ID_MAPPING_TABLE_LEN ARRAY_SIZE(id_mapping_table) - u32 new_id; +static unsigned get_equivalent_processor_rev_id(unsigned orig_id) +{ + unsigned new_id = 0; int i; - new_id = 0; - - for (i = 0; i < sizeof(id_mapping_table); i += 2 ) { - if(id_mapping_table[i]==orig_id) { + for (i = 0; i < ID_MAPPING_TABLE_LEN; i += 2) { + if (id_mapping_table[i]==orig_id) { new_id = id_mapping_table[i + 1]; break; } } - return new_id; - } void update_microcode(u32 cpu_deviceid) diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c index 4a53fea..3e3afc6 100644 --- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c +++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c @@ -19,6 +19,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <stdint.h> +#include <stdlib.h> #include <console/console.h> #include <cpu/amd/microcode.h> @@ -40,49 +42,43 @@ static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = { 0x0, 0x0, 0x0, 0x0, }; -static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { - static unsigned id_mapping_table[] = { - #if !CONFIG_K8_REV_F_SUPPORT - 0x0f48, 0x0048, - 0x0f58, 0x0048, - - 0x0f4a, 0x004a, - 0x0f5a, 0x004a, - 0x0f7a, 0x004a, - 0x0f82, 0x004a, - 0x0fc0, 0x004a, - 0x0ff0, 0x004a, - - 0x10f50, 0x0150, - 0x10f70, 0x0150, - 0x10f80, 0x0150, - 0x10fc0, 0x0150, - 0x10ff0, 0x0150, - - 0x20f10, 0x0210, - 0x20f12, 0x0210, - 0x20f32, 0x0210, - 0x20fb1, 0x0210, - #endif - - #if CONFIG_K8_REV_F_SUPPORT - - #endif - - }; +static const u32 id_mapping_table[] = { +#if !CONFIG_K8_REV_F_SUPPORT + 0x0f48, 0x0048, + 0x0f58, 0x0048, + + 0x0f4a, 0x004a, + 0x0f5a, 0x004a, + 0x0f7a, 0x004a, + 0x0f82, 0x004a, + 0x0fc0, 0x004a, + 0x0ff0, 0x004a, + + 0x10f50, 0x0150, + 0x10f70, 0x0150, + 0x10f80, 0x0150, + 0x10fc0, 0x0150, + 0x10ff0, 0x0150, + + 0x20f10, 0x0210, + 0x20f12, 0x0210, + 0x20f32, 0x0210, + 0x20fb1, 0x0210, +#endif +}; +#define ID_MAPPING_TABLE_LEN ARRAY_SIZE(id_mapping_table) - unsigned new_id; +static unsigned get_equivalent_processor_rev_id(unsigned orig_id) +{ + unsigned new_id = 0; int i; - new_id = 0; - - for(i=0; i<sizeof(id_mapping_table); i+=2 ) { - if(id_mapping_table[i]==orig_id) { - new_id = id_mapping_table[i+1]; + for (i = 0; i < ID_MAPPING_TABLE_LEN; i += 2) { + if (id_mapping_table[i]==orig_id) { + new_id = id_mapping_table[i + 1]; break; } } - return new_id; }

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Patch set updated for coreboot: 8acdc8f amd/model_10xxx: Drop AMD_UCODE_PATCH_FILE selection

by Kyösti Mälkki

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4521 -gerrit commit 8acdc8ffea75a51de5aea5f14b0a103041d3086a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 11 13:03:04 2013 +0200 amd/model_10xxx: Drop AMD_UCODE_PATCH_FILE selection Include microcode updates in CBFS for every CPU revision the platform can support, as changing to different CPU revision should not require a coreboot rebuild. This increases CBFS usage from 2 kB to 14 kB. Change-Id: I6bf90221a688f1a54e49641ce3ba378c5bf659f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/model_10xxx/microcode_blob.c | 8 +++++++- src/mainboard/advansus/a785e-i/Kconfig | 4 ---- src/mainboard/amd/bimini_fam10/Kconfig | 4 ---- src/mainboard/amd/mahogany_fam10/Kconfig | 4 ---- src/mainboard/amd/serengeti_cheetah_fam10/Kconfig | 4 ---- src/mainboard/amd/tilapia_fam10/Kconfig | 4 ---- src/mainboard/asus/kfsn4-dre/Kconfig | 4 ---- src/mainboard/asus/m4a78-em/Kconfig | 4 ---- src/mainboard/asus/m4a785-m/Kconfig | 4 ---- src/mainboard/asus/m4a785t-m/Kconfig | 4 ---- src/mainboard/asus/m5a88-v/Kconfig | 4 ---- src/mainboard/avalue/eax-785e/Kconfig | 4 ---- src/mainboard/gigabyte/ma785gm/Kconfig | 4 ---- src/mainboard/gigabyte/ma785gmt/Kconfig | 4 ---- src/mainboard/gigabyte/ma78gm/Kconfig | 4 ---- src/mainboard/hp/dl165_g6_fam10/Kconfig | 4 ---- src/mainboard/iei/kino-780am2-fam10/Kconfig | 4 ---- src/mainboard/jetway/pa78vm5/Kconfig | 4 ---- src/mainboard/msi/ms9652_fam10/Kconfig | 4 ---- src/mainboard/supermicro/h8dmr_fam10/Kconfig | 4 ---- src/mainboard/supermicro/h8qme_fam10/Kconfig | 4 ---- src/mainboard/supermicro/h8scm_fam10/Kconfig | 4 ---- src/mainboard/tyan/s2912_fam10/Kconfig | 4 ---- 23 files changed, 7 insertions(+), 89 deletions(-) diff --git a/src/cpu/amd/model_10xxx/microcode_blob.c b/src/cpu/amd/model_10xxx/microcode_blob.c index c697cea..6544a2a 100644 --- a/src/cpu/amd/model_10xxx/microcode_blob.c +++ b/src/cpu/amd/model_10xxx/microcode_blob.c @@ -18,7 +18,13 @@ */ unsigned char microcode[] __attribute__ ((aligned(16))) = { -#include CONFIG_AMD_UCODE_PATCH_FILE +#include "mc_patch_01000086.h" +#include "mc_patch_01000095.h" +#include "mc_patch_01000096.h" +#include "mc_patch_0100009f.h" +#include "mc_patch_010000b6.h" +#include "mc_patch_010000bf.h" +#include "mc_patch_010000c4.h" /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index ef7faf4..ab77898 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -69,10 +69,6 @@ config IRQ_SLOT_COUNT int default 11 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_010000b6.h" - config VGA_BIOS_ID string default "1002,9712" diff --git a/src/mainboard/amd/bimini_fam10/Kconfig b/src/mainboard/amd/bimini_fam10/Kconfig index 52f45e4..1af8d64 100644 --- a/src/mainboard/amd/bimini_fam10/Kconfig +++ b/src/mainboard/amd/bimini_fam10/Kconfig @@ -69,8 +69,4 @@ config IRQ_SLOT_COUNT int default 11 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_010000b6.h" - endif #BOARD_AMD_BIMINI_FAM10 diff --git a/src/mainboard/amd/mahogany_fam10/Kconfig b/src/mainboard/amd/mahogany_fam10/Kconfig index 8250580..acf88ef 100644 --- a/src/mainboard/amd/mahogany_fam10/Kconfig +++ b/src/mainboard/amd/mahogany_fam10/Kconfig @@ -57,10 +57,6 @@ config IRQ_SLOT_COUNT int default 11 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_01000095.h" - config VGA_BIOS_ID string default "1002,9615" diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig index 8677fc9..74f3c3b 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig @@ -58,8 +58,4 @@ config IRQ_SLOT_COUNT int default 11 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_01000095.h" - endif # BOARD_AMD_SERENGETI_CHEETAH_FAM10 diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig index 4f5b8d5..b6c9448 100644 --- a/src/mainboard/amd/tilapia_fam10/Kconfig +++ b/src/mainboard/amd/tilapia_fam10/Kconfig @@ -57,10 +57,6 @@ config IRQ_SLOT_COUNT int default 11 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_010000b6.h" - config VGA_BIOS bool default n diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index 245fecf..4c0e432 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -72,10 +72,6 @@ config IRQ_SLOT_COUNT int default 13 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_01000095.h" - config CK804_PCI_E_X int default 1 diff --git a/src/mainboard/asus/m4a78-em/Kconfig b/src/mainboard/asus/m4a78-em/Kconfig index 440b7f5..6118d12 100644 --- a/src/mainboard/asus/m4a78-em/Kconfig +++ b/src/mainboard/asus/m4a78-em/Kconfig @@ -56,8 +56,4 @@ config IRQ_SLOT_COUNT int default 18 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_010000b6.h" - endif diff --git a/src/mainboard/asus/m4a785-m/Kconfig b/src/mainboard/asus/m4a785-m/Kconfig index 5162e16..dd58db3 100644 --- a/src/mainboard/asus/m4a785-m/Kconfig +++ b/src/mainboard/asus/m4a785-m/Kconfig @@ -57,8 +57,4 @@ config IRQ_SLOT_COUNT int default 19 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_010000b6.h" - endif diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index 3e3fcea..19d8fd2 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -59,8 +59,4 @@ config IRQ_SLOT_COUNT int default 19 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_0100009f.h" - endif diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig index a76dd52..3a0f70f 100644 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ b/src/mainboard/asus/m5a88-v/Kconfig @@ -67,10 +67,6 @@ config IRQ_SLOT_COUNT int default 11 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_010000bf.h" - config VGA_BIOS_ID string default "1002,9715" diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig index 30fbe25..091dcee 100644 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ b/src/mainboard/avalue/eax-785e/Kconfig @@ -69,10 +69,6 @@ config IRQ_SLOT_COUNT int default 11 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_010000b6.h" - config VGA_BIOS_ID string default "1002,9712" diff --git a/src/mainboard/gigabyte/ma785gm/Kconfig b/src/mainboard/gigabyte/ma785gm/Kconfig index 82b5c4f..f830e81 100644 --- a/src/mainboard/gigabyte/ma785gm/Kconfig +++ b/src/mainboard/gigabyte/ma785gm/Kconfig @@ -57,8 +57,4 @@ config IRQ_SLOT_COUNT int default 11 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_010000b6.h" - endif # BOARD_GIGABYTE_MA785GM diff --git a/src/mainboard/gigabyte/ma785gmt/Kconfig b/src/mainboard/gigabyte/ma785gmt/Kconfig index 7ae9ef8..505d033 100644 --- a/src/mainboard/gigabyte/ma785gmt/Kconfig +++ b/src/mainboard/gigabyte/ma785gmt/Kconfig @@ -57,8 +57,4 @@ config IRQ_SLOT_COUNT int default 11 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_010000b6.h" - endif # BOARD_GIGABYTE_MA785GMT diff --git a/src/mainboard/gigabyte/ma78gm/Kconfig b/src/mainboard/gigabyte/ma78gm/Kconfig index cd4fadf..b36640f 100644 --- a/src/mainboard/gigabyte/ma78gm/Kconfig +++ b/src/mainboard/gigabyte/ma78gm/Kconfig @@ -57,8 +57,4 @@ config IRQ_SLOT_COUNT int default 11 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_01000095.h" - endif # BOARD_GIGABYTE_MA78GM diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index 5bb58db..f6aea01 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -64,10 +64,6 @@ config IRQ_SLOT_COUNT int default 15 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_01000095.h" - config BOOTBLOCK_MAINBOARD_INIT string default "mainboard/hp/dl165_g6_fam10/bootblock.c" diff --git a/src/mainboard/iei/kino-780am2-fam10/Kconfig b/src/mainboard/iei/kino-780am2-fam10/Kconfig index 7565043..069a4ae 100644 --- a/src/mainboard/iei/kino-780am2-fam10/Kconfig +++ b/src/mainboard/iei/kino-780am2-fam10/Kconfig @@ -57,10 +57,6 @@ config IRQ_SLOT_COUNT int default 11 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_01000086.h" - config VGA_BIOS_ID string default "1002,9615" diff --git a/src/mainboard/jetway/pa78vm5/Kconfig b/src/mainboard/jetway/pa78vm5/Kconfig index c779eca..56ad128 100644 --- a/src/mainboard/jetway/pa78vm5/Kconfig +++ b/src/mainboard/jetway/pa78vm5/Kconfig @@ -57,8 +57,4 @@ config IRQ_SLOT_COUNT int default 11 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_010000b6.h" - endif # BOARD_JETWAY_PA78VM5 diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index 91ddbbc..f7d99f8 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -89,10 +89,6 @@ config APIC_ID_OFFSET hex default 0x00 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_01000096.h" - config HT3_SUPPORT bool default y diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig b/src/mainboard/supermicro/h8dmr_fam10/Kconfig index 9f31542..3a72049 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig +++ b/src/mainboard/supermicro/h8dmr_fam10/Kconfig @@ -64,8 +64,4 @@ config IRQ_SLOT_COUNT int default 11 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_0100009f.h" - endif # BOARD_SUPERMICRO_H8DMR_FAM10 diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig b/src/mainboard/supermicro/h8qme_fam10/Kconfig index 89798aa..b3a1faf 100644 --- a/src/mainboard/supermicro/h8qme_fam10/Kconfig +++ b/src/mainboard/supermicro/h8qme_fam10/Kconfig @@ -62,8 +62,4 @@ config IRQ_SLOT_COUNT int default 11 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_0100009f.h" - endif # BOARD_SUPERMICRO_H8QME_FAM10 diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig index e76ecec..7fbbf66 100644 --- a/src/mainboard/supermicro/h8scm_fam10/Kconfig +++ b/src/mainboard/supermicro/h8scm_fam10/Kconfig @@ -57,8 +57,4 @@ config IRQ_SLOT_COUNT int default 11 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_010000c4.h" - endif # BOARD_AMD_H8SCM_FAM10 diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index 901a7ed..91a6e0d 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -68,10 +68,6 @@ config IRQ_SLOT_COUNT int default 11 -config AMD_UCODE_PATCH_FILE - string - default "mc_patch_01000095.h" - config MCP55_PCI_E_X_0 int default 1

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coreboot-gerrit January 2015