coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 2d19f0f drivers/pc80/mc146818rtc: Reduce superfluous preprocessor use
by Alexandru Gagniuc 30 Jan '15

30 Jan '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8306 -gerrit commit 2d19f0f06243325d83df004ca5e732db72ee9b85 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 30 00:07:12 2015 -0600 drivers/pc80/mc146818rtc: Reduce superfluous preprocessor use cmos_init() had layers of preprocessor directives, which resulted in a complete mess. Refactor it to make use of the IS_ENABLED() macro. This improves readability significantly. One of the changes is to remove in inline stub declaration of (get|set)_option. Although that provided the ability for the compiler to optimize out code when USE_OPTION_TABLE is not selected, there is no evidence that such savings are measureable. Change-Id: I07f00084d809adbb55031b2079f71136ade3028e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/pc80/Makefile.inc | 4 +- src/drivers/pc80/mc146818rtc.c | 99 ++++++++++++++++++++++-------------------- src/include/pc80/mc146818rtc.h | 14 ++---- 3 files changed, 57 insertions(+), 60 deletions(-) diff --git a/src/drivers/pc80/Makefile.inc b/src/drivers/pc80/Makefile.inc index 1d28152..9715949 100644 --- a/src/drivers/pc80/Makefile.inc +++ b/src/drivers/pc80/Makefile.inc @@ -7,9 +7,7 @@ ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-y += keyboard.c ramstage-$(CONFIG_SPKMODEM) += spkmodem.c -ifeq ($(CONFIG_DRIVERS_MC146818),y) -romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c -endif +romstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_early.c romstage-$(CONFIG_LPC_TPM) += tpm.c romstage-$(CONFIG_SPKMODEM) += spkmodem.c diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index fc3adf0..5f04292 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -26,9 +26,15 @@ #include <boot/coreboot_tables.h> #include <rtc.h> #include <string.h> +#include <cbfs.h> + +/* There's no way around this include guard. option_table.h is autogenerated */ #if CONFIG_USE_OPTION_TABLE #include "option_table.h" -#include <cbfs.h> +#else +#define LB_CKS_RANGE_START 0 +#define LB_CKS_RANGE_END 0 +#define LB_CKS_LOC 0 #endif @@ -48,7 +54,6 @@ static void cmos_reset_date(void) rtc_set(&time); } -#if CONFIG_USE_OPTION_TABLE static int cmos_checksum_valid(int range_start, int range_end, int cks_loc) { int i; @@ -71,19 +76,18 @@ static void cmos_set_checksum(int range_start, int range_end, int cks_loc) cmos_write(((sum >> 8) & 0x0ff), cks_loc); cmos_write(((sum >> 0) & 0x0ff), cks_loc + 1); } -#endif #define RTC_CONTROL_DEFAULT (RTC_24H) #define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ) #ifndef __SMM__ -void cmos_init(int invalid) +void cmos_init(bool invalid) { - int cmos_invalid = 0; - int checksum_invalid = 0; -#if CONFIG_USE_OPTION_TABLE - unsigned char x; -#endif + bool cmos_invalid = false; + bool checksum_invalid = false; + bool clear_cmos; + size_t i; + uint8_t x; #ifndef __PRE_RAM__ /* @@ -98,38 +102,37 @@ void cmos_init(int invalid) printk(BIOS_DEBUG, "RTC Init\n"); -#if CONFIG_USE_OPTION_TABLE - /* See if there has been a CMOS power problem. */ - x = cmos_read(RTC_VALID); - cmos_invalid = !(x & RTC_VRT); + if (IS_ENABLED(CONFIG_USE_OPTION_TABLE)) { + /* See if there has been a CMOS power problem. */ + x = cmos_read(RTC_VALID); + cmos_invalid = !(x & RTC_VRT); - /* See if there is a CMOS checksum error */ - checksum_invalid = !cmos_checksum_valid(PC_CKS_RANGE_START, - PC_CKS_RANGE_END,PC_CKS_LOC); + /* See if there is a CMOS checksum error */ + checksum_invalid = !cmos_checksum_valid(PC_CKS_RANGE_START, + PC_CKS_RANGE_END, PC_CKS_LOC); -#define CLEAR_CMOS 0 -#else -#define CLEAR_CMOS 1 -#endif + clear_cmos = false; + } else { + clear_cmos = true; + } if (invalid || cmos_invalid || checksum_invalid) { -#if CLEAR_CMOS - int i; - - cmos_write(0, 0x01); - cmos_write(0, 0x03); - cmos_write(0, 0x05); - for (i = 10; i < 128; i++) - cmos_write(0, i); -#endif + if(clear_cmos) { + cmos_write(0, 0x01); + cmos_write(0, 0x03); + cmos_write(0, 0x05); + for (i = 10; i < 128; i++) + cmos_write(0, i); + } + if (cmos_invalid) cmos_reset_date(); printk(BIOS_WARNING, "RTC:%s%s%s%s\n", - invalid?" Clear requested":"", - cmos_invalid?" Power Problem":"", - checksum_invalid?" Checksum invalid":"", - CLEAR_CMOS?" zeroing cmos":""); + invalid ? " Clear requested":"", + cmos_invalid ? " Power Problem":"", + checksum_invalid ? " Checksum invalid":"", + clear_cmos ? " zeroing cmos":""); } /* Setup the real time clock */ @@ -139,24 +142,23 @@ void cmos_init(int invalid) /* Ensure all reserved bits are 0 in register D */ cmos_write(RTC_VRT, RTC_VALID); -#if CONFIG_USE_OPTION_TABLE - /* See if there is a LB CMOS checksum error */ - checksum_invalid = !cmos_checksum_valid(LB_CKS_RANGE_START, - LB_CKS_RANGE_END,LB_CKS_LOC); - if (checksum_invalid) - printk(BIOS_DEBUG, "RTC: coreboot checksum invalid\n"); - - /* Make certain we have a valid checksum */ - cmos_set_checksum(PC_CKS_RANGE_START, PC_CKS_RANGE_END, PC_CKS_LOC); -#endif + if(IS_ENABLED(CONFIG_USE_OPTION_TABLE)) { + /* See if there is a LB CMOS checksum error */ + checksum_invalid = !cmos_checksum_valid(LB_CKS_RANGE_START, + LB_CKS_RANGE_END,LB_CKS_LOC); + if (checksum_invalid) + printk(BIOS_DEBUG, "RTC: coreboot checksum invalid\n"); + + /* Make certain we have a valid checksum */ + cmos_set_checksum(PC_CKS_RANGE_START, PC_CKS_RANGE_END, PC_CKS_LOC); + } /* Clear any pending interrupts */ cmos_read(RTC_INTR_FLAGS); } -#endif +#endif /* __SMM__ */ -#if CONFIG_USE_OPTION_TABLE /* * This routine returns the value of the requested bits. * input bit = bit count from the beginning of the cmos image @@ -200,6 +202,9 @@ enum cb_err get_option(void *dest, const char *name) size_t namelen; int found = 0; + if (!IS_ENABLED(CONFIG_USE_OPTION_TABLE)) + return CB_CMOS_OTABLE_DISABLED; + /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); @@ -280,6 +285,9 @@ enum cb_err set_option(const char *name, void *value) size_t namelen; int found = 0; + if (!IS_ENABLED(CONFIG_USE_OPTION_TABLE)) + return CB_CMOS_OTABLE_DISABLED; + /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); @@ -318,7 +326,6 @@ enum cb_err set_option(const char *name, void *value) return CB_SUCCESS; } -#endif /* CONFIG_USE_OPTION_TABLE */ /* * If the CMOS is cleared, the rtc_reg has the invalid date. That diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 90ae7ae..c74af66 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -169,21 +169,13 @@ static inline void cmos_write32(u8 offset, u32 value) #endif #if !defined(__ROMCC__) -void cmos_init(int invalid); +void cmos_init(bool invalid); void cmos_check_update_date(void); -#if CONFIG_USE_OPTION_TABLE + enum cb_err set_option(const char *name, void *val); enum cb_err get_option(void *dest, const char *name); unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def); -#else -static inline enum cb_err set_option(const char *name __attribute__((unused)), - void *val __attribute__((unused))) - { return CB_CMOS_OTABLE_DISABLED; }; -static inline enum cb_err get_option(void *dest __attribute__((unused)), - const char *name __attribute__((unused))) - { return CB_CMOS_OTABLE_DISABLED; } -#define read_option_lowlevel(start, size, def) def -#endif + #else /* defined(__ROMCC__) */ #include <drivers/pc80/mc146818rtc_early.c> #endif /* !defined(__ROMCC__) */

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Patch merged into coreboot/master: 9664345 devicetree: Search PnP device node from the tree by path
by gerrit＠coreboot.org 30 Jan '15

30 Jan '15

the following patch was just integrated into master: commit 96643455864a961881a3b2c4922ea76c3a5b4d20 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jan 28 22:03:46 2015 +0200 devicetree: Search PnP device node from the tree by path Copied from device_util.c with added ROMSTAGE_CONST. Change-Id: If872631ed96a79b9a0b15e09382d6f81098c8db3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8297 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8297 for details. -gerrit

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New patch to review for coreboot: 656e103 southbridge/intel/bd82x6x native usb init: replace some magic values
by Nicolas Reinecke 30 Jan '15

30 Jan '15

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8307 -gerrit commit 656e1035fd8be23c49df42079a2cc9558fb65d3e Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Thu Jan 29 15:48:27 2015 +0100 southbridge/intel/bd82x6x native usb init: replace some magic values Some magic numbers are documented in the PCH datasheet so use them. Change-Id: I15b58ff99b3bc11ac437e5ea74f4f01b7c02032a Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/southbridge/intel/bd82x6x/early_usb_native.c | 8 ++++---- src/southbridge/intel/bd82x6x/pch.h | 6 ++++++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/early_usb_native.c b/src/southbridge/intel/bd82x6x/early_usb_native.c index b1f8447..b8247c6 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_native.c +++ b/src/southbridge/intel/bd82x6x/early_usb_native.c @@ -33,7 +33,7 @@ early_usb_init (const struct southbridge_usb_port *portmap) /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, }; - const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51 , 0x2000094a, 0x2000035f }; + const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51, 0x2000094a, 0x2000035f }; int i; /* Activate PMBAR. */ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); @@ -56,17 +56,17 @@ early_usb_init (const struct southbridge_usb_port *portmap) for (i = 0; i < 14; i++) if (!portmap[i].enabled) reg32 |= (1 << i); - write32 (DEFAULT_RCBABASE | 0x359c, reg32); + write32 (DEFAULT_RCBABASE | USBPDO, reg32); reg32 = 0; for (i = 0; i < 8; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 0) reg32 |= (1 << (i + 8 * portmap[i].oc_pin)); - write32 (DEFAULT_RCBABASE | 0x35a0, reg32); + write32 (DEFAULT_RCBABASE | USBOCM1, reg32); reg32 = 0; for (i = 8; i < 14; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 4) reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4))); - write32 (DEFAULT_RCBABASE | 0x35a4, reg32); + write32 (DEFAULT_RCBABASE | USBOCM2, reg32); for (i = 0; i < 22; i++) write32 (DEFAULT_RCBABASE | (0x35a8 + 4 * i), 0); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 7cde7bc..cfdea7c 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -438,6 +438,12 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define PCH_DISABLE_MEI1 (1 << 1) #define PCH_ENABLE_DBDF (1 << 0) +/* USB Port Disable Override */ +#define USBPDO 0x359c /* 32bit */ +/* USB Overcurrent MAP Register */ +#define USBOCM1 0x35a0 /* 32bit */ +#define USBOCM2 0x35a4 /* 32bit */ + /* ICH7 GPIOBASE */ #define GPIO_USE_SEL 0x00 #define GP_IO_SEL 0x04

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Patch set updated for coreboot: 544d994 southbridge/intel/bd82x6x: add option to disable hdmi audio codec
by Nicolas Reinecke 30 Jan '15

30 Jan '15

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8303 -gerrit commit 544d9945a0f7fa6ae8560be1226332d79fade136 Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Thu Jan 29 23:43:06 2015 +0100 southbridge/intel/bd82x6x: add option to disable hdmi audio codec Some Thinkpads like T420s or T520 with discrete GPU have only VGA and LVDS conntected to the IGP. For this devices is it usefull to have an option to disable the audio codec. Change-Id: Iaa60b6d4c3c98ec9616ea0ef43913bbcf0d315da Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/mainboard/lenovo/t420s/devicetree.cb | 3 +++ src/mainboard/lenovo/t520/devicetree.cb | 3 +++ src/southbridge/intel/bd82x6x/azalia.c | 23 +++++++++++------------ src/southbridge/intel/bd82x6x/chip.h | 2 ++ 4 files changed, 19 insertions(+), 12 deletions(-) diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 990b576..25c8105 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -61,6 +61,9 @@ chip northbridge/intel/sandybridge # Set max SATA speed to 6.0 Gb/s register "sata_interface_speed_support" = "0x3" + # disable HDMI audio for discrete gpu models + register "azalia_hdmi_disable" = "1" + register "gen1_dec" = "0x7c1601" register "gen2_dec" = "0x0c15e1" register "gen4_dec" = "0x0c06a1" diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index d2a4d6b..058eec8 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -57,6 +57,9 @@ chip northbridge/intel/sandybridge # Set max SATA speed to 6.0 Gb/s register "sata_interface_speed_support" = "0x3" + # disable HDMI audio for discrete gpu models + register "azalia_hdmi_disable" = "1" + register "gen1_dec" = "0x7c1601" register "gen2_dec" = "0x0c15e1" register "gen4_dec" = "0x0c06a1" diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index bef88ab..a000a64 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -228,6 +228,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask) static void azalia_init(struct device *dev) { + struct southbridge_intel_bd82x6x_config *config = dev->chip_info; u32 base; struct resource *res; u32 codec_mask; @@ -267,22 +268,20 @@ static void azalia_init(struct device *dev) reg32 |= (1 << 31); pci_write_config32(dev, 0x120, reg32); - // Enable HDMI codec: - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 1); - pci_write_config32(dev, 0xc4, reg32); + if (!(config->azalia_hdmi_disable)) { + // Enable HDMI codec: + reg32 = pci_read_config32(dev, 0xc4); + reg32 |= (1 << 1); + pci_write_config32(dev, 0xc4, reg32); - reg8 = pci_read_config8(dev, 0x43); - reg8 |= (1 << 6); - pci_write_config8(dev, 0x43, reg8); + reg8 = pci_read_config8(dev, 0x43); + reg8 |= (1 << 6); + pci_write_config8(dev, 0x43, reg8); + } /* Additional programming steps */ reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 13); - pci_write_config32(dev, 0xc4, reg32); - - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 10); + reg32 |= (1 << 13) | (1 << 10); pci_write_config32(dev, 0xc4, reg32); reg32 = pci_read_config32(dev, 0xd0); diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 290bb05..6182e44 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -89,6 +89,8 @@ struct southbridge_intel_bd82x6x_config { int docking_supported; uint8_t pcie_hotplug_map[8]; + + uint8_t azalia_hdmi_disable; }; #endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */

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Patch set updated for coreboot: d453276 southbridge/intel/bd82x6x: add option to disable hdmi audio codec
by Nicolas Reinecke 30 Jan '15

30 Jan '15

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8303 -gerrit commit d45327629292f28eec63cc02a1130b9dc40417a7 Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Thu Jan 29 23:43:06 2015 +0100 southbridge/intel/bd82x6x: add option to disable hdmi audio codec Some Thinkpads like T420s or T520 with discrete GPU have only VGA and LVDS conntected to the IGP. For this devices is it usefull to have an option to disable the audio codec. Change-Id: Iaa60b6d4c3c98ec9616ea0ef43913bbcf0d315da Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/southbridge/intel/bd82x6x/azalia.c | 23 +++++++++++------------ src/southbridge/intel/bd82x6x/chip.h | 2 ++ 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index bef88ab..a000a64 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -228,6 +228,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask) static void azalia_init(struct device *dev) { + struct southbridge_intel_bd82x6x_config *config = dev->chip_info; u32 base; struct resource *res; u32 codec_mask; @@ -267,22 +268,20 @@ static void azalia_init(struct device *dev) reg32 |= (1 << 31); pci_write_config32(dev, 0x120, reg32); - // Enable HDMI codec: - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 1); - pci_write_config32(dev, 0xc4, reg32); + if (!(config->azalia_hdmi_disable)) { + // Enable HDMI codec: + reg32 = pci_read_config32(dev, 0xc4); + reg32 |= (1 << 1); + pci_write_config32(dev, 0xc4, reg32); - reg8 = pci_read_config8(dev, 0x43); - reg8 |= (1 << 6); - pci_write_config8(dev, 0x43, reg8); + reg8 = pci_read_config8(dev, 0x43); + reg8 |= (1 << 6); + pci_write_config8(dev, 0x43, reg8); + } /* Additional programming steps */ reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 13); - pci_write_config32(dev, 0xc4, reg32); - - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 10); + reg32 |= (1 << 13) | (1 << 10); pci_write_config32(dev, 0xc4, reg32); reg32 = pci_read_config32(dev, 0xd0); diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 290bb05..6182e44 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -89,6 +89,8 @@ struct southbridge_intel_bd82x6x_config { int docking_supported; uint8_t pcie_hotplug_map[8]; + + uint8_t azalia_hdmi_disable; }; #endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */

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Patch set updated for coreboot: 79682f8 intel/cpu/model_2065x|nehalem: remove unsupported MSR_PP0/MSR_PP1
by Alexander Couzens 30 Jan '15

30 Jan '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8295 -gerrit commit 79682f829f0458b3222e358e760148e1a6d27bdd Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Jan 28 03:00:42 2015 +0100 intel/cpu/model_2065x|nehalem: remove unsupported MSR_PP0/MSR_PP1 It seems to be a relict when this cpu support was backported from sandybridge. Change-Id: I2277bb90e6da2676b31eb2665b7c15f074e3d4bf Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/cpu/intel/model_2065x/finalize.c | 18 +----------------- src/cpu/intel/model_2065x/model_2065x.h | 10 ---------- 2 files changed, 1 insertion(+), 27 deletions(-) diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index 3c494e4..a97c76b 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2015 Alexander Couzens <lynxis(a)fe80.eu> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -52,23 +53,6 @@ void intel_model_2065x_finalize_smm(void) if (cpuid_ecx(1) & (1 << 25)) msr_set_bit(MSR_FEATURE_CONFIG, 0); -#ifdef LOCK_POWER_CONTROL_REGISTERS - /* - * Lock the power control registers. - * - * These registers can be left unlocked if modifying power - * limits from the OS is desirable. Modifying power limits - * from the OS can be especially useful for experimentation - * during early phases of system bringup while the thermal - * power envelope is being proven. - */ - - msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31); - msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31); - msr_set_bit(MSR_PKG_POWER_LIMIT, 63); - msr_set_bit(MSR_PP0_POWER_LIMIT, 31); - msr_set_bit(MSR_PP1_POWER_LIMIT, 31); -#endif /* Lock TM interupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index f9dc7e8..454f7be 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -74,16 +74,6 @@ #define PKG_POWER_LIMIT_TIME_SHIFT 17 #define PKG_POWER_LIMIT_TIME_MASK 0x7f -#define MSR_PP0_CURRENT_CONFIG 0x601 -#define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */ -#define MSR_PP1_CURRENT_CONFIG 0x602 -#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */ -#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */ -#define MSR_PKG_POWER_SKU_UNIT 0x606 -#define MSR_PKG_POWER_SKU 0x614 -#define MSR_PP0_POWER_LIMIT 0x638 -#define MSR_PP1_POWER_LIMIT 0x640 - #define IVB_CONFIG_TDP_MIN_CPUID 0x306a2 #define MSR_CONFIG_TDP_NOMINAL 0x648 #define MSR_CONFIG_TDP_LEVEL1 0x649

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Patch set updated for coreboot: c30b34e cpu/intel: >= nehalem: add comments to msr finalize's
by Alexander Couzens 30 Jan '15

30 Jan '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8294 -gerrit commit c30b34e4fffc1b3f5107006a8d3ab0c1c038eb4e Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Jan 28 01:51:04 2015 +0100 cpu/intel: >= nehalem: add comments to msr finalize's Improve documentation of lock down MSRs in finalize(). Most of these aren't documented in public MSRs. Change-Id: I4fc47bb9b71bdd7907aae65fc18b419a17ae8547 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/cpu/intel/fsp_model_206ax/finalize.c | 5 +++++ src/cpu/intel/haswell/finalize.c | 5 +++++ src/cpu/intel/model_2065x/finalize.c | 6 +++++- src/cpu/intel/model_206ax/finalize.c | 5 +++++ 4 files changed, 20 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/fsp_model_206ax/finalize.c b/src/cpu/intel/fsp_model_206ax/finalize.c index 4ed5d1e..179d978 100644 --- a/src/cpu/intel/fsp_model_206ax/finalize.c +++ b/src/cpu/intel/fsp_model_206ax/finalize.c @@ -43,6 +43,8 @@ static void msr_set_bit(unsigned reg, unsigned bit) void intel_model_206ax_finalize_smm(void) { + /* Look into Bios Writer's Guide for the meaning of these MSR */ + /* Lock C-State MSR */ msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ @@ -67,6 +69,9 @@ void intel_model_206ax_finalize_smm(void) msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif + /* Lock TM interupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); + + /* Lock memory configuration to protect SMM */ msr_set_bit(MSR_LT_LOCK_MEMORY, 0); } diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index 1731322..0a53a25 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -46,6 +46,8 @@ static void msr_set_bit(unsigned reg, unsigned bit) void intel_cpu_haswell_finalize_smm(void) { #if 0 + /* Look into Bios Writer's Guide for the meaning of these MSR */ + /* Lock C-State MSR */ msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ @@ -70,7 +72,10 @@ void intel_cpu_haswell_finalize_smm(void) msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif + /* Lock TM interupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); + + /* Lock memory configuration to protect SMM */ msr_set_bit(MSR_LT_LOCK_MEMORY, 0); #endif } diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index b37a84c..3c494e4 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -44,6 +44,8 @@ static void msr_set_bit(unsigned reg, unsigned bit) void intel_model_2065x_finalize_smm(void) { + /* Look into Bios Writer's Guide for the meaning of these MSRs */ + /* Lock C-State MSR */ msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ @@ -67,7 +69,9 @@ void intel_model_2065x_finalize_smm(void) msr_set_bit(MSR_PP0_POWER_LIMIT, 31); msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif - + /* Lock TM interupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); + + /* Lock memory configuration to protect SMM */ msr_set_bit(MSR_LT_LOCK_MEMORY, 0); } diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 2c215a4..6d16c95 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -44,6 +44,8 @@ static void msr_set_bit(unsigned reg, unsigned bit) void intel_model_206ax_finalize_smm(void) { + /* Look into Bios Writer's Guide for the meaning of these MSR */ + /* Lock C-State MSR */ msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ @@ -68,6 +70,9 @@ void intel_model_206ax_finalize_smm(void) msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif + /* Lock TM interupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); + + /* Lock memory configuration to protect SMM */ msr_set_bit(MSR_LT_LOCK_MEMORY, 0); }

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Patch set updated for coreboot: 4927574 utils/msrtool: add westmere cpuids to nehalem
by Alexander Couzens 30 Jan '15

30 Jan '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8293 -gerrit commit 4927574c9a7ca8c4b24447474d5632269dad868b Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Tue Jan 27 13:30:52 2015 +0100 utils/msrtool: add westmere cpuids to nehalem Westmere's are nehalem's in 32nm Change-Id: I529194d50dbe3f585faee14961542433ea96ab75 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- util/msrtool/intel_nehalem.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c index 3c2cbf8..3674615 100644 --- a/util/msrtool/intel_nehalem.c +++ b/util/msrtool/intel_nehalem.c @@ -24,7 +24,10 @@ int intel_nehalem_probe(const struct targetdef *target, const struct cpuid_t *id (0x1a == id->model) || (0x1e == id->model) || (0x1f == id->model) || - (0x2e == id->model) + (0x2e == id->model) || + (0x25 == id->model) || /* westmere */ + (0x2c == id->model) || /* westmere */ + (0x2f == id->model) /* westmere */ )); }

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Patch set updated for coreboot: d2c905e intel/nehalem: use nehalem smi finalizer instead of sandybridges
by Alexander Couzens 30 Jan '15

30 Jan '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8292 -gerrit commit d2c905ee17d61ff1d0c4b6dc35277106d7b52c93 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Tue Jan 27 11:57:43 2015 +0100 intel/nehalem: use nehalem smi finalizer instead of sandybridges The nehalem smi finalize handler was just copied from sandybridge. This patch prepares the usage of nehalem finalizer it's renaming the actual function and using it. So nehalem/finalize.c was unused before. TEST=Built and tested on x201t with additional patch to use finalizers Change-Id: Ifb44eeaaa6e03556deeb5d12ed1147e02d6d6eb9 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/mainboard/lenovo/x201/smihandler.c | 4 ++-- src/mainboard/packardbell/ms2290/smihandler.c | 4 ++-- src/northbridge/intel/nehalem/finalize.c | 2 +- src/northbridge/intel/nehalem/nehalem.h | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 7af613b..d8e7807 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -25,7 +25,7 @@ #include "southbridge/intel/ibexpeak/nvs.h" #include "southbridge/intel/ibexpeak/pch.h" #include "southbridge/intel/ibexpeak/me.h" -#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/nehalem/nehalem.h> #include <cpu/intel/model_2065x/model_2065x.h> #include <ec/acpi/ec.h> #include <pc80/mc146818rtc.h> @@ -164,7 +164,7 @@ int mainboard_smi_apmc(u8 data) intel_me_finalize_smm(); intel_pch_finalize_smm(); - intel_sandybridge_finalize_smm(); + intel_nehalem_finalize_smm(); intel_model_2065x_finalize_smm(); mainboard_finalized = 1; diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index f04ff90..bbe1597 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -25,7 +25,7 @@ #include "southbridge/intel/ibexpeak/nvs.h" #include "southbridge/intel/ibexpeak/pch.h" #include "southbridge/intel/ibexpeak/me.h" -#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/nehalem/nehalem.h> #include <cpu/intel/model_2065x/model_2065x.h> #include <ec/acpi/ec.h> #include <pc80/mc146818rtc.h> @@ -88,7 +88,7 @@ int mainboard_smi_apmc(u8 data) intel_me_finalize_smm(); intel_pch_finalize_smm(); - intel_sandybridge_finalize_smm(); + intel_nehalem_finalize_smm(); intel_model_2065x_finalize_smm(); mainboard_finalized = 1; diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c index 401d9ec..72baa48 100644 --- a/src/northbridge/intel/nehalem/finalize.c +++ b/src/northbridge/intel/nehalem/finalize.c @@ -24,7 +24,7 @@ #define PCI_DEV_SNB PCI_DEV(0, 0, 0) -void intel_sandybridge_finalize_smm(void) +void intel_nehalem_finalize_smm(void) { pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index 73137b2..d79b0b7 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -588,7 +588,7 @@ struct ied_header { #define PCI_DEVICE_ID_IB 0x0154 #ifdef __SMM__ -void intel_sandybridge_finalize_smm(void); +void intel_nehalem_finalize_smm(void); #else /* !__SMM__ */ int bridge_silicon_revision(void); void nehalem_early_initialization(int chipset_type);

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Patch set updated for coreboot: 401ee32 intel/nehalem: use nehalem smi finalizer instead of sandybridges
by Alexander Couzens 30 Jan '15

30 Jan '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8292 -gerrit commit 401ee3221b38492ea97740d94a9534e30b7b9564 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Tue Jan 27 11:57:43 2015 +0100 intel/nehalem: use nehalem smi finalizer instead of sandybridges The nehalem smi finalize handler was just copied from sandybridge. This patch prepares the usage of nehalem finalizer it's renaming the actual function and using it. So nehalem/finalize.c was unused before. TEST=Built and tested on x201t with additional patch to use finalizers Change-Id: Ifb44eeaaa6e03556deeb5d12ed1147e02d6d6eb9 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/mainboard/lenovo/x201/smihandler.c | 4 ++-- src/mainboard/packardbell/ms2290/smihandler.c | 4 ++-- src/northbridge/intel/nehalem/finalize.c | 2 +- src/northbridge/intel/nehalem/nehalem.h | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 7af613b..d8e7807 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -25,7 +25,7 @@ #include "southbridge/intel/ibexpeak/nvs.h" #include "southbridge/intel/ibexpeak/pch.h" #include "southbridge/intel/ibexpeak/me.h" -#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/nehalem/nehalem.h> #include <cpu/intel/model_2065x/model_2065x.h> #include <ec/acpi/ec.h> #include <pc80/mc146818rtc.h> @@ -164,7 +164,7 @@ int mainboard_smi_apmc(u8 data) intel_me_finalize_smm(); intel_pch_finalize_smm(); - intel_sandybridge_finalize_smm(); + intel_nehalem_finalize_smm(); intel_model_2065x_finalize_smm(); mainboard_finalized = 1; diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index f04ff90..bbe1597 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -25,7 +25,7 @@ #include "southbridge/intel/ibexpeak/nvs.h" #include "southbridge/intel/ibexpeak/pch.h" #include "southbridge/intel/ibexpeak/me.h" -#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/nehalem/nehalem.h> #include <cpu/intel/model_2065x/model_2065x.h> #include <ec/acpi/ec.h> #include <pc80/mc146818rtc.h> @@ -88,7 +88,7 @@ int mainboard_smi_apmc(u8 data) intel_me_finalize_smm(); intel_pch_finalize_smm(); - intel_sandybridge_finalize_smm(); + intel_nehalem_finalize_smm(); intel_model_2065x_finalize_smm(); mainboard_finalized = 1; diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c index 401d9ec..72baa48 100644 --- a/src/northbridge/intel/nehalem/finalize.c +++ b/src/northbridge/intel/nehalem/finalize.c @@ -24,7 +24,7 @@ #define PCI_DEV_SNB PCI_DEV(0, 0, 0) -void intel_sandybridge_finalize_smm(void) +void intel_nehalem_finalize_smm(void) { pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index 73137b2..d79b0b7 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -588,7 +588,7 @@ struct ied_header { #define PCI_DEVICE_ID_IB 0x0154 #ifdef __SMM__ -void intel_sandybridge_finalize_smm(void); +void intel_nehalem_finalize_smm(void); #else /* !__SMM__ */ int bridge_silicon_revision(void); void nehalem_early_initialization(int chipset_type);

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coreboot-gerrit January 2015