coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

1 participants
1236 discussions

Patch set updated for coreboot: e70e150 Get rid of .car.global_data warnings for GCC build
by Martin Roth 30 Jan '15

30 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8301 -gerrit commit e70e15028a8abfa5904677e9db67d058006fb71a Author: Martin Roth <gaumless(a)gmail.com> Date: Thu Jan 22 19:10:10 2015 -0700 Get rid of .car.global_data warnings for GCC build The "used" attribute was added in commit 27cf2472 which caused these warnings to start appearing when using the standard coreboot GCC toolchain: {standard input}: Assembler messages: {standard input}:96: Warning: ignoring changed section type for .car.global_data {standard input}:96: Warning: ignoring changed section attributes for .car.global_data The # at the end of the section name causes the assembler to ignore everything following the name. I verified that the resulting binaries are the same with and without the #. Change-Id: Iaac8042533842ed887f33895f083b613a18f496a Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/arch/x86/include/arch/early_variables.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 2d5ae85..5394af3 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -23,8 +23,12 @@ #ifdef __PRE_RAM__ asm(".section .car.global_data,\"w\",@nobits"); asm(".previous"); +#ifdef __clang__ #define CAR_GLOBAL __attribute__((used,section(".car.global_data"))) #else +#define CAR_GLOBAL __attribute__((used,section(".car.global_data#"))) +#endif /* __clang__ */ +#else #define CAR_GLOBAL #endif

1 0

New patch to review for coreboot: 623af9f lenovo/t530/romstage.c: add usb port description and missing oc config
by Nicolas Reinecke 29 Jan '15

29 Jan '15

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8304 -gerrit commit 623af9f2549007d096988d3a4ef3811c94095028 Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Thu Jan 29 10:07:53 2015 +0100 lenovo/t530/romstage.c: add usb port description and missing oc config OC2 at port 4 was missing. Verified with RCBA dump. Change-Id: Ide5701d53aeee28619204c7ac408662626aa11e4 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/mainboard/lenovo/t530/romstage.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index fbf47ac..f29d375 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -53,20 +53,20 @@ void rcba_config(void) } const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 1, 1 }, - { 1, 2, 3 }, - { 1, 1, -1 }, - { 1, 1, -1 }, - { 1, 0, -1 }, - { 0, 0, -1 }, - { 1, 2, -1 }, - { 1, 0, -1 }, - { 1, 1, 5 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 3, -1 }, - { 1, 1, -1 }, + { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */ + { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */ + { 1, 2, 3 }, /* P2: Dock, USB3, OC 3 */ + { 1, 1, -1 }, /* P3: WWAN slot, no OC */ + { 1, 1, 2 }, /* P4: yellow USB, OC 2 */ + { 1, 0, -1 }, /* P5: ExpressCard slot, no OC */ + { 0, 0, -1 }, /* P6: color sensor(w530), no OC */ + { 1, 2, -1 }, /* P7: docking, no OC */ + { 1, 0, -1 }, /* P8: smart card reader, no OC */ + { 1, 1, 5 }, /* P9: USB port single (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 0, -1 }, /* P11: bluetooth, no OC. */ + { 1, 3, -1 }, /* P12: wlan, no OC - disabled in vendor bios*/ + { 1, 1, -1 }, /* P13: camera, no OC */ }; void mainboard_get_spd(spd_raw_data *spd) {

1 0

New patch to review for coreboot: a36bff5 southbridge/intel/bd82x6x: add option to disable hdmi audio codec
by Nicolas Reinecke 29 Jan '15

29 Jan '15

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8303 -gerrit commit a36bff53e21a89a48a65b77bb3fd428f320b26be Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Thu Jan 29 23:43:06 2015 +0100 southbridge/intel/bd82x6x: add option to disable hdmi audio codec Some Thinkpads like T420s or T520 with discrete GPU have only VGA and LVDS conntected to the IGP. For this devices is it usefull to have an option to disable the audio codec. Change-Id: Iaa60b6d4c3c98ec9616ea0ef43913bbcf0d315da Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/southbridge/intel/bd82x6x/azalia.c | 23 +++++++++++------------ src/southbridge/intel/bd82x6x/chip.h | 2 ++ 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index bef88ab..ff958eb 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -228,6 +228,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask) static void azalia_init(struct device *dev) { + struct southbridge_intel_bd82x6x_config *config = dev->chip_info; u32 base; struct resource *res; u32 codec_mask; @@ -267,22 +268,20 @@ static void azalia_init(struct device *dev) reg32 |= (1 << 31); pci_write_config32(dev, 0x120, reg32); - // Enable HDMI codec: - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 1); - pci_write_config32(dev, 0xc4, reg32); + if (!(config->azalia_hdmi_disable))) { + // Enable HDMI codec: + reg32 = pci_read_config32(dev, 0xc4); + reg32 |= (1 << 1); + pci_write_config32(dev, 0xc4, reg32); - reg8 = pci_read_config8(dev, 0x43); - reg8 |= (1 << 6); - pci_write_config8(dev, 0x43, reg8); + reg8 = pci_read_config8(dev, 0x43); + reg8 |= (1 << 6); + pci_write_config8(dev, 0x43, reg8); + } /* Additional programming steps */ reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 13); - pci_write_config32(dev, 0xc4, reg32); - - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 10); + reg32 |= (1 << 13) | (1 << 10); pci_write_config32(dev, 0xc4, reg32); reg32 = pci_read_config32(dev, 0xd0); diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 290bb05..6182e44 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -89,6 +89,8 @@ struct southbridge_intel_bd82x6x_config { int docking_supported; uint8_t pcie_hotplug_map[8]; + + uint8_t azalia_hdmi_disable; }; #endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */

1 0

Patch set updated for coreboot: 7635e87 FSP & CBMEM: Fix broken cbmem CAR transition.
by Martin Roth 29 Jan '15

29 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8196 -gerrit commit 7635e87bd42316a9ce1327ef86389293f7cdee44 Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jan 11 14:29:29 2015 -0700 FSP & CBMEM: Fix broken cbmem CAR transition. 1) Save the pointer to the FSP HOB list to low memory at address 0x614. This is the same location as CBMEM_RESUME_BACKUP - the two aren't used in the same platform, so overlapping should be OK. I didn't see any documentation that actually said that this location was free to use, and didn't need to be restored after use in S3 resume, but it looks like the DOS boot vector gets loaded juat above this location, so it SHOULD be ok. The alternative is to copy the memory out and store it in cbmem until we're ready to restore it. 2) When a request for the pointer to a CAR variable comes in, pass back the location inside the FSP hob structure. 3) Skip the memcopy of the CAR Data. The CAR variables do not get transitioned back into cbmem, but used out of the HOB structure. 4) Remove the BROKEN_CAR_MIGRATE Kconfig option from the FSP platform. Change-Id: Iaf566dce1b41a3bcb17e4134877f68262b5e113f Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 1 - src/cpu/intel/fsp_model_406dx/Kconfig | 1 - src/cpu/x86/car.c | 23 +++++++++++++++------- src/include/cbmem.h | 1 + .../intel/fsp_rangeley/fsp/chipset_fsp_util.c | 2 ++ .../intel/fsp_sandybridge/fsp/chipset_fsp_util.c | 1 + src/soc/intel/fsp_baytrail/Kconfig | 1 - src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 2 ++ 8 files changed, 22 insertions(+), 10 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index ea99ee0..05bdce4 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -41,7 +41,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER - select BROKEN_CAR_MIGRATE config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index c3acc78..ec4be84 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -36,7 +36,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER - select BROKEN_CAR_MIGRATE choice prompt "Rangeley CPU Stepping" diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index cca9afd..9f1a26e 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -23,6 +23,9 @@ #include <cbmem.h> #include <arch/early_variables.h> +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP) +#include <drivers/intel/fsp/fsp_util.h> +#endif typedef void (* const car_migration_func_t)(void); extern car_migration_func_t _car_migrate_start; @@ -41,10 +44,13 @@ extern char _car_data_end[]; */ static int car_migrated CAR_GLOBAL; - +/** @brief returns pointer to a CAR variable, before or after migration. + * + * @param var pointer to the CAR variable + */ void *car_get_var_ptr(void *var) { - char *migrated_base; + char *migrated_base = NULL; int offset; void * _car_start = &_car_data_start; void * _car_end = &_car_data_end; @@ -61,12 +67,15 @@ void *car_get_var_ptr(void *var) return var; } +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP) + migrated_base=(char *)find_saved_temp_mem( + *(void **)CBMEM_FSP_HOB_PTR); +#else migrated_base = cbmem_find(CBMEM_ID_CAR_GLOBALS); +#endif - if (migrated_base == NULL) { - printk(BIOS_ERR, "CAR: Could not find migration base!\n"); - return var; - } + if (migrated_base == NULL) + die( "CAR: Could not find migration base!\n"); offset = (char *)var - (char *)_car_start; @@ -140,7 +149,7 @@ static void do_car_migrate_hooks(void) void car_migrate_variables(void) { - if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE)) + if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE) && !IS_ENABLED(PLATFORM_USES_FSP)) do_car_migrate_variables(); if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE)) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ca7a5f4..2f86b85 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -40,6 +40,7 @@ */ #define CBMEM_BOOT_MODE 0x610 #define CBMEM_RESUME_BACKUP 0x614 +#define CBMEM_FSP_HOB_PTR 0x614 #define CBMEM_ID_FREESPACE 0x46524545 #define CBMEM_ID_GDT 0x4c474454 diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index ae95087..18c947f 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -167,6 +167,8 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; + if (Status == 0xFFFFFFFF) { soft_reset(); } diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c index a666d70..716873c 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c @@ -107,6 +107,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; if (Status == 0xFFFFFFFF) { hard_reset(); } diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index b05def2..0ebb5c7 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -50,7 +50,6 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS if INCLUDE_MICROCODE_IN_BUILD select CPU_MICROCODE_ADDED_DURING_BUILD if INCLUDE_MICROCODE_IN_BUILD select ROMSTAGE_RTC_INIT - select BROKEN_CAR_MIGRATE config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c6b5f9c..b8c1bf6 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -329,6 +329,8 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; + if (Status == 0xFFFFFFFF) { warm_reset(); }

1 0

Patch set updated for coreboot: 2c1cdba FSP platforms: Clear area in CAR for cbmem
by Martin Roth 29 Jan '15

29 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8195 -gerrit commit 2c1cdba6ac682623e14354e51dea0887571ec124 Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jan 11 14:58:47 2015 -0700 FSP platforms: Clear area in CAR for cbmem cbmem requires that the memory at _car_data_start be cleared or it does not get used. This patch clears the CAR area used by cbmem. Most of the CAR implementations clear the entire area when setting up the CAR area. The FSP loads the entire are with a pattern instead, so the cbmem area needs to be cleared. Change-Id: I829ddc26133353a784dfc01729af9b3bf427e889 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/drivers/intel/fsp/cache_as_ram.inc | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/drivers/intel/fsp/cache_as_ram.inc b/src/drivers/intel/fsp/cache_as_ram.inc index 9e8b2a2..8c04dc7 100644 --- a/src/drivers/intel/fsp/cache_as_ram.inc +++ b/src/drivers/intel/fsp/cache_as_ram.inc @@ -42,6 +42,8 @@ #ifndef CONFIG_CPU_MICROCODE_CBFS_LOC # error "CONFIG_CPU_MICROCODE_CBFS_LOC must be set." #endif +.extern _car_data_start +.extern _car_data_end #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ @@ -95,6 +97,14 @@ CAR_init_done: movl %esp, %ebp pushl %ebx + /* Clear the cbmem CAR memory region. */ + movl $_car_data_start, %edi + movl $_car_data_end, %ecx + sub %edi, %ecx + shr $2, %ecx + xorl %eax, %eax + rep stosl + before_romstage: post_code(0x23)

1 0

Patch merged into coreboot/master: 20c2c4b asus/kfsn4-dre/Kconfig: Enable power on after power fail by default
by gerrit＠coreboot.org 29 Jan '15

29 Jan '15

the following patch was just integrated into master: commit 20c2c4b277e72c279229c1eea19aeaee94ab2ae1 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Jan 28 15:34:29 2015 -0600 asus/kfsn4-dre/Kconfig: Enable power on after power fail by default Change-Id: I655843c78d31cc69a007ddaf9b51cde063c48c79 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8299 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8299 for details. -gerrit

1 0

New patch to review for coreboot: d41f8b8 lenovo/t5x0: Make version look like something thinkpad_acpi would accept
by Nicolas Reinecke 29 Jan '15

29 Jan '15

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8302 -gerrit commit d41f8b8beb8d931e636a704582334e114ec11c56 Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Wed Jan 28 11:38:44 2015 +0100 lenovo/t5x0: Make version look like something thinkpad_acpi would accept thinkpad_acpi checks that BIOS version matches some pattern. Report version in this form. same as http://review.coreboot.org/4650 / 63acd22dc5366c72a7165138f5030df9523824dc Change-Id: I82d7a2b9f2ec56557b3a9c26d1af57ed39e31850 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/mainboard/lenovo/t520/mainboard.c | 13 +++++++++++++ src/mainboard/lenovo/t530/mainboard.c | 13 +++++++++++++ 2 files changed, 26 insertions(+) diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index 582ef81..8419abc 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -37,6 +37,7 @@ #include <cbfs.h> #include <pc80/keyboard.h> #include <ec/lenovo/h8/h8.h> +#include <version.h> void mainboard_suspend_resume(void) { @@ -44,7 +45,19 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } +const char *smbios_mainboard_bios_version(void) +{ + static char *s = NULL; + + /* Satisfy thinkpad_acpi. */ + if (strlen(CONFIG_LOCALVERSION)) + return "CBET4000 " CONFIG_LOCALVERSION; + if (s != NULL) + return s; + s = strconcat("CBET4000 ", coreboot_version); + return s; +} static void mainboard_init(device_t dev) { diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c index 14e1960..072ebe9 100644 --- a/src/mainboard/lenovo/t530/mainboard.c +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -37,6 +37,7 @@ #include <cbfs.h> #include <pc80/keyboard.h> #include <ec/lenovo/h8/h8.h> +#include <version.h> void mainboard_suspend_resume(void) { @@ -44,7 +45,19 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } +const char *smbios_mainboard_bios_version(void) +{ + static char *s = NULL; + + /* Satisfy thinkpad_acpi. */ + if (strlen(CONFIG_LOCALVERSION)) + return "CBET4000 " CONFIG_LOCALVERSION; + if (s != NULL) + return s; + s = strconcat("CBET4000 ", coreboot_version); + return s; +} static void mainboard_init(device_t dev) {

1 0

Patch set updated for coreboot: dd196a5 get rid of .car.global_data warnings for GCC build
by Martin Roth 29 Jan '15

29 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8301 -gerrit commit dd196a564b34628c72210ce768025703b63f893c Author: Martin Roth <gaumless(a)gmail.com> Date: Thu Jan 22 19:10:10 2015 -0700 get rid of .car.global_data warnings for GCC build The "used" attribute was added in commit 27cf2472 which caused these warnings to start appearing when using the standard coreboot GCC toolchain: {standard input}: Assembler messages: {standard input}:96: Warning: ignoring changed section type for .car.global_data {standard input}:96: Warning: ignoring changed section attributes for .car.global_data Change-Id: Iaac8042533842ed887f33895f083b613a18f496a Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/arch/x86/include/arch/early_variables.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 2d5ae85..5394af3 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -23,8 +23,12 @@ #ifdef __PRE_RAM__ asm(".section .car.global_data,\"w\",@nobits"); asm(".previous"); +#ifdef __clang__ #define CAR_GLOBAL __attribute__((used,section(".car.global_data"))) #else +#define CAR_GLOBAL __attribute__((used,section(".car.global_data#"))) +#endif /* __clang__ */ +#else #define CAR_GLOBAL #endif

1 0

Patch set updated for coreboot: 68d36ae FSP & CBMEM: Fix broken cbmem CAR transition.
by Martin Roth 29 Jan '15

29 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8196 -gerrit commit 68d36ae251e187aac023584cc6338fa809de6728 Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jan 11 14:29:29 2015 -0700 FSP & CBMEM: Fix broken cbmem CAR transition. 1) Save the pointer to the FSP HOB list to low memory at address 0x614. This is the same location as CBMEM_RESUME_BACKUP - the two aren't used in the same platform, so overlapping should be OK. I didn't see any documentation that actually said that this location was free to use, and didn't need to be restored after use in S3 resume, but it looks like the DOS boot vector gets loaded juat above this location, so it SHOULD be ok. The alternative is to copy the memory out and store it in cbmem until we're ready to restore it. 2) When a request for the pointer to a CAR variable comes in, pass back the location inside the FSP hob structure. 3) Skip the memcopy of the CAR Data. The CAR variables do not get transitioned back into cbmem, but used out of the HOB structure. 4) Remove the BROKEN_CAR_MIGRATE Kconfig option from the FSP platform. Change-Id: Iaf566dce1b41a3bcb17e4134877f68262b5e113f Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 1 - src/cpu/intel/fsp_model_406dx/Kconfig | 1 - src/cpu/x86/car.c | 37 +++++++++++++++++++--- src/include/cbmem.h | 1 + .../intel/fsp_rangeley/fsp/chipset_fsp_util.c | 2 ++ .../intel/fsp_sandybridge/fsp/chipset_fsp_util.c | 1 + src/soc/intel/fsp_baytrail/Kconfig | 1 - src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 2 ++ 8 files changed, 38 insertions(+), 8 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index ea99ee0..05bdce4 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -41,7 +41,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER - select BROKEN_CAR_MIGRATE config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index c3acc78..ec4be84 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -36,7 +36,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER - select BROKEN_CAR_MIGRATE choice prompt "Rangeley CPU Stepping" diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 81230bd..fd2740c 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -23,6 +23,9 @@ #include <cbmem.h> #include <arch/early_variables.h> +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP) +#include <drivers/intel/fsp/fsp_util.h> +#endif typedef void (* const car_migration_func_t)(void); extern car_migration_func_t _car_migrate_start; @@ -41,13 +44,16 @@ extern char _car_data_end[]; */ static int car_migrated CAR_GLOBAL; - +/** @brief returns pointer to a CAR variable, before or after migration. + * + * @param var pointer to the CAR variable + */ void *car_get_var_ptr(void *var) { - char *migrated_base; - int offset; + char *migrated_base = NULL; void * _car_start = &_car_data_start; void * _car_end = &_car_data_end; + int offset = (char *)var - (char *)_car_start; /* If the cache-as-ram has not been migrated return the pointer * passed in. */ @@ -61,14 +67,33 @@ void *car_get_var_ptr(void *var) return var; } +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP) + /* Before memory is initialized: + * CBMEM_FSP_HOB_PTR == 0xffffffff + * Use CAR by returning the variable passed in. + * + * After memory is initialized, but before the migration: + * CBMEM_FSP_HOB_PTR is a pointer to the start of the FSP HOB list. + * Use saved CAR area in HOB - handled here. + */ + + if (*(uint32_t *)CBMEM_FSP_HOB_PTR != 0xffffffff) { + /* find the saved temp memory so we can recover cbmem */ + migrated_base=(char *)find_saved_temp_mem( + *(void **)CBMEM_FSP_HOB_PTR); + + } + if (migrated_base == NULL) + die("Error: Could not locate Saved CAR memory."); + +#else migrated_base = cbmem_find(CBMEM_ID_CAR_GLOBALS); if (migrated_base == NULL) { printk(BIOS_ERR, "CAR: Could not find migration base!\n"); return var; } - - offset = (char *)var - (char *)_car_start; +#endif return &migrated_base[offset]; } @@ -114,6 +139,7 @@ void clear_car_data_area(void) static void do_car_migrate_variables(void) { +#if !IS_ENABLED(PLATFORM_USES_FSP) void *migrated_base; size_t car_data_size = &_car_data_end[0] - &_car_data_start[0]; @@ -129,6 +155,7 @@ static void do_car_migrate_variables(void) } memcpy(migrated_base, &_car_data_start[0], car_data_size); +#endif /* Mark that the data has been moved. */ car_migrated = ~0; diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ca7a5f4..2f86b85 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -40,6 +40,7 @@ */ #define CBMEM_BOOT_MODE 0x610 #define CBMEM_RESUME_BACKUP 0x614 +#define CBMEM_FSP_HOB_PTR 0x614 #define CBMEM_ID_FREESPACE 0x46524545 #define CBMEM_ID_GDT 0x4c474454 diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index ae95087..18c947f 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -167,6 +167,8 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; + if (Status == 0xFFFFFFFF) { soft_reset(); } diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c index a666d70..716873c 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c @@ -107,6 +107,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; if (Status == 0xFFFFFFFF) { hard_reset(); } diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index b05def2..0ebb5c7 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -50,7 +50,6 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS if INCLUDE_MICROCODE_IN_BUILD select CPU_MICROCODE_ADDED_DURING_BUILD if INCLUDE_MICROCODE_IN_BUILD select ROMSTAGE_RTC_INIT - select BROKEN_CAR_MIGRATE config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c6b5f9c..b8c1bf6 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -329,6 +329,8 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; + if (Status == 0xFFFFFFFF) { warm_reset(); }

1 0

Patch set updated for coreboot: 589d7c8 FSP platforms: Clear area in CAR for cbmem
by Martin Roth 29 Jan '15

29 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8195 -gerrit commit 589d7c83121501ebd926c36ddf08f63d0ac058cc Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jan 11 14:58:47 2015 -0700 FSP platforms: Clear area in CAR for cbmem cbmem requires that the memory at DCACHE_RAM_BASE be cleared or it does not get used. This patch clears CAR used by cbmem. Most of the CAR implementations clear the entire area when setting up the CAR area. The FSP loads the entire are with a pattern instead. Change-Id: I829ddc26133353a784dfc01729af9b3bf427e889 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/arch/x86/include/arch/early_variables.h | 1 + src/cpu/x86/car.c | 7 +++++++ src/mainboard/intel/cougar_canyon2/romstage.c | 4 ++++ src/soc/intel/fsp_baytrail/romstage/romstage.c | 3 +++ src/southbridge/intel/fsp_rangeley/romstage.c | 4 ++++ 5 files changed, 19 insertions(+) diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 2d5ae85..1a11b93 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -61,6 +61,7 @@ static inline void *car_get_var_ptr(void *var) { return var; } #if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_CACHE_AS_RAM) /* Migrate the CAR variables to memory. */ void car_migrate_variables(void); +void clear_car_data_area(void); #else static inline void car_migrate_variables(void) { } #endif diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index cca9afd..81230bd 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -105,6 +105,13 @@ void *car_sync_var_ptr(void *var) return mig_var; } +void clear_car_data_area(void) +{ + size_t car_data_size = &_car_data_end[0] - &_car_data_start[0]; + + memset(&_car_data_start[0], 0, car_data_size); +} + static void do_car_migrate_variables(void) { void *migrated_base; diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 72832ea..6879e14 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -24,6 +24,7 @@ #include <string.h> #include <lib.h> #include <timestamp.h> +#include <arch/early_variables.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/pnp_def.h> @@ -180,6 +181,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) u32 pm1_cnt; u16 pm1_sts; + /* Clear CAR Memory for CBMEM */ + clear_car_data_area(); + post_code(0x40); #if CONFIG_COLLECT_TIMESTAMPS diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index b0b8133..9e86dc3 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -21,6 +21,7 @@ #include <stddef.h> #include <arch/cpu.h> #include <lib.h> +#include <arch/early_variables.h> #include <arch/io.h> #include <arch/cbfs.h> #include <arch/stages.h> @@ -158,6 +159,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) uint32_t fd_mask = 0; uint32_t fd2_mask = 0; + /* Clear CAR Memory for CBMEM */ + clear_car_data_area(); post_code(0x40); program_base_addresses(); diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index fba9eb6..30ac56b 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -22,6 +22,7 @@ #include <string.h> #include <lib.h> #include <timestamp.h> +#include <arch/early_variables.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/pnp_def.h> @@ -44,6 +45,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) uint32_t fd_mask = 0; uint32_t func_dis = DEFAULT_PBASE + PBASE_FUNC_DIS; + /* Clear CAR Memory for CBMEM */ + clear_car_data_area(); + /* * Do not use the Serial Console before it is setup. * This causes the I/O to clog and a side effect is

1 0

← Newer
1
...
5
6
7
8
9
10
11
...
124
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2015