coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 7f3ae39 nvidia/ck804: Enable AMD Family 0Fh/10h dynamic ACPI _PSS objects
by gerrit＠coreboot.org 28 Jan '15

28 Jan '15

the following patch was just integrated into master: commit 7f3ae39640adabbd2288fdeff20b04c55a3a3e9f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jan 27 01:44:37 2015 -0600 nvidia/ck804: Enable AMD Family 0Fh/10h dynamic ACPI _PSS objects Change-Id: I682e6c34d059ae21f9767302659bdfdbea86bcc8 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8285 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8285 for details. -gerrit

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Patch set updated for coreboot: fde8e4f mainboards: Add support for the Asus KFSN4-DRE series of motherboards
by Timothy Pearson 28 Jan '15

28 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8270 -gerrit commit fde8e4ffe2487615ba5a270021d47b2963c19548 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:35:48 2015 -0600 mainboards: Add support for the Asus KFSN4-DRE series of motherboards Status: Tested with KFSN4-DRE PCB v1.04G Booted Ubuntu Linux 14.04 and all onboard peripherals appear to work. Dual Opteron 8347 CPUs tested with 8GB RAM (4GB per bank). Dual Opteron 8356 CPUs tested with 1GB RAM in slot A1. AMD PowerNow! functions correctly via ACPI. Video, network, USB, SATA, and serial have received thorough testing. Tested with KFSN4-DRE PCB v1.05G Single Opteron 2419 CPU tested with 1GB RAM in slot A1. Booted to PXE configuration menu; not tested further. Known issues: RAM initialization is a bit flaky with multiple high-density modules; this could be a generic MCT training issue but is probably bad hardware. The XGI Volari option ROM crashes SeaBIOS v1.7.5, but the video device works after Linux boots and initializes the device. Suspend/resume functions at the S1 level but sometimes hangs on resume. Wake on LAN can be flaky; the strap(s) needed to have WoL work on power application were not physically installed by ASUS so the board needs to boot at least once after power application before it will work. Change-Id: I0709f822eea8ed877f55db9443143028a5400472 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/kfsn4-dre/Kconfig | 108 +++ src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl | 245 +++++++ src/mainboard/asus/kfsn4-dre/acpi_tables.c | 71 ++ src/mainboard/asus/kfsn4-dre/board_info.txt | 5 + src/mainboard/asus/kfsn4-dre/cmos.layout | 118 ++++ src/mainboard/asus/kfsn4-dre/devicetree.cb | 121 ++++ src/mainboard/asus/kfsn4-dre/dsdt.asl | 951 ++++++++++++++++++++++++++ src/mainboard/asus/kfsn4-dre/get_bus_conf.c | 134 ++++ src/mainboard/asus/kfsn4-dre/irq_tables.c | 184 +++++ src/mainboard/asus/kfsn4-dre/mptable.c | 156 +++++ src/mainboard/asus/kfsn4-dre/resourcemap.c | 284 ++++++++ src/mainboard/asus/kfsn4-dre/romstage.c | 394 +++++++++++ src/mainboard/asus/kfsn4-dre/spd_notes.txt | 50 ++ 14 files changed, 2824 insertions(+) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index edd8f5d..9bc4e35 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -33,6 +33,8 @@ config BOARD_ASUS_F2A85_M bool "F2A85-M" config BOARD_ASUS_F2A85_M_LE bool "F2A85-M LE" +config BOARD_ASUS_KFSN4_DRE + bool "KFSN4-DRE" config BOARD_ASUS_K8V_X bool "K8V-X" config BOARD_ASUS_M2N_E @@ -76,6 +78,7 @@ source "src/mainboard/asus/a8v-e_deluxe/Kconfig" source "src/mainboard/asus/f2a85-m/Kconfig" source "src/mainboard/asus/f2a85-m_le/Kconfig" source "src/mainboard/asus/k8v-x/Kconfig" +source "src/mainboard/asus/kfsn4-dre/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig new file mode 100644 index 0000000..07e01fd --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -0,0 +1,108 @@ +if BOARD_ASUS_KFSN4_DRE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_SOCKET_F_1207 + select DIMM_DDR2 + select DIMM_REGISTERED + select NORTHBRIDGE_AMD_AMDFAM10 + select SOUTHBRIDGE_NVIDIA_CK804 + select SUPERIO_WINBOND_W83627THG + select PARALLEL_CPU_INIT + select HAVE_HARD_RESET + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select LIFT_BSP_APIC_ID + select BOARD_ROMSIZE_KB_1024 + select ENABLE_APIC_EXT_ID + select AMDMCT + select MMCONF_SUPPORT_DEFAULT + +config MAINBOARD_DIR + string + default asus/kfsn4-dre + +config DCACHE_RAM_BASE + hex + default 0xc4000 + +config DCACHE_RAM_SIZE + hex + default 0x0c000 + +config APIC_ID_OFFSET + hex + default 0 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "KFSN4-DRE" + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + +config PCI_64BIT_PREF_MEM + bool + default n + +config MAX_CPUS + int + default 8 + +config MAX_PHYSICAL_CPUS + int + default 2 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config IRQ_SLOT_COUNT + int + default 13 + +config AMD_UCODE_PATCH_FILE + string + default "mc_patch_01000095.h" + +config CK804_PCI_E_X + int + default 1 + +config CK804_PCIE_PME_WAKE + bool + default y + +config DRIVERS_PS2_KEYBOARD + bool + default y + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n + +config VGA_BIOS_ID + string + depends on VGA_BIOS + default "18ca:0020" + +config AMDMCT_BACKGROUND_SCRUB_RATE + hex + default 0x06 + +endif # BOARD_ASUS_KFSN4_DRE diff --git a/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl b/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl new file mode 100644 index 0000000..c55835e --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl @@ -0,0 +1,245 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2010 - 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com> + * Copyright (C) 2007, 2008 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * WARNING: Sleep/Wake is a work in progress and is still somewhat flaky! + */ + + /* SuperIO control port */ + Name (SPIO, 0x2E) + + /* SuperIO control map */ + OperationRegion (SPIM, SystemIO, SPIO, 0x02) + Field (SPIM, ByteAcc, NoLock, Preserve) { + INDX, 8, + DATA, 8 + } + + /* SuperIO control registers */ + IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) { + Offset (0x07), + CR07, 8, /* Logical device number */ + Offset (0x2C), + CR2C, 8, /* GPIO3 multiplexed pin selection */ + Offset (0x30), + CR30, 8, /* Logical device activation control register */ + Offset (0xE0), + CRE0, 8, /* Wake control register */ + Offset (0xE6), + CRE6, 8, /* Mouse wake event configuration register */ + Offset (0xF1), + CRF1, 8, /* GPIO3 data register */ + Offset (0xF3), + CRF3, 8, /* SUSLED mode register */ + Offset (0xF6), + CRF6, 8, /* SMI/PME event generation control register */ + Offset (0xF9), + CRF9, 8, /* ACPI PME configuration register */ + } + + /* Southbridge control ports */ + /* Both are offsets from PM base address (0x2000) */ + Name (SBC1, 0x2090) /* Offset 0x90 */ + Name (SBC2, 0x2400) /* Offset 0x400 */ + + /* Southbridge control maps */ + OperationRegion (SBM1, SystemIO, SBC1, 0x10) + Field (SBM1, ByteAcc, NoLock, Preserve) { + S1CT, 2, + Offset (0x04), + S3CT, 2, + Offset (0x08), + S4CT, 2, + Offset (0x0C), + S5CT, 2, + } + OperationRegion (SBM2, SystemIO, SBC2, 0x08) + Field (SBM2, ByteAcc, NoLock, Preserve) { + , 15, + PS1S, 1, + , 31, + PS1E, 1, + } + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* Set up LEDs */ + /* Access SuperIO GPIO3/GPIO4 device */ + Store(0x87, INDX) + Store(0x87, INDX) + Store(0x09, CR07) + + /* Set GPIO3 pin 64 (power LED) to GP37 mode */ + And(CR2C, 0xF3, Local0) + Or(Local0, 0x04, CR2C) + + /* Set power LED to steady on */ + Or(CRF1, 0x80, CRF1) + + /* Restore default SuperIO access */ + Store(0xAA, INDX) + + /* Configure SuperIO for wake */ + /* Access SuperIO ACPI device */ + Store(0x87, INDX) + Store(0x87, INDX) + Store(0x0A, CR07) + + if (LEqual(Arg0, One)) /* Resuming from power state S1 */ + { + /* Set power management to SMI mode and disable SMI events */ + And(CRF9, 0xFA, CRF9) + + /* Deactivate the ACPI device */ + Store(Zero, CR30) + + /* Disable PS/2 SMI/PME events */ + And(CRF6, 0xCF, CRF6) + } + if (Lor(LEqual(Arg0, 0x03), LEqual(Arg0, 0x04))) /* Resuming from power state S3 or S4 */ + { + /* Disable PS/2 wake */ + And(CRE0, 0x1D, CRE0) + And(CRE6, 0x7F, CRE6) + } + + /* Restore default SuperIO access */ + Store(0xAA, INDX) + + /* Configure southbridge for wake */ + Store(Zero, PS1E) + Store(0x02, S1CT) + Store(0x02, S3CT) + Store(0x02, S4CT) + Store(0x02, S5CT) + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + + Return(WKST) + } /* End Method(\_WAK) */ + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(\_PTS, 1) { + /* Set up LEDs */ + if (LEqual(Arg0, One)) /* Power state S1 requested */ + { + /* Access SuperIO GPIO3/GPIO4 device */ + Store(0x87, INDX) + Store(0x87, INDX) + Store(0x09, CR07) + + /* Set GPIO3 pin 64 (power LED) to SUSLED mode */ + And(CR2C, 0xF3, CR2C) + + /* Set suspend LED to 1Hz toggle pulse with 50% duty cycle */ + Or(CRF3, 0x80, CRF3) + + /* Restore default SuperIO access */ + Store(0xAA, INDX) + } + + /* Configure SuperIO for sleep */ + /* Access SuperIO ACPI device */ + Store(0x87, INDX) + Store(0x87, INDX) + Store(0x0A, CR07) + + /* Disable PS/2 wakeup and connect PANSW_IN to PANSW_OUT */ + And(CRE0, 0x1F, CRE0) + + if (LEqual(Arg0, One)) /* Power state S1 requested */ + { + /* Set power management to PME mode and enable PME events */ + Or(CRF9, 0x05, CRF9) + + /* Activate the ACPI device */ + Store(One, CR30) + + /* Enable PS/2 keyboard SMI/PME events */ + And(CRF6, 0xEF, CRF6) + + /* Enable PS/2 keyboard wake */ + Or(CRE0, 0x40, CRE0) + + /* Enable PS/2 mouse SMI/PME events */ + And(CRF6, 0xDF, CRF6) + + /* Enable PS/2 mouse wake */ + Or(CRE0, 0x20, CRE0) + } + else { + /* Enable PS/2 keyboard wake on any keypress */ + Or(CRE0, 0x41, CRE0) + + /* Enable PS/2 mouse wake on any click */ + Or(CRE0, 0x22, CRE0) + Or(CRE6, 0x80, CRE6) + } + + /* Restore default SuperIO access */ + Store(0xAA, INDX) + + /* Configure southbridge for sleep */ + Store(One, PS1S) + Store(One, PS1E) + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + } /* End Method(\_PTS) */ diff --git a/src/mainboard/asus/kfsn4-dre/acpi_tables.c b/src/mainboard/asus/kfsn4-dre/acpi_tables.c new file mode 100644 index 0000000..904ad38 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/acpi_tables.c @@ -0,0 +1,71 @@ +/* + * ACPI support + * written by Stefan Reinauer <stepan(a)openbios.org> + * (C) 2005 Stefan Reinauer + * + * Copyright 2005 AMD + * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + */ + +#include <console/console.h> +#include <string.h> +#include <assert.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam10_sysconf.h> + +/* APIC */ +unsigned long acpi_fill_madt(unsigned long current) +{ + device_t dev; + struct resource *res; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write NVIDIA CK804 IOAPIC. */ + dev = dev_find_slot(0x0, PCI_DEVFN(sysconf.sbdn + 0x1, 0)); + ASSERT(dev != NULL); + + res = find_resource(dev, PCI_BASE_ADDRESS_1); + ASSERT(res != NULL); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, res->base, 0); + + /* Initialize interrupt mapping if mptable.c didn't. */ + if (!IS_ENABLED(CONFIG_GENERATE_MP_TABLE)) { + /* Copied from mptable.c */ + /* Enable interrupts for commonly used devices (USB, SATA, etc.) */ + pci_write_config32(dev, 0x7c, 0x0d800018); + pci_write_config32(dev, 0x80, 0xd8002009); + pci_write_config32(dev, 0x84, 0x00000001); + } + +// /* IRQ of timer (override IRQ0 --> APIC IRQ2) */ +// current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) +// current, 0, 0, 2, 0); + /* IRQ9 */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + /* IRQ14 */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 14, 14, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH); + /* IRQ15 */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 15, 15, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH); + + /* create all subtables for processors */ + /* acpi_create_madt_lapic_nmis returns current, not size. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} diff --git a/src/mainboard/asus/kfsn4-dre/board_info.txt b/src/mainboard/asus/kfsn4-dre/board_info.txt new file mode 100644 index 0000000..788888e --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/board_info.txt @@ -0,0 +1,5 @@ +Category: server +ROM package: PLCC-32 +ROM protocol: LPC +ROM socketed: y +Flashrom support: y \ No newline at end of file diff --git a/src/mainboard/asus/kfsn4-dre/cmos.layout b/src/mainboard/asus/kfsn4-dre/cmos.layout new file mode 100644 index 0000000..3bb6df3 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/cmos.layout @@ -0,0 +1,118 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering +## Copyright (C) 2007 AMD +## Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +446 1 e 1 power_on_after_fail +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/kfsn4-dre/devicetree.cb b/src/mainboard/asus/kfsn4-dre/devicetree.cb new file mode 100644 index 0000000..3e0e41e --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/devicetree.cb @@ -0,0 +1,121 @@ +chip northbridge/amd/amdfam10/root_complex # Root complex + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device domain 0 on # PCI domain + subsystemid 0x1043 0x8162 inherit + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on end # Link 0 == LDT 0 + device pci 18.0 on # Link 1 == LDT 1 [SB on link 1] + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627thg # Super I/O + device pnp 2e.0 on # Floppy + # Set up interface resources + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off end # Parallel port + device pnp 2e.2 on # Com1 + # Set up interface resources + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + # Set up interface resources + io 0x60 = 0x2f8 + irq 0x70 = 3 + # Select correct package I/O pins + io 0xf1 = 0x04 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + # Set up interface resources + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.7 off end # Game port, MIDI, GPIO 1 & 5 + device pnp 2e.8 off end # GPIO 2 + device pnp 2e.9 on end # GPIO 3, GPIO 4 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + # Set up interface resources + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM n-0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM n-0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM n-0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM n-0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM n-1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM n-1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM n-1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM n-1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on end # SM 1 + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 off end # AC'97 Audio (N/A) + device pci 4.1 off end # AC'97 Modem (N/A) + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 0 + device pci 8.0 on end # SATA 1 + device pci 9.0 on # Bridge + device pci 4.0 on end # VGA + end + device pci a.0 off end + device pci b.0 on # Bridge + device pci 0.0 on end # NIC A + end + device pci c.0 on # Bridge + device pci 0.0 on end # LSI SAS + end + device pci d.0 on # Bridge + device pci 0.0 on end # NIC B + end + device pci e.0 on # Bridge + # Slot # PCI E 0 + end + device pci f.0 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end + end + end +end diff --git a/src/mainboard/asus/kfsn4-dre/dsdt.asl b/src/mainboard/asus/kfsn4-dre/dsdt.asl new file mode 100644 index 0000000..9f66ffc --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/dsdt.asl @@ -0,0 +1,951 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2005 - 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com> + * Copyright (C) 2007, 2008 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * WARNING: Sleep/Wake is a work in progress and is still somewhat flaky! + * Everything else does to the best of my knowledge... (T.P. 01/26/2015) + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +/* + * PCI link routing templates taken from ck804.asl and modified for this board + */ + +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "ASUS ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00000001 /* OEM Revision */ + ) +{ + #include "northbridge/amd/amdfam10/amdfam10_util.asl" + + /* Some global data */ + Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PICM, One) /* Assume APIC */ + + /* HPET control */ + Name (SHPB, 0xFED00000) + Name (SHPL, 0x1000) + + /* Define power states */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) /* Normal operation */ + Name (_S1, Package () { 0x01, 0x00, 0x00, 0x00 }) /* Standby */ + /* Name (_S3, Package () { 0x05, 0x00, 0x00, 0x00 }) */ /* Not supported by hardware */ + /* Name (_S4, Package () { 0x06, 0x00, 0x00, 0x00 }) */ + Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 }) /* Hard power off */ + + /* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + Method (_PIC, 1, Serialized) { + Store (Arg0, PICM) + } + + /* _PR CPU0 is dynamically supplied by SSDT */ + /* CPU objects and _PSS entries are dynamically supplied by SSDT */ + + Scope(\_GPE) { /* Start Scope GPE */ + /* VGA controller PME# */ + Method(_L00) { + /* Level-Triggered GPE */ + Notify(\_SB.PCI0.VGAC, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Keyboard controller PME# */ + Method(_L03) { + /* Level-Triggered GPE */ + Notify(\_SB.PCI0.LPC.KBD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.LPC.MOU, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* USB2 PME# */ + Method(_L05) { + /* Level-Triggered GPE */ + Notify (\_SB.PCI0.USB2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Slot PME# */ + Method(_L0B) { + /* Level-Triggered GPE */ + Notify (\_SB.PCI0.PCIE.SLT1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.LSIC.SLT2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* USB0 PME# */ + Method(_L0D) { + /* Level-Triggered GPE */ + Notify (\_SB.PCI0.USB0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Keyboard controller PME# */ + Method(_L10) { + /* Level-Triggered GPE */ + Notify(\_SB.PCI0.LPC.KBD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.LPC.MOU, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* PCIe PME# */ + Method(_L11) { + /* Level-Triggered GPE */ + Notify (\_SB.PCI0.NICB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.PCIE, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.NICA, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.LSIC, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + } /* End Scope GPE */ + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device (CK804) */ + Device (PCI0) + { + /* BUS0 root bus */ + + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00180001) + Name (_UID, 0x00) + + Name (HCIN, 0x00) // HC1 + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + /* Operating System Capabilities Method */ + Method(_OSC,4) + { + /* Let OS control everything */ + Return (Arg3) + } + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + External (CBST) + + /* PCI Routing Tables */ + Name (PR00, Package () { + /* PIC */ + /* ISA Bridge */ + Package (0x04) { 0x0001FFFF, 0x00, LKSM, 0x00 }, + + /* USB */ + Package (0x04) { 0x0002FFFF, 0x00, LUB0, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, LUB2, 0x00 }, + + /* SATA 0 */ + Package (0x04) { 0x0007FFFF, 0x00, LSA0, 0x00 }, + + /* SATA 1 */ + Package (0x04) { 0x0008FFFF, 0x00, LSA1, 0x00 }, + + /* NIC A (Bridge) */ + Package (0x04) { 0x000BFFFF, 0x00, LNKB, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x01, LNKC, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x02, LNKD, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x03, LNKA, 0x00 }, + + /* NIC B (Bridge) */ + Package (0x04) { 0x000CFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x03, LNKD, 0x00 }, + + /* LSI SAS Controller (Bridge) */ + Package (0x04) { 0x000DFFFF, 0x00, LNKD, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x01, LNKA, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x02, LNKB, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x03, LNKC, 0x00 }, + + /* PCI-E Slot (Bridge) */ + Package (0x04) { 0x000EFFFF, 0x00, LNKC, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x01, LNKD, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x02, LNKA, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x03, LNKB, 0x00 }, + }) + + Name (AR00, Package () { + /* APIC */ + /* ISA Bridge */ + Package (0x04) { 0x0001FFFF, 0x00, LKSM, 0x00 }, + + /* USB */ + Package (0x04) { 0x0002FFFF, 0x00, LUB0, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, LUB2, 0x00 }, + + /* SATA 0 */ + Package (0x04) { 0x0007FFFF, 0x00, LSA0, 0x00 }, + + /* SATA 1 */ + Package (0x04) { 0x0008FFFF, 0x00, LSA1, 0x00 }, + + /* NIC A (Bridge) */ + Package (0x04) { 0x000BFFFF, 0x00, LNIB, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x01, LNIC, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x02, LNND, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x03, LNIA, 0x00 }, + + /* NIC B (Bridge) */ + Package (0x04) { 0x000CFFFF, 0x00, LNIA, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x01, LNIB, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x02, LNIC, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x03, LNND, 0x00 }, + + /* LSI SAS Controller (Bridge) */ + Package (0x04) { 0x000DFFFF, 0x00, LNND, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x01, LNIA, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x02, LNIB, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x03, LNIC, 0x00 }, + + /* PCI-E Slot (Bridge) */ + Package (0x04) { 0x000EFFFF, 0x00, LNIC, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x01, LNND, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x02, LNIA, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x03, LNIB, 0x00 }, + }) + + Name (PR01, Package () { + /* PIC */ + Package (0x04) { 0x0004FFFF, 0x00, LNKA, 0x00 }, + }) + + Name (AR01, Package () { + /* APIC */ + Package (0x04) { 0x0004FFFF, 0x00, LNIA, 0x00 }, + }) + + Name (PR02, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKD, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKA, 0x00 }, + }) + + Name (AR02, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, LNIB, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNIC, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNND, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNIA, 0x00 }, + }) + + Name (PR03, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, + }) + + Name (AR03, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, LNIA, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNIB, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNIC, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNND, 0x00 }, + }) + + Name (PR04, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKD, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKC, 0x00 }, + }) + + Name (AR04, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, LNND, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNIA, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNIB, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNIC, 0x00 }, + }) + + Name (PR05, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKD, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKB, 0x00 }, + }) + + Name (AR05, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, LNIC, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNND, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNIA, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNIB, 0x00 }, + }) + + /* PCI Resource Tables */ + + Name (RSIA, ResourceTemplate () { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) {8} + }) + + Name (RSMA, ResourceTemplate () { + /* APIC */ + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {16} + }) + + Name (RSIB, ResourceTemplate () { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) {1} + }) + + Name (RSMB, ResourceTemplate () { + /* APIC */ + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {17} + }) + + Name (RSIC, ResourceTemplate () { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) {2} + }) + + Name (RSMC, ResourceTemplate () { + /* APIC */ + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {18} + }) + + Name (RSND, ResourceTemplate () { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) {13} + }) + + Name (RSMD, ResourceTemplate () { + /* APIC */ + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {19} + }) + + Name (RSS2, ResourceTemplate () + { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) + {3, 4, 5, 7, 9, 10, 11, 12, 14, 15} + }) + + Name (RSA1, ResourceTemplate () + { + /* APIC */ + IRQ (Level, ActiveLow, Shared, ) + {3, 4, 5, 6, 7, 10, 11, 12, 14, 15} + }) + + Method (_CRS, 0, Serialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods below use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + +#include "southbridge/nvidia/ck804/acpi/ck804.asl" + + /* PCI Routing Table Access */ + Method (_PRT, 0, NotSerialized) { + If (PICM) { + Return (AR00) + } Else { + Return (PR00) + } + } + + /* USB0 */ + Device (LUB0) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTQ) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTQ) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (PRSC) + } Else { + Return (RSA1) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSC(\_SB.PCI0.LPCB.INTQ)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTQ)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTQ) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTQ) + } + } + } + + /* USB2 */ + Device (LUB2) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTL) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTL) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (PRSC) + } Else { + Return (RSA1) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSC(\_SB.PCI0.LPCB.INTL)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTL)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTL) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTL) + } + } + } + + /* ISA Bridge */ + Device (LKSM) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x0C) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTK) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTK) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSA1) + } Else { + Return (RSS2) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTK)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTK)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTK) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTK) + } + } + } + + /* Bridge device link (NIC A) */ + Device (LNIA) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTA) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTA) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSMA) + } Else { + Return (RSIA) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTA)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTA)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTA) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTA) + } + } + } + + /* Bridge device link (NIC B) */ + Device (LNIB) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTB) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTB) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSMB) + } Else { + Return (RSIB) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTB)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTB)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTB) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTB) + } + } + } + + /* Bridge device link */ + Device (LNIC) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTC) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTC) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSMC) + } Else { + Return (RSIC) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTC)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTC)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTC) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTC) + } + } + } + + /* Bridge device link */ + Device (LNND) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTD) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTD) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSMD) + } Else { + Return (RSND) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTD)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTD)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTD) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTD) + } + } + } + + /* 0:02.0 CK804 USB 0 */ + Device (USB0) + { + Name (_ADR, 0x00020000) // _ADR: Address + Name(_PRW, Package () {0x0D, 0x04}) // Wake from S1-S4 + } + + /* 0:02.0 CK804 USB 2 */ + Device (USB2) + { + Name (_ADR, 0x00020001) // _ADR: Address + Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 + } + + /* 1:04.0 VGA Controller */ + Device (VGAC) + { + Name (_ADR, 0x00090000) // _ADR: Address + Name(_PRW, Package () {0x00, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR01) + } Else { + Return (PR01) + } + } + } + + /* 2:00.0 PCIe NIC A */ + Device (NICA) + { + Name (_ADR, 0x000B0000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR02) + } Else { + Return (PR02) + } + } + Device (BDC1) + { + Name (_ADR, Zero) // _ADR: Address + } + } + + /* 3:00.0 PCIe NIC B */ + Device (NICB) + { + Name (_ADR, 0x000C0000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR03) + } Else { + Return (PR03) + } + } + Device (BDC2) + { + Name (_ADR, Zero) // _ADR: Address + } + } + + /* 4:00.0 PCIe LSI SAS Controller */ + Device (LSIC) + { + Name (_ADR, 0x000D0000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR04) + } Else { + Return (PR04) + } + } + + Device (SLT2) + { + Name (_ADR, 0xFFFF) // _ADR: Address + Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 + } + } + + /* 5:00.0 PCIe x16 */ + Device (PCIE) + { + Name (_ADR, 0x000E0000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR05) + } Else { + Return (PR05) + } + } + Device (SLT1) + { + Name (_ADR, 0xFFFF) // _ADR: Address + Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 + } + } + + Device (LPC) { + Name (_HID, EisaId ("PNP0A05")) + Name (_ADR, 0x00010000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Name (_CID, EisaId ("PNP030B")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, Serialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F03")) + Name (_CID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, Serialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + + /* UART 1 */ + Device (URT1) + { + Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART + Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4 + Method (_STA, 0, NotSerialized) + { + Return (0x0f) // Always enable + } + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + } EndDependentFn() + }) + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + }) + } + } + + /* UART 2 */ + Device (URT2) + { + Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART + Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4 + Method (_STA, 0, NotSerialized) + { + Return (0x0f) // Always enable + } + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + }) + } + } + + /* Floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, Serialized) + { + Name (BUF0, ResourceTemplate () { + FixedIO (0x03F0, 0x08) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + Device (HPET) + { + Name (_HID, EisaId ("PNP0103")) + Name (CRS, ResourceTemplate () + { + Memory32Fixed (ReadOnly, + 0x00000000, + 0x00001000, + _Y02) + IRQNoFlags () {0} + IRQNoFlags () {8} + }) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._BAS, HPT1) + CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._LEN, HPT2) + Store (SHPB, HPT1) + Store (SHPL, HPT2) + Return (CRS) + } + + } + } + } + + Device (PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } + +#include "acpi/pm_ctrl.asl" + +} diff --git a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c new file mode 100644 index 0000000..9d20d76 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#include <stdlib.h> +#if CONFIG_LOGICAL_CPUS +#include <cpu/amd/multicore.h> +#endif +#include <cpu/amd/amdfam10_sysconf.h> +#include <stdlib.h> + +/* + * Global variables for MB layouts and these will be shared by irqtable, + * mptable and acpi_tables. + */ +/* busnum is default */ +unsigned char bus_ck804[6]; +unsigned apicid_ck804; + +/* Here you only need to set value in pci1234 for HT-IO that could be +installed or not You may need to preset pci1234 for HTIO board, please +refer to src/northbridge/amd/amdfam10/get_pci1234.c for detail */ +static u32 pci1234x[] = { + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, + }; + + +/* HT Chain device num, actually it is unit id base of every ht device +in chain, assume every chain only have 4 ht device at most */ + +static unsigned hcdnx[] = { + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, +}; + +extern void get_pci1234(void); + +static unsigned get_bus_conf_done = 0; + +void get_bus_conf(void) +{ + unsigned apicid_base, sbdn; + device_t dev; + int i; + + if (get_bus_conf_done == 1) + return; /* Do it only once. */ + + get_bus_conf_done = 1; + + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_pci1234(); + + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sbdn = sysconf.sbdn; + + for (i = 0; i < 6; i++) + bus_ck804[i] = 0; + + /* CK804 */ + dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x09, 0)); + if (dev) { + bus_ck804[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804[2]++; + } else { + printk + (BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x09); + bus_ck804[1] = 2; + bus_ck804[2] = 3; + } + + for (i = 2; i < 6; i++) { + dev = dev_find_slot(bus_ck804[0], + PCI_DEVFN(sbdn + 0x0b + i - 2, 0)); + if (dev) { + bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_ck804[0], sbdn + 0x0b + i - 2); + } + } + + if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { + apicid_base = get_apicid_base(1); + printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==1: apicid_base: %08x\n", apicid_base); + } + else { + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==0: apicid_base: %08x\n", apicid_base); + } + apicid_ck804 = apicid_base + 0; +} diff --git a/src/mainboard/asus/kfsn4-dre/irq_tables.c b/src/mainboard/asus/kfsn4-dre/irq_tables.c new file mode 100644 index 0000000..437961c --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/irq_tables.c @@ -0,0 +1,184 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// WARNING +// These tables are INVALID for this mainboard! +// The ACPI tables are correct; a backport to these PIR tables is needed... + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam10_sysconf.h> + +extern unsigned char bus_isa; +extern unsigned char bus_ck804[6]; + + +/** + * Add one line to IRQ table. + */ +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, + uint8_t devfn, uint8_t link0, uint16_t bitmap0, + uint8_t link1, uint16_t bitmap1, uint8_t link2, + uint16_t bitmap2, uint8_t link3, uint16_t bitmap3, + uint8_t slot, uint8_t rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +/** + * Create the IRQ routing table. + * Values are derived from getpir generated code. + */ +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + unsigned slot_num, sbdn; + uint8_t *v, sum = 0; + int i; + + /* get_bus_conf() will find out all bus num and APIC that share with + * mptable.c and mptable.c. + */ + get_bus_conf(); + sbdn = sysconf.sbdn; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000. */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (uint8_t *)(addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + pirq->rtr_bus = bus_ck804[0]; + pirq->rtr_devfn = ((sbdn + 9) << 3) | 0; + pirq->exclusive_irqs = 0x828; + pirq->rtr_vendor = 0x10de; + pirq->rtr_device = 0x005c; + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* Slot1 PCIE 16x */ + write_pirq_info(pirq_info, bus_ck804[1], (0 << 3) | 0, 0x3, 0xdeb8, 0x4, + 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0); + pirq_info++; + slot_num++; + + + /* Slot2 PCIE 1x */ + write_pirq_info(pirq_info, bus_ck804[2], (0 << 3) | 0, 0x4, 0xdeb8, 0x1, + 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 5, 0); + pirq_info++; + slot_num++; + + /* Slot3 PCIE 1x */ + write_pirq_info(pirq_info, bus_ck804[3], (0 << 3) | 0, 0x1, 0xdeb8, 0x2, + 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 6, 0); + pirq_info++; + slot_num++; + + /* Slot4 PCIE 4x */ + write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0, 0x2, + 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 7, 0); + pirq_info++; + slot_num++; + + /* Slot5 - Slot7 PCI */ + for (i = 0; i < 3; i++) { + write_pirq_info(pirq_info, bus_ck804[5], (0 << (6 + i)) | 0, + ((i + 0) % 4) + 1, 0xdeb8, + ((i + 1) % 4) + 1, 0xdeb8, + ((i + 2) % 4) + 1, 0xdeb8, + ((i + 3) % 4) + 1, 0xdeb8, i, 0); + pirq_info++; + slot_num++; + } + + /* PCI bridge */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 9) << 3) | 0, 0x1, + 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0, 0); + pirq_info++; + slot_num++; + + /* SMBus */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 1) << 3) | 0, 0x2, + 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + /* USB */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 2) << 3) | 0, 0x1, + 0xdeb8, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + /* SATA */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 7) << 3) | 0, 0x1, + 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + /* SATA */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 8) << 3) | 0, 0x1, + 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + if (sum != pirq->checksum) + pirq->checksum = sum; + + printk(BIOS_INFO, "done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/asus/kfsn4-dre/mptable.c b/src/mainboard/asus/kfsn4-dre/mptable.c new file mode 100644 index 0000000..46ae594 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/mptable.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// WARNING +// These tables are INCOMPLETE for this mainboard! +// The ACPI tables are correct; a backport to these MP tables is needed... + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam10_sysconf.h> + +extern unsigned char bus_ck804[6]; +extern unsigned apicid_ck804; + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + unsigned sbdn; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + smp_write_processors(mc); + + get_bus_conf(); + sbdn = sysconf.sbdn; + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + { + device_t dev; + struct resource *res; + + dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_1); + if (res) { + smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); + } + + /* Initialize interrupt mapping. */ + + /* + LPC bridge PCI config registers: + + 0x7c:0x0000ffff + - bitmap of masked pci irqs? + - PIRQ[ABCD] possibly? + + 0x7c:0x00f00000 + - sata at f8 - port 1 + + 0x7c:0x0f000000 + - sata at f7 - port 1 + + 0x80:0xf0000000 + - sata at f7 - port 0 + + 0x80:0x0f000000 + - sata at f8 - port 0 + + 0x80:0x0000f000 + - EHCI + + 0x84:0x00000f00 + - NIC + + 0x84:0x0000000f + - OHCI + + known values of nibbles: + + 0 - unrouted? + 1 - irq 23 + 8 - irq 20 + c - irq 12 + d - irq 21 + e - irq 14 + f - irq 15 + */ + + // Enable interrupts for commonly used devices (USB, SATA, etc.) + pci_write_config32(dev, 0x7c, 0x0d800018); + pci_write_config32(dev, 0x80, 0xd8002009); + pci_write_config32(dev, 0x84, 0x00000001); + } + } + + mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0); + + // Onboard ck804 smbus + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804, + 0xa); + + // Onboard ck804 USB 1.1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804, + 0x15); + + // Onboard ck804 USB 2 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804, + 0x14); + + // Onboard ck804 SATA 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804, + 0x17); + + // Onboard ck804 SATA 1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804, + 0x16); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + mptable_lintsrc(mc, bus_ck804[0]); + + /* There is no extension information... */ + + /* Compute the checksums. */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/kfsn4-dre/resourcemap.c b/src/mainboard/asus/kfsn4-dre/resourcemap.c new file mode 100644 index 0000000..5ba0b01 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/resourcemap.c @@ -0,0 +1,284 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static void setup_mb_resource_map(void) +{ + static const unsigned int register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [31:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000, + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000, + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> Nvidia CK 804 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independent of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration region i + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> Nvidia CK 804 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + + }; + + int max; + max = ARRAY_SIZE(register_values); + setup_resource_map(register_values, max); +} diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c new file mode 100644 index 0000000..cd8b9de --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -0,0 +1,394 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define FAM10_SCAN_PCI_BUS 0 +#define FAM10_ALLOCATE_IO_RANGE 1 + +unsigned int get_sbdn(unsigned bus); + +#include <stdint.h> +#include <string.h> +#include <reset.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <lib.h> +#include <spd.h> +#include <cpu/amd/model_10xxx_rev.h> +#include "southbridge/nvidia/ck804/early_smbus.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> +#include "lib/delay.c" +#include <cpu/x86/lapic.h> +#include "northbridge/amd/amdfam10/reset_test.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627thg/w83627thg.h> +#include <cpu/x86/bist.h> +// #include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdfam10/debug.c" +#include "northbridge/amd/amdfam10/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) + +static void activate_spd_rom(const struct mem_controller *ctrl); + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include <northbridge/amd/amdfam10/amdfam10.h> +#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" +#include "northbridge/amd/amdfam10/pci.c" +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" + +/* + * Avoid crash (complete with severe memory corruption!) during initial CAR boot + * in ck804_early_setup_x(). + * Interestingly once the system is fully booted into Linux this can be set, but + * not before! Apparently something isn't initialized but the amount of effort + * required to fix this is non-negligible and of unknown real-world benefit + */ +#define CK804_SKIP_PCI_REG_78_INIT 1 + +#define CK804_MB_SETUP \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/ + +#include <southbridge/nvidia/ck804/early_setup_ss.h> +#include "southbridge/nvidia/ck804/early_setup_car.c" +#include <cpu/amd/microcode.h> + +#include "cpu/amd/model_10xxx/init_cpus.c" +#include "northbridge/amd/amdfam10/early_ht.c" + +#define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3) + +/** + * @brief Get SouthBridge device number + * @param[in] bus target bus number + * @return southbridge device number + */ +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus); + return (dev >> 15) & 0x1f; +} + +/* + * ASUS KFSN4-DRE specific SPD enable/disable magic. + * + * Setting CK804 GPIO43 and GPIO44 to 0 and 0 respectively will make the + * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD + * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which + * will make RAM init fail. + * + * Disable SPD access after RAM init to allow access to standard SMBus/I2C offsets + * which is required e.g. by lm-sensors. + */ + +#define CK804_BOARD_BOOT_BASE_UNIT_UID 1 + +static const unsigned int ctrl_conf_enable_spd_node0[] = { + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/ +}; + +static const unsigned int ctrl_conf_enable_spd_node1[] = { + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x01),/* W3,GPIO44, U6 input S1*/ +}; + +static const unsigned int ctrl_conf_disable_spd[] = { + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x01),/* W2,GPIO43, U6 input S0*/ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/ +}; + +static const unsigned int ctrl_conf_fix_pci_numbering[] = { + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x44), ~(0x00010000), 0x00000000, /* Force CK804 to start its internal device numbering (Base Unit ID) at 0 instead of the power-on default of 1 */ +}; + +static const unsigned int ctrl_conf_enable_msi_mapping[] = { + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */ +}; + +static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id) +{ + unsigned busn[4], io_base[4]; + int i, ck804_num = 0; + + for (i = 0; i < 4; i++) { + u32 id; + device_t dev; + if (i == 0) /* SB chain */ + dev = PCI_DEV(i * 0x40, bus_unit_id, 0); + else + dev = 0; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (id == 0x005e10de) { + busn[ck804_num] = i * 0x40; + io_base[ck804_num] = i * 0x4000; + ck804_num++; + } + } + + if (ck804_num < 1) + printk(BIOS_WARNING, "CK804 not found at device base unit id %02x!\n", bus_unit_id); + + ck804_early_set_port(ck804_num, busn, io_base); + + setup_resource_map_x_offset(values, + size, + PCI_DEV(0, bus_unit_id, 0), io_base[0]); + + ck804_early_clear_port(ck804_num, busn, io_base); +} + +static void sio_setup(void) +{ + u32 dword; + u8 byte; + + /* Subject decoding */ + byte = pci_read_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b, byte); + + /* LPC Positive Decode 0 */ + dword = pci_read_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0); + /* Serial 0, Serial 1 */ + dword |= (1 << 0) | (1 << 1); + pci_write_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0, dword); +} + +static const uint8_t spd_addr[] = { + // Node 0 + RC00, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, + // Node 1 + RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, +}; + +static void activate_spd_rom(const struct mem_controller *ctrl) { + printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); + if (ctrl->node_id == 0) { + printk(BIOS_DEBUG, "enable_spd_node0()\n"); + ck804_control(ctrl_conf_enable_spd_node0, ARRAY_SIZE(ctrl_conf_enable_spd_node0), CK804_DEVN_BASE); + } + else if (ctrl->node_id == 1) { + printk(BIOS_DEBUG, "enable_spd_node1()\n"); + ck804_control(ctrl_conf_enable_spd_node1, ARRAY_SIZE(ctrl_conf_enable_spd_node1), CK804_DEVN_BASE); + } +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + struct sys_info *sysinfo = &sysinfo_car; + + u32 bsp_apicid = 0, val, wants_reset; + msr_t msr; + + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + set_bsp_node_CHtExtNodeCfgEn(); + enumerate_ht_chain(); + sio_setup(); + } + + post_code(0x30); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + post_code(0x32); + + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + if (CONFIG_MAX_PHYSICAL_CPUS != 2) + printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket board!\n", CONFIG_MAX_PHYSICAL_CPUS); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + /* Setup sysinfo defaults */ + set_sysinfo_in_ram(0); + + update_microcode(val); + + post_code(0x33); + + cpuSetAMDMSR(); + post_code(0x34); + + amd_ht_init(sysinfo); + post_code(0x35); + + /* Setup nodes PCI space and start core 0 AP init. */ + finalize_node_setup(sysinfo); + + /* Setup any mainboard PCI settings etc. */ + setup_mb_resource_map(); + post_code(0x36); + + /* wait for all the APs core0 started by finalize_node_setup. */ + /* FIXME: A bunch of cores are going to start output to serial at once. + * It would be nice to fix up prink spinlocks for ROM XIP mode. + * I think it could be done by putting the spinlock flag in the cache + * of the BSP located right after sysinfo. + */ + wait_all_core0_started(); + + if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); + start_other_cores(); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + } + + printk(BIOS_DEBUG, "set_ck804_base_unit_id()\n"); + ck804_control(ctrl_conf_fix_pci_numbering, ARRAY_SIZE(ctrl_conf_fix_pci_numbering), CK804_BOARD_BOOT_BASE_UNIT_UID); + + post_code(0x38); + + if (IS_ENABLED(CONFIG_SET_FIDVID)) { + msr = rdmsr(0xc0010071); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); + + post_code(0x39); + + if (!warm_reset_detect(0)) { // BSP is node 0 + init_fidvid_bsp(bsp_apicid, sysinfo->nodes); + } else { + init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + } + + post_code(0x3A); + + /* show final fid and vid */ + msr=rdmsr(0xc0010071); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); + } + + init_timer(); // Need to use TMICT to synconize FID/VID + + wants_reset = ck804_early_setup_x(); + + /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ + if (!warm_reset_detect(0)) { + printk(BIOS_INFO, "...WARM RESET...\n\n\n"); + soft_reset(); + die("After soft_reset_x - shouldn't see this message!!!\n"); + } + + if (wants_reset) { + printk(BIOS_DEBUG, "ck804_early_setup_x wanted additional reset!\n"); + } + + post_code(0x3B); + + /* It's the time to set ctrl in sysinfo now; */ + printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + post_code(0x3D); + + printk(BIOS_DEBUG, "enable_smbus()\n"); + enable_smbus(); + +#if 0 + /* FIXME + * After the AMD K10 code has been converted to use + * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block + */ + if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) { + dump_spd_registers(&cpu[0]); + dump_smbus_registers(); + } +#endif + + post_code(0x40); + + printk(BIOS_DEBUG, "raminit_amdmct()\n"); + raminit_amdmct(sysinfo); + post_code(0x41); + + printk(BIOS_DEBUG, "disable_spd()\n"); + ck804_control(ctrl_conf_disable_spd, ARRAY_SIZE(ctrl_conf_disable_spd), CK804_DEVN_BASE); + + printk(BIOS_DEBUG, "enable_msi_mapping()\n"); + ck804_control(ctrl_conf_enable_msi_mapping, ARRAY_SIZE(ctrl_conf_enable_msi_mapping), CK804_DEVN_BASE); + + /* Initialize GPIO */ + /* Access SuperIO GPI03 logical device */ + uint16_t port = GPIO3_DEV >> 8; + outb(0x87, port); + outb(0x87, port); + pnp_set_logical_device(GPIO3_DEV); + /* Set GP37 (power LED) to output */ + pnp_write_config(GPIO3_DEV, 0xf0, 0x7f); + /* Set GP37 (power LED) on */ + pnp_write_config(GPIO3_DEV, 0xf1, 0x80); + /* Set pin 64 multiplex to GP37 */ + uint8_t cr2c = pnp_read_config(GPIO3_DEV, 0x2c); + pnp_write_config(GPIO3_DEV, 0x2c, (cr2c & 0xf3) | 0x04); + /* Restore default SuperIO access */ + outb(0xaa, port); + + post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. + post_code(0x43); // Should never see this post code. +} + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + return 0; +} diff --git a/src/mainboard/asus/kfsn4-dre/spd_notes.txt b/src/mainboard/asus/kfsn4-dre/spd_notes.txt new file mode 100644 index 0000000..ff49c18 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/spd_notes.txt @@ -0,0 +1,50 @@ +==================================================================================================== +SPD mux +==================================================================================================== + +DIMM_A1 SDA signal traced to U6 pin 1 +Destructive testing of failed board (removal of U7 northbridge!) yielded the following information: +U6 S0 <--> U7 W2 +U6 S1 <--> U7 W3 + +Proprietary BIOS enables the SPD during POST with: +S0: LOW +S1: LOW + +then temporarily switches to: +S0: LOW +S1: HIGH + +then switches to runtime mode with: +S0: HIGH +S1: LOW + +After probing with a custom GPIO-flipping tool under Linux the following GPIO mappings were found: +CK804 pin W2 <--> GPIO43 +CK804 pin W3 <--> GPIO44 + +==================================================================================================== +Other hardware +==================================================================================================== + +Power LED (-) is connected to U15 (SuperIO) pin 64 via U4 pins 5,6 and a small MOSFET +ID LED (-) is connected to a ??? via U4 pins 1,2,3,4 and U77 pins 5,6 +It appears that setting U15 (SuperIO) pin 88 LOW will override the ID LED and force it ON + +PCIe slot WAKE# connects to U7 pin E23 (PCIE_WAKE#) + +CPU_WARN1 is driven by (???) via a simple buffer (U13 pin 10) +MEM_WARN1 is driven by U7 pin AD3 (CPUVDD_EN) via a simple buffer (U101 pin 3) + +U7 pin AK3 is disconnected (routed to unpopulated capacitor/resistor) +PU1 pin 37 (VDDPWRGD) drives U7 pin AJ4 (CPU_VLD) +A small MOSFET directly above another small MOSFET directly above the right-hand edge of the PCIe slot drives U7 pin AK5 (HT_VLD) + +When > Barcelona CPU installed on PCB rev 1.04G: +U7 pin AK4 (MEM_VLD): HIGH +PU1 pin 37: LOW +U7 pin AK5: LOW + +HyperTransport 1.2V supply appears to be generated by a linear regulator containing Q191 and downconverting the CK804 1.5V supply +The enable pin appears to be tied to AUX_PANEL pin 1 (+5VSB) via a resistor +Through two MOSFETs the HT supply enable pin is tied to U7 pin AE3 (HTVDD_EN)

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Patch set updated for coreboot: ce86079 mainboards: Add support for the Asus KFSN4-DRE series of motherboards
by Timothy Pearson 28 Jan '15

28 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8270 -gerrit commit ce86079ac4a03115cae0f3957ce82e2a84fec6d6 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:35:48 2015 -0600 mainboards: Add support for the Asus KFSN4-DRE series of motherboards Status: Tested with KFSN4-DRE PCB v1.04G Booted Ubuntu Linux 14.04 and all onboard peripherals appear to work. Dual Opteron 8347 CPUs tested with 8GB RAM (4GB per bank). Dual Opteron 8356 CPUs tested with 1GB RAM in slot A1. AMD PowerNow! functions correctly via ACPI. Video, network, USB, SATA, and serial have received thorough testing. Tested with KFSN4-DRE PCB v1.05G Single Opteron 2419 CPU tested with 1GB RAM in slot A1. Booted to PXE configuration menu; not tested further. Known issues: RAM initialization is a bit flaky with multiple high-density modules; this could be a generic MCT training issue but is probably bad hardware. The XGI Volari option ROM crashes SeaBIOS v1.7.5, but the video device works after Linux boots and initializes the device. Suspend/resume functions at the S1 level but sometimes hangs on resume. Wake on LAN can be flaky; the strap(s) needed to have WoL work on power application were not physically installed by ASUS so the board needs to boot at least once after power application before it will work. Change-Id: I0709f822eea8ed877f55db9443143028a5400472 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/kfsn4-dre/Kconfig | 108 +++ src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl | 245 +++++++ src/mainboard/asus/kfsn4-dre/acpi_tables.c | 71 ++ src/mainboard/asus/kfsn4-dre/board_info.txt | 5 + src/mainboard/asus/kfsn4-dre/cmos.layout | 118 ++++ src/mainboard/asus/kfsn4-dre/devicetree.cb | 121 ++++ src/mainboard/asus/kfsn4-dre/dsdt.asl | 951 ++++++++++++++++++++++++++ src/mainboard/asus/kfsn4-dre/get_bus_conf.c | 134 ++++ src/mainboard/asus/kfsn4-dre/irq_tables.c | 184 +++++ src/mainboard/asus/kfsn4-dre/mptable.c | 156 +++++ src/mainboard/asus/kfsn4-dre/resourcemap.c | 284 ++++++++ src/mainboard/asus/kfsn4-dre/romstage.c | 394 +++++++++++ src/mainboard/asus/kfsn4-dre/spd_notes.txt | 50 ++ 14 files changed, 2824 insertions(+) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index edd8f5d..9bc4e35 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -33,6 +33,8 @@ config BOARD_ASUS_F2A85_M bool "F2A85-M" config BOARD_ASUS_F2A85_M_LE bool "F2A85-M LE" +config BOARD_ASUS_KFSN4_DRE + bool "KFSN4-DRE" config BOARD_ASUS_K8V_X bool "K8V-X" config BOARD_ASUS_M2N_E @@ -76,6 +78,7 @@ source "src/mainboard/asus/a8v-e_deluxe/Kconfig" source "src/mainboard/asus/f2a85-m/Kconfig" source "src/mainboard/asus/f2a85-m_le/Kconfig" source "src/mainboard/asus/k8v-x/Kconfig" +source "src/mainboard/asus/kfsn4-dre/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig new file mode 100644 index 0000000..07e01fd --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -0,0 +1,108 @@ +if BOARD_ASUS_KFSN4_DRE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_SOCKET_F_1207 + select DIMM_DDR2 + select DIMM_REGISTERED + select NORTHBRIDGE_AMD_AMDFAM10 + select SOUTHBRIDGE_NVIDIA_CK804 + select SUPERIO_WINBOND_W83627THG + select PARALLEL_CPU_INIT + select HAVE_HARD_RESET + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select LIFT_BSP_APIC_ID + select BOARD_ROMSIZE_KB_1024 + select ENABLE_APIC_EXT_ID + select AMDMCT + select MMCONF_SUPPORT_DEFAULT + +config MAINBOARD_DIR + string + default asus/kfsn4-dre + +config DCACHE_RAM_BASE + hex + default 0xc4000 + +config DCACHE_RAM_SIZE + hex + default 0x0c000 + +config APIC_ID_OFFSET + hex + default 0 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "KFSN4-DRE" + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + +config PCI_64BIT_PREF_MEM + bool + default n + +config MAX_CPUS + int + default 8 + +config MAX_PHYSICAL_CPUS + int + default 2 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config IRQ_SLOT_COUNT + int + default 13 + +config AMD_UCODE_PATCH_FILE + string + default "mc_patch_01000095.h" + +config CK804_PCI_E_X + int + default 1 + +config CK804_PCIE_PME_WAKE + bool + default y + +config DRIVERS_PS2_KEYBOARD + bool + default y + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n + +config VGA_BIOS_ID + string + depends on VGA_BIOS + default "18ca:0020" + +config AMDMCT_BACKGROUND_SCRUB_RATE + hex + default 0x06 + +endif # BOARD_ASUS_KFSN4_DRE diff --git a/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl b/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl new file mode 100644 index 0000000..c55835e --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl @@ -0,0 +1,245 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2010 - 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com> + * Copyright (C) 2007, 2008 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * WARNING: Sleep/Wake is a work in progress and is still somewhat flaky! + */ + + /* SuperIO control port */ + Name (SPIO, 0x2E) + + /* SuperIO control map */ + OperationRegion (SPIM, SystemIO, SPIO, 0x02) + Field (SPIM, ByteAcc, NoLock, Preserve) { + INDX, 8, + DATA, 8 + } + + /* SuperIO control registers */ + IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) { + Offset (0x07), + CR07, 8, /* Logical device number */ + Offset (0x2C), + CR2C, 8, /* GPIO3 multiplexed pin selection */ + Offset (0x30), + CR30, 8, /* Logical device activation control register */ + Offset (0xE0), + CRE0, 8, /* Wake control register */ + Offset (0xE6), + CRE6, 8, /* Mouse wake event configuration register */ + Offset (0xF1), + CRF1, 8, /* GPIO3 data register */ + Offset (0xF3), + CRF3, 8, /* SUSLED mode register */ + Offset (0xF6), + CRF6, 8, /* SMI/PME event generation control register */ + Offset (0xF9), + CRF9, 8, /* ACPI PME configuration register */ + } + + /* Southbridge control ports */ + /* Both are offsets from PM base address (0x2000) */ + Name (SBC1, 0x2090) /* Offset 0x90 */ + Name (SBC2, 0x2400) /* Offset 0x400 */ + + /* Southbridge control maps */ + OperationRegion (SBM1, SystemIO, SBC1, 0x10) + Field (SBM1, ByteAcc, NoLock, Preserve) { + S1CT, 2, + Offset (0x04), + S3CT, 2, + Offset (0x08), + S4CT, 2, + Offset (0x0C), + S5CT, 2, + } + OperationRegion (SBM2, SystemIO, SBC2, 0x08) + Field (SBM2, ByteAcc, NoLock, Preserve) { + , 15, + PS1S, 1, + , 31, + PS1E, 1, + } + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* Set up LEDs */ + /* Access SuperIO GPIO3/GPIO4 device */ + Store(0x87, INDX) + Store(0x87, INDX) + Store(0x09, CR07) + + /* Set GPIO3 pin 64 (power LED) to GP37 mode */ + And(CR2C, 0xF3, Local0) + Or(Local0, 0x04, CR2C) + + /* Set power LED to steady on */ + Or(CRF1, 0x80, CRF1) + + /* Restore default SuperIO access */ + Store(0xAA, INDX) + + /* Configure SuperIO for wake */ + /* Access SuperIO ACPI device */ + Store(0x87, INDX) + Store(0x87, INDX) + Store(0x0A, CR07) + + if (LEqual(Arg0, One)) /* Resuming from power state S1 */ + { + /* Set power management to SMI mode and disable SMI events */ + And(CRF9, 0xFA, CRF9) + + /* Deactivate the ACPI device */ + Store(Zero, CR30) + + /* Disable PS/2 SMI/PME events */ + And(CRF6, 0xCF, CRF6) + } + if (Lor(LEqual(Arg0, 0x03), LEqual(Arg0, 0x04))) /* Resuming from power state S3 or S4 */ + { + /* Disable PS/2 wake */ + And(CRE0, 0x1D, CRE0) + And(CRE6, 0x7F, CRE6) + } + + /* Restore default SuperIO access */ + Store(0xAA, INDX) + + /* Configure southbridge for wake */ + Store(Zero, PS1E) + Store(0x02, S1CT) + Store(0x02, S3CT) + Store(0x02, S4CT) + Store(0x02, S5CT) + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + + Return(WKST) + } /* End Method(\_WAK) */ + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(\_PTS, 1) { + /* Set up LEDs */ + if (LEqual(Arg0, One)) /* Power state S1 requested */ + { + /* Access SuperIO GPIO3/GPIO4 device */ + Store(0x87, INDX) + Store(0x87, INDX) + Store(0x09, CR07) + + /* Set GPIO3 pin 64 (power LED) to SUSLED mode */ + And(CR2C, 0xF3, CR2C) + + /* Set suspend LED to 1Hz toggle pulse with 50% duty cycle */ + Or(CRF3, 0x80, CRF3) + + /* Restore default SuperIO access */ + Store(0xAA, INDX) + } + + /* Configure SuperIO for sleep */ + /* Access SuperIO ACPI device */ + Store(0x87, INDX) + Store(0x87, INDX) + Store(0x0A, CR07) + + /* Disable PS/2 wakeup and connect PANSW_IN to PANSW_OUT */ + And(CRE0, 0x1F, CRE0) + + if (LEqual(Arg0, One)) /* Power state S1 requested */ + { + /* Set power management to PME mode and enable PME events */ + Or(CRF9, 0x05, CRF9) + + /* Activate the ACPI device */ + Store(One, CR30) + + /* Enable PS/2 keyboard SMI/PME events */ + And(CRF6, 0xEF, CRF6) + + /* Enable PS/2 keyboard wake */ + Or(CRE0, 0x40, CRE0) + + /* Enable PS/2 mouse SMI/PME events */ + And(CRF6, 0xDF, CRF6) + + /* Enable PS/2 mouse wake */ + Or(CRE0, 0x20, CRE0) + } + else { + /* Enable PS/2 keyboard wake on any keypress */ + Or(CRE0, 0x41, CRE0) + + /* Enable PS/2 mouse wake on any click */ + Or(CRE0, 0x22, CRE0) + Or(CRE6, 0x80, CRE6) + } + + /* Restore default SuperIO access */ + Store(0xAA, INDX) + + /* Configure southbridge for sleep */ + Store(One, PS1S) + Store(One, PS1E) + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + } /* End Method(\_PTS) */ diff --git a/src/mainboard/asus/kfsn4-dre/acpi_tables.c b/src/mainboard/asus/kfsn4-dre/acpi_tables.c new file mode 100644 index 0000000..904ad38 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/acpi_tables.c @@ -0,0 +1,71 @@ +/* + * ACPI support + * written by Stefan Reinauer <stepan(a)openbios.org> + * (C) 2005 Stefan Reinauer + * + * Copyright 2005 AMD + * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + */ + +#include <console/console.h> +#include <string.h> +#include <assert.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam10_sysconf.h> + +/* APIC */ +unsigned long acpi_fill_madt(unsigned long current) +{ + device_t dev; + struct resource *res; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write NVIDIA CK804 IOAPIC. */ + dev = dev_find_slot(0x0, PCI_DEVFN(sysconf.sbdn + 0x1, 0)); + ASSERT(dev != NULL); + + res = find_resource(dev, PCI_BASE_ADDRESS_1); + ASSERT(res != NULL); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, res->base, 0); + + /* Initialize interrupt mapping if mptable.c didn't. */ + if (!IS_ENABLED(CONFIG_GENERATE_MP_TABLE)) { + /* Copied from mptable.c */ + /* Enable interrupts for commonly used devices (USB, SATA, etc.) */ + pci_write_config32(dev, 0x7c, 0x0d800018); + pci_write_config32(dev, 0x80, 0xd8002009); + pci_write_config32(dev, 0x84, 0x00000001); + } + +// /* IRQ of timer (override IRQ0 --> APIC IRQ2) */ +// current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) +// current, 0, 0, 2, 0); + /* IRQ9 */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + /* IRQ14 */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 14, 14, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH); + /* IRQ15 */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 15, 15, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH); + + /* create all subtables for processors */ + /* acpi_create_madt_lapic_nmis returns current, not size. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} diff --git a/src/mainboard/asus/kfsn4-dre/board_info.txt b/src/mainboard/asus/kfsn4-dre/board_info.txt new file mode 100644 index 0000000..788888e --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/board_info.txt @@ -0,0 +1,5 @@ +Category: server +ROM package: PLCC-32 +ROM protocol: LPC +ROM socketed: y +Flashrom support: y \ No newline at end of file diff --git a/src/mainboard/asus/kfsn4-dre/cmos.layout b/src/mainboard/asus/kfsn4-dre/cmos.layout new file mode 100644 index 0000000..3bb6df3 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/cmos.layout @@ -0,0 +1,118 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering +## Copyright (C) 2007 AMD +## Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +446 1 e 1 power_on_after_fail +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/kfsn4-dre/devicetree.cb b/src/mainboard/asus/kfsn4-dre/devicetree.cb new file mode 100644 index 0000000..3e0e41e --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/devicetree.cb @@ -0,0 +1,121 @@ +chip northbridge/amd/amdfam10/root_complex # Root complex + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device domain 0 on # PCI domain + subsystemid 0x1043 0x8162 inherit + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on end # Link 0 == LDT 0 + device pci 18.0 on # Link 1 == LDT 1 [SB on link 1] + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627thg # Super I/O + device pnp 2e.0 on # Floppy + # Set up interface resources + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off end # Parallel port + device pnp 2e.2 on # Com1 + # Set up interface resources + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + # Set up interface resources + io 0x60 = 0x2f8 + irq 0x70 = 3 + # Select correct package I/O pins + io 0xf1 = 0x04 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + # Set up interface resources + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.7 off end # Game port, MIDI, GPIO 1 & 5 + device pnp 2e.8 off end # GPIO 2 + device pnp 2e.9 on end # GPIO 3, GPIO 4 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + # Set up interface resources + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM n-0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM n-0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM n-0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM n-0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM n-1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM n-1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM n-1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM n-1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on end # SM 1 + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 off end # AC'97 Audio (N/A) + device pci 4.1 off end # AC'97 Modem (N/A) + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 0 + device pci 8.0 on end # SATA 1 + device pci 9.0 on # Bridge + device pci 4.0 on end # VGA + end + device pci a.0 off end + device pci b.0 on # Bridge + device pci 0.0 on end # NIC A + end + device pci c.0 on # Bridge + device pci 0.0 on end # LSI SAS + end + device pci d.0 on # Bridge + device pci 0.0 on end # NIC B + end + device pci e.0 on # Bridge + # Slot # PCI E 0 + end + device pci f.0 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end + end + end +end diff --git a/src/mainboard/asus/kfsn4-dre/dsdt.asl b/src/mainboard/asus/kfsn4-dre/dsdt.asl new file mode 100644 index 0000000..9f66ffc --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/dsdt.asl @@ -0,0 +1,951 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2005 - 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com> + * Copyright (C) 2007, 2008 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * WARNING: Sleep/Wake is a work in progress and is still somewhat flaky! + * Everything else does to the best of my knowledge... (T.P. 01/26/2015) + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +/* + * PCI link routing templates taken from ck804.asl and modified for this board + */ + +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "ASUS ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00000001 /* OEM Revision */ + ) +{ + #include "northbridge/amd/amdfam10/amdfam10_util.asl" + + /* Some global data */ + Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PICM, One) /* Assume APIC */ + + /* HPET control */ + Name (SHPB, 0xFED00000) + Name (SHPL, 0x1000) + + /* Define power states */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) /* Normal operation */ + Name (_S1, Package () { 0x01, 0x00, 0x00, 0x00 }) /* Standby */ + /* Name (_S3, Package () { 0x05, 0x00, 0x00, 0x00 }) */ /* Not supported by hardware */ + /* Name (_S4, Package () { 0x06, 0x00, 0x00, 0x00 }) */ + Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 }) /* Hard power off */ + + /* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + Method (_PIC, 1, Serialized) { + Store (Arg0, PICM) + } + + /* _PR CPU0 is dynamically supplied by SSDT */ + /* CPU objects and _PSS entries are dynamically supplied by SSDT */ + + Scope(\_GPE) { /* Start Scope GPE */ + /* VGA controller PME# */ + Method(_L00) { + /* Level-Triggered GPE */ + Notify(\_SB.PCI0.VGAC, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Keyboard controller PME# */ + Method(_L03) { + /* Level-Triggered GPE */ + Notify(\_SB.PCI0.LPC.KBD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.LPC.MOU, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* USB2 PME# */ + Method(_L05) { + /* Level-Triggered GPE */ + Notify (\_SB.PCI0.USB2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Slot PME# */ + Method(_L0B) { + /* Level-Triggered GPE */ + Notify (\_SB.PCI0.PCIE.SLT1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.LSIC.SLT2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* USB0 PME# */ + Method(_L0D) { + /* Level-Triggered GPE */ + Notify (\_SB.PCI0.USB0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Keyboard controller PME# */ + Method(_L10) { + /* Level-Triggered GPE */ + Notify(\_SB.PCI0.LPC.KBD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.LPC.MOU, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* PCIe PME# */ + Method(_L11) { + /* Level-Triggered GPE */ + Notify (\_SB.PCI0.NICB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.PCIE, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.NICA, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.LSIC, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + } /* End Scope GPE */ + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device (CK804) */ + Device (PCI0) + { + /* BUS0 root bus */ + + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00180001) + Name (_UID, 0x00) + + Name (HCIN, 0x00) // HC1 + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + /* Operating System Capabilities Method */ + Method(_OSC,4) + { + /* Let OS control everything */ + Return (Arg3) + } + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + External (CBST) + + /* PCI Routing Tables */ + Name (PR00, Package () { + /* PIC */ + /* ISA Bridge */ + Package (0x04) { 0x0001FFFF, 0x00, LKSM, 0x00 }, + + /* USB */ + Package (0x04) { 0x0002FFFF, 0x00, LUB0, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, LUB2, 0x00 }, + + /* SATA 0 */ + Package (0x04) { 0x0007FFFF, 0x00, LSA0, 0x00 }, + + /* SATA 1 */ + Package (0x04) { 0x0008FFFF, 0x00, LSA1, 0x00 }, + + /* NIC A (Bridge) */ + Package (0x04) { 0x000BFFFF, 0x00, LNKB, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x01, LNKC, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x02, LNKD, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x03, LNKA, 0x00 }, + + /* NIC B (Bridge) */ + Package (0x04) { 0x000CFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x03, LNKD, 0x00 }, + + /* LSI SAS Controller (Bridge) */ + Package (0x04) { 0x000DFFFF, 0x00, LNKD, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x01, LNKA, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x02, LNKB, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x03, LNKC, 0x00 }, + + /* PCI-E Slot (Bridge) */ + Package (0x04) { 0x000EFFFF, 0x00, LNKC, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x01, LNKD, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x02, LNKA, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x03, LNKB, 0x00 }, + }) + + Name (AR00, Package () { + /* APIC */ + /* ISA Bridge */ + Package (0x04) { 0x0001FFFF, 0x00, LKSM, 0x00 }, + + /* USB */ + Package (0x04) { 0x0002FFFF, 0x00, LUB0, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, LUB2, 0x00 }, + + /* SATA 0 */ + Package (0x04) { 0x0007FFFF, 0x00, LSA0, 0x00 }, + + /* SATA 1 */ + Package (0x04) { 0x0008FFFF, 0x00, LSA1, 0x00 }, + + /* NIC A (Bridge) */ + Package (0x04) { 0x000BFFFF, 0x00, LNIB, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x01, LNIC, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x02, LNND, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x03, LNIA, 0x00 }, + + /* NIC B (Bridge) */ + Package (0x04) { 0x000CFFFF, 0x00, LNIA, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x01, LNIB, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x02, LNIC, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x03, LNND, 0x00 }, + + /* LSI SAS Controller (Bridge) */ + Package (0x04) { 0x000DFFFF, 0x00, LNND, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x01, LNIA, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x02, LNIB, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x03, LNIC, 0x00 }, + + /* PCI-E Slot (Bridge) */ + Package (0x04) { 0x000EFFFF, 0x00, LNIC, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x01, LNND, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x02, LNIA, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x03, LNIB, 0x00 }, + }) + + Name (PR01, Package () { + /* PIC */ + Package (0x04) { 0x0004FFFF, 0x00, LNKA, 0x00 }, + }) + + Name (AR01, Package () { + /* APIC */ + Package (0x04) { 0x0004FFFF, 0x00, LNIA, 0x00 }, + }) + + Name (PR02, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKD, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKA, 0x00 }, + }) + + Name (AR02, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, LNIB, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNIC, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNND, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNIA, 0x00 }, + }) + + Name (PR03, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, + }) + + Name (AR03, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, LNIA, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNIB, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNIC, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNND, 0x00 }, + }) + + Name (PR04, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKD, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKC, 0x00 }, + }) + + Name (AR04, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, LNND, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNIA, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNIB, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNIC, 0x00 }, + }) + + Name (PR05, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKD, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKB, 0x00 }, + }) + + Name (AR05, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, LNIC, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNND, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNIA, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNIB, 0x00 }, + }) + + /* PCI Resource Tables */ + + Name (RSIA, ResourceTemplate () { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) {8} + }) + + Name (RSMA, ResourceTemplate () { + /* APIC */ + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {16} + }) + + Name (RSIB, ResourceTemplate () { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) {1} + }) + + Name (RSMB, ResourceTemplate () { + /* APIC */ + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {17} + }) + + Name (RSIC, ResourceTemplate () { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) {2} + }) + + Name (RSMC, ResourceTemplate () { + /* APIC */ + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {18} + }) + + Name (RSND, ResourceTemplate () { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) {13} + }) + + Name (RSMD, ResourceTemplate () { + /* APIC */ + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {19} + }) + + Name (RSS2, ResourceTemplate () + { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) + {3, 4, 5, 7, 9, 10, 11, 12, 14, 15} + }) + + Name (RSA1, ResourceTemplate () + { + /* APIC */ + IRQ (Level, ActiveLow, Shared, ) + {3, 4, 5, 6, 7, 10, 11, 12, 14, 15} + }) + + Method (_CRS, 0, Serialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods below use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + +#include "southbridge/nvidia/ck804/acpi/ck804.asl" + + /* PCI Routing Table Access */ + Method (_PRT, 0, NotSerialized) { + If (PICM) { + Return (AR00) + } Else { + Return (PR00) + } + } + + /* USB0 */ + Device (LUB0) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTQ) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTQ) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (PRSC) + } Else { + Return (RSA1) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSC(\_SB.PCI0.LPCB.INTQ)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTQ)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTQ) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTQ) + } + } + } + + /* USB2 */ + Device (LUB2) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTL) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTL) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (PRSC) + } Else { + Return (RSA1) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSC(\_SB.PCI0.LPCB.INTL)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTL)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTL) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTL) + } + } + } + + /* ISA Bridge */ + Device (LKSM) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x0C) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTK) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTK) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSA1) + } Else { + Return (RSS2) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTK)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTK)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTK) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTK) + } + } + } + + /* Bridge device link (NIC A) */ + Device (LNIA) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTA) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTA) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSMA) + } Else { + Return (RSIA) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTA)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTA)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTA) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTA) + } + } + } + + /* Bridge device link (NIC B) */ + Device (LNIB) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTB) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTB) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSMB) + } Else { + Return (RSIB) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTB)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTB)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTB) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTB) + } + } + } + + /* Bridge device link */ + Device (LNIC) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTC) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTC) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSMC) + } Else { + Return (RSIC) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTC)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTC)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTC) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTC) + } + } + } + + /* Bridge device link */ + Device (LNND) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTD) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTD) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSMD) + } Else { + Return (RSND) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTD)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTD)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTD) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTD) + } + } + } + + /* 0:02.0 CK804 USB 0 */ + Device (USB0) + { + Name (_ADR, 0x00020000) // _ADR: Address + Name(_PRW, Package () {0x0D, 0x04}) // Wake from S1-S4 + } + + /* 0:02.0 CK804 USB 2 */ + Device (USB2) + { + Name (_ADR, 0x00020001) // _ADR: Address + Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 + } + + /* 1:04.0 VGA Controller */ + Device (VGAC) + { + Name (_ADR, 0x00090000) // _ADR: Address + Name(_PRW, Package () {0x00, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR01) + } Else { + Return (PR01) + } + } + } + + /* 2:00.0 PCIe NIC A */ + Device (NICA) + { + Name (_ADR, 0x000B0000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR02) + } Else { + Return (PR02) + } + } + Device (BDC1) + { + Name (_ADR, Zero) // _ADR: Address + } + } + + /* 3:00.0 PCIe NIC B */ + Device (NICB) + { + Name (_ADR, 0x000C0000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR03) + } Else { + Return (PR03) + } + } + Device (BDC2) + { + Name (_ADR, Zero) // _ADR: Address + } + } + + /* 4:00.0 PCIe LSI SAS Controller */ + Device (LSIC) + { + Name (_ADR, 0x000D0000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR04) + } Else { + Return (PR04) + } + } + + Device (SLT2) + { + Name (_ADR, 0xFFFF) // _ADR: Address + Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 + } + } + + /* 5:00.0 PCIe x16 */ + Device (PCIE) + { + Name (_ADR, 0x000E0000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR05) + } Else { + Return (PR05) + } + } + Device (SLT1) + { + Name (_ADR, 0xFFFF) // _ADR: Address + Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 + } + } + + Device (LPC) { + Name (_HID, EisaId ("PNP0A05")) + Name (_ADR, 0x00010000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Name (_CID, EisaId ("PNP030B")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, Serialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F03")) + Name (_CID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, Serialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + + /* UART 1 */ + Device (URT1) + { + Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART + Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4 + Method (_STA, 0, NotSerialized) + { + Return (0x0f) // Always enable + } + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + } EndDependentFn() + }) + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + }) + } + } + + /* UART 2 */ + Device (URT2) + { + Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART + Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4 + Method (_STA, 0, NotSerialized) + { + Return (0x0f) // Always enable + } + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + }) + } + } + + /* Floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, Serialized) + { + Name (BUF0, ResourceTemplate () { + FixedIO (0x03F0, 0x08) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + Device (HPET) + { + Name (_HID, EisaId ("PNP0103")) + Name (CRS, ResourceTemplate () + { + Memory32Fixed (ReadOnly, + 0x00000000, + 0x00001000, + _Y02) + IRQNoFlags () {0} + IRQNoFlags () {8} + }) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._BAS, HPT1) + CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._LEN, HPT2) + Store (SHPB, HPT1) + Store (SHPL, HPT2) + Return (CRS) + } + + } + } + } + + Device (PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } + +#include "acpi/pm_ctrl.asl" + +} diff --git a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c new file mode 100644 index 0000000..9d20d76 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#include <stdlib.h> +#if CONFIG_LOGICAL_CPUS +#include <cpu/amd/multicore.h> +#endif +#include <cpu/amd/amdfam10_sysconf.h> +#include <stdlib.h> + +/* + * Global variables for MB layouts and these will be shared by irqtable, + * mptable and acpi_tables. + */ +/* busnum is default */ +unsigned char bus_ck804[6]; +unsigned apicid_ck804; + +/* Here you only need to set value in pci1234 for HT-IO that could be +installed or not You may need to preset pci1234 for HTIO board, please +refer to src/northbridge/amd/amdfam10/get_pci1234.c for detail */ +static u32 pci1234x[] = { + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, + }; + + +/* HT Chain device num, actually it is unit id base of every ht device +in chain, assume every chain only have 4 ht device at most */ + +static unsigned hcdnx[] = { + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, +}; + +extern void get_pci1234(void); + +static unsigned get_bus_conf_done = 0; + +void get_bus_conf(void) +{ + unsigned apicid_base, sbdn; + device_t dev; + int i; + + if (get_bus_conf_done == 1) + return; /* Do it only once. */ + + get_bus_conf_done = 1; + + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_pci1234(); + + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sbdn = sysconf.sbdn; + + for (i = 0; i < 6; i++) + bus_ck804[i] = 0; + + /* CK804 */ + dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x09, 0)); + if (dev) { + bus_ck804[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804[2]++; + } else { + printk + (BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x09); + bus_ck804[1] = 2; + bus_ck804[2] = 3; + } + + for (i = 2; i < 6; i++) { + dev = dev_find_slot(bus_ck804[0], + PCI_DEVFN(sbdn + 0x0b + i - 2, 0)); + if (dev) { + bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_ck804[0], sbdn + 0x0b + i - 2); + } + } + + if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { + apicid_base = get_apicid_base(1); + printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==1: apicid_base: %08x\n", apicid_base); + } + else { + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==0: apicid_base: %08x\n", apicid_base); + } + apicid_ck804 = apicid_base + 0; +} diff --git a/src/mainboard/asus/kfsn4-dre/irq_tables.c b/src/mainboard/asus/kfsn4-dre/irq_tables.c new file mode 100644 index 0000000..437961c --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/irq_tables.c @@ -0,0 +1,184 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// WARNING +// These tables are INVALID for this mainboard! +// The ACPI tables are correct; a backport to these PIR tables is needed... + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam10_sysconf.h> + +extern unsigned char bus_isa; +extern unsigned char bus_ck804[6]; + + +/** + * Add one line to IRQ table. + */ +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, + uint8_t devfn, uint8_t link0, uint16_t bitmap0, + uint8_t link1, uint16_t bitmap1, uint8_t link2, + uint16_t bitmap2, uint8_t link3, uint16_t bitmap3, + uint8_t slot, uint8_t rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +/** + * Create the IRQ routing table. + * Values are derived from getpir generated code. + */ +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + unsigned slot_num, sbdn; + uint8_t *v, sum = 0; + int i; + + /* get_bus_conf() will find out all bus num and APIC that share with + * mptable.c and mptable.c. + */ + get_bus_conf(); + sbdn = sysconf.sbdn; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000. */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (uint8_t *)(addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + pirq->rtr_bus = bus_ck804[0]; + pirq->rtr_devfn = ((sbdn + 9) << 3) | 0; + pirq->exclusive_irqs = 0x828; + pirq->rtr_vendor = 0x10de; + pirq->rtr_device = 0x005c; + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* Slot1 PCIE 16x */ + write_pirq_info(pirq_info, bus_ck804[1], (0 << 3) | 0, 0x3, 0xdeb8, 0x4, + 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0); + pirq_info++; + slot_num++; + + + /* Slot2 PCIE 1x */ + write_pirq_info(pirq_info, bus_ck804[2], (0 << 3) | 0, 0x4, 0xdeb8, 0x1, + 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 5, 0); + pirq_info++; + slot_num++; + + /* Slot3 PCIE 1x */ + write_pirq_info(pirq_info, bus_ck804[3], (0 << 3) | 0, 0x1, 0xdeb8, 0x2, + 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 6, 0); + pirq_info++; + slot_num++; + + /* Slot4 PCIE 4x */ + write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0, 0x2, + 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 7, 0); + pirq_info++; + slot_num++; + + /* Slot5 - Slot7 PCI */ + for (i = 0; i < 3; i++) { + write_pirq_info(pirq_info, bus_ck804[5], (0 << (6 + i)) | 0, + ((i + 0) % 4) + 1, 0xdeb8, + ((i + 1) % 4) + 1, 0xdeb8, + ((i + 2) % 4) + 1, 0xdeb8, + ((i + 3) % 4) + 1, 0xdeb8, i, 0); + pirq_info++; + slot_num++; + } + + /* PCI bridge */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 9) << 3) | 0, 0x1, + 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0, 0); + pirq_info++; + slot_num++; + + /* SMBus */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 1) << 3) | 0, 0x2, + 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + /* USB */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 2) << 3) | 0, 0x1, + 0xdeb8, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + /* SATA */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 7) << 3) | 0, 0x1, + 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + /* SATA */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 8) << 3) | 0, 0x1, + 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + if (sum != pirq->checksum) + pirq->checksum = sum; + + printk(BIOS_INFO, "done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/asus/kfsn4-dre/mptable.c b/src/mainboard/asus/kfsn4-dre/mptable.c new file mode 100644 index 0000000..46ae594 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/mptable.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// WARNING +// These tables are INCOMPLETE for this mainboard! +// The ACPI tables are correct; a backport to these MP tables is needed... + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam10_sysconf.h> + +extern unsigned char bus_ck804[6]; +extern unsigned apicid_ck804; + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + unsigned sbdn; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + smp_write_processors(mc); + + get_bus_conf(); + sbdn = sysconf.sbdn; + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + { + device_t dev; + struct resource *res; + + dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_1); + if (res) { + smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); + } + + /* Initialize interrupt mapping. */ + + /* + LPC bridge PCI config registers: + + 0x7c:0x0000ffff + - bitmap of masked pci irqs? + - PIRQ[ABCD] possibly? + + 0x7c:0x00f00000 + - sata at f8 - port 1 + + 0x7c:0x0f000000 + - sata at f7 - port 1 + + 0x80:0xf0000000 + - sata at f7 - port 0 + + 0x80:0x0f000000 + - sata at f8 - port 0 + + 0x80:0x0000f000 + - EHCI + + 0x84:0x00000f00 + - NIC + + 0x84:0x0000000f + - OHCI + + known values of nibbles: + + 0 - unrouted? + 1 - irq 23 + 8 - irq 20 + c - irq 12 + d - irq 21 + e - irq 14 + f - irq 15 + */ + + // Enable interrupts for commonly used devices (USB, SATA, etc.) + pci_write_config32(dev, 0x7c, 0x0d800018); + pci_write_config32(dev, 0x80, 0xd8002009); + pci_write_config32(dev, 0x84, 0x00000001); + } + } + + mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0); + + // Onboard ck804 smbus + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804, + 0xa); + + // Onboard ck804 USB 1.1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804, + 0x15); + + // Onboard ck804 USB 2 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804, + 0x14); + + // Onboard ck804 SATA 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804, + 0x17); + + // Onboard ck804 SATA 1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804, + 0x16); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + mptable_lintsrc(mc, bus_ck804[0]); + + /* There is no extension information... */ + + /* Compute the checksums. */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/kfsn4-dre/resourcemap.c b/src/mainboard/asus/kfsn4-dre/resourcemap.c new file mode 100644 index 0000000..5ba0b01 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/resourcemap.c @@ -0,0 +1,284 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static void setup_mb_resource_map(void) +{ + static const unsigned int register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [31:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000, + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000, + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> Nvidia CK 804 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independent of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration region i + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> Nvidia CK 804 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + + }; + + int max; + max = ARRAY_SIZE(register_values); + setup_resource_map(register_values, max); +} diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c new file mode 100644 index 0000000..2827d2b --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -0,0 +1,394 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define FAM10_SCAN_PCI_BUS 0 +#define FAM10_ALLOCATE_IO_RANGE 1 + +unsigned int get_sbdn(unsigned bus); + +#include <stdint.h> +#include <string.h> +#include <reset.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <lib.h> +#include <spd.h> +#include <cpu/amd/model_10xxx_rev.h> +#include "southbridge/nvidia/ck804/early_smbus.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> +#include "lib/delay.c" +#include <cpu/x86/lapic.h> +#include "northbridge/amd/amdfam10/reset_test.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627thg/w83627thg.h> +#include <cpu/x86/bist.h> +// #include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdfam10/debug.c" +#include "northbridge/amd/amdfam10/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) + +static void activate_spd_rom(const struct mem_controller *ctrl); + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include <northbridge/amd/amdfam10/amdfam10.h> +#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" +#include "northbridge/amd/amdfam10/pci.c" +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" + +/* + * Avoid crash (complete with severe memory corruption!) during initial CAR boot + * in ck804_early_setup_x(). + * Interestingly once the system is fully booted into Linux this can be set, but + * not before! Apparently something isn't initialized but the amount of effort + * required to fix this is non-negligible and of unknown real-world benefit + */ +#define CK804_SKIP_PCI_REG_78_INIT 1 + +#define CK804_MB_SETUP \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/ + +#include <southbridge/nvidia/ck804/early_setup_ss.h> +#include "southbridge/nvidia/ck804/early_setup_car.c" +#include <cpu/amd/microcode.h> + +#include "cpu/amd/model_10xxx/init_cpus.c" +#include "northbridge/amd/amdfam10/early_ht.c" + +#define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3) + +/** + * @brief Get SouthBridge device number + * @param[in] bus target bus number + * @return southbridge device number + */ +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus); + return (dev >> 15) & 0x1f; +} + +/* + * ASUS KFSN4-DRE specific SPD enable/disable magic. + * + * Setting CK804 GPIO43 and GPIO44 to 0 and 0 respectively will make the + * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD + * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which + * will make RAM init fail. + * + * Disable SPD access after RAM init to allow access to standard SMBus/I2C offsets + * which is required e.g. by lm-sensors. + */ + +#define CK804_BOARD_BOOT_BASE_UNIT_UID 1 + +static const unsigned int ctrl_conf_enable_spd_node0[] = { + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/ +}; + +static const unsigned int ctrl_conf_enable_spd_node1[] = { + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x01),/* W3,GPIO44, U6 input S1*/ +}; + +static const unsigned int ctrl_conf_disable_spd[] = { + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x01),/* W2,GPIO43, U6 input S0*/ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/ +}; + +static const unsigned int ctrl_conf_fix_pci_numbering[] = { + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x44), ~(0x00010000), 0x00000000, /* Force CK804 to start its internal device numbering (Base Unit ID) at 0 instead of the power-on default of 1 */ +}; + +static const unsigned int ctrl_conf_enable_msi_mapping[] = { + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */ +}; + +static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id) +{ + unsigned busn[4], io_base[4]; + int i, ck804_num = 0; + + for (i = 0; i < 4; i++) { + u32 id; + device_t dev; + if (i == 0) /* SB chain */ + dev = PCI_DEV(i * 0x40, bus_unit_id, 0); + else + dev = 0; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (id == 0x005e10de) { + busn[ck804_num] = i * 0x40; + io_base[ck804_num] = i * 0x4000; + ck804_num++; + } + } + + if (ck804_num < 1) + printk(BIOS_WARNING, "CK804 not found at device base unit id %02x!\n", bus_unit_id); + + ck804_early_set_port(ck804_num, busn, io_base); + + setup_resource_map_x_offset(values, + size, + PCI_DEV(0, bus_unit_id, 0), io_base[0]); + + ck804_early_clear_port(ck804_num, busn, io_base); +} + +static void sio_setup(void) +{ + u32 dword; + u8 byte; + + /* Subject decoding */ + byte = pci_read_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b, byte); + + /* LPC Positive Decode 0 */ + dword = pci_read_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0); + /* Serial 0, Serial 1 */ + dword |= (1 << 0) | (1 << 1); + pci_write_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0, dword); +} + +static const uint8_t spd_addr[] = { + // Node 0 + RC00, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, + // Node 1 + RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, +}; + +static void activate_spd_rom(const struct mem_controller *ctrl) { + printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); + if (ctrl->node_id == 0) { + printk(BIOS_DEBUG, "enable_spd_node0()\n"); + ck804_control(ctrl_conf_enable_spd_node0, ARRAY_SIZE(ctrl_conf_enable_spd_node0), CK804_DEVN_BASE); + } + else if (ctrl->node_id == 1) { + printk(BIOS_DEBUG, "enable_spd_node1()\n"); + ck804_control(ctrl_conf_enable_spd_node1, ARRAY_SIZE(ctrl_conf_enable_spd_node1), CK804_DEVN_BASE); + } +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + struct sys_info *sysinfo = &sysinfo_car; + + u32 bsp_apicid = 0, val, wants_reset; + msr_t msr; + + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + set_bsp_node_CHtExtNodeCfgEn(); + enumerate_ht_chain(); + sio_setup(); + } + + post_code(0x30); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + post_code(0x32); + + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + if (CONFIG_MAX_PHYSICAL_CPUS != 2) + printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket board!\n", CONFIG_MAX_PHYSICAL_CPUS); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + /* Setup sysinfo defaults */ + set_sysinfo_in_ram(0); + + update_microcode(val); + + post_code(0x33); + + cpuSetAMDMSR(); + post_code(0x34); + + amd_ht_init(sysinfo); + post_code(0x35); + + /* Setup nodes PCI space and start core 0 AP init. */ + finalize_node_setup(sysinfo); + + /* Setup any mainboard PCI settings etc. */ + setup_mb_resource_map(); + post_code(0x36); + + /* wait for all the APs core0 started by finalize_node_setup. */ + /* FIXME: A bunch of cores are going to start output to serial at once. + * It would be nice to fix up prink spinlocks for ROM XIP mode. + * I think it could be done by putting the spinlock flag in the cache + * of the BSP located right after sysinfo. + */ + wait_all_core0_started(); + + if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); + start_other_cores(); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + } + + printk(BIOS_DEBUG, "set_ck804_base_unit_id()\n"); + ck804_control(ctrl_conf_fix_pci_numbering, ARRAY_SIZE(ctrl_conf_fix_pci_numbering), CK804_BOARD_BOOT_BASE_UNIT_UID); + + post_code(0x38); + + if (IS_ENABLED(CONFIG_SET_FIDVID)) { + msr = rdmsr(0xc0010071); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); + + post_code(0x39); + + if (!warm_reset_detect(0)) { // BSP is node 0 + init_fidvid_bsp(bsp_apicid, sysinfo->nodes); + } else { + init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + } + + post_code(0x3A); + + /* show final fid and vid */ + msr=rdmsr(0xc0010071); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); + } + + init_timer(); // Need to use TMICT to synconize FID/VID + + wants_reset = ck804_early_setup_x(); + + /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ + if (!warm_reset_detect(0)) { + printk(BIOS_INFO, "...WARM RESET...\n\n\n"); + soft_reset(); + die("After soft_reset_x - shouldn't see this message!!!\n"); + } + + if (wants_reset) { + printk(BIOS_DEBUG, "ck804_early_setup_x wanted additional reset!\n"); + } + + post_code(0x3B); + + /* It's the time to set ctrl in sysinfo now; */ + printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + post_code(0x3D); + + printk(BIOS_DEBUG, "enable_smbus()\n"); + enable_smbus(); + +#if 0 + /* FIXME + * After the AMD K10 code has been converted to use + * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block + */ + if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) { + dump_spd_registers(&cpu[0]); + dump_smbus_registers(); + } +#endif + + post_code(0x40); + + printk(BIOS_DEBUG, "raminit_amdmct()\n"); + raminit_amdmct(sysinfo); + post_code(0x41); + + printk(BIOS_DEBUG, "disable_spd()\n"); + ck804_control(ctrl_conf_disable_spd, ARRAY_SIZE(ctrl_conf_disable_spd), CK804_DEVN_BASE); + + printk(BIOS_DEBUG, "enable_msi_mapping()\n"); + ck804_control(ctrl_conf_enable_msi_mapping, ARRAY_SIZE(ctrl_conf_enable_msi_mapping), CK804_DEVN_BASE); + + /* Initialize GPIO */ + /* Access SuperIO GPI03 logical device */ + uint16_t port = GPIO3_DEV >> 8; + outb(0x87, port); + outb(0x87, port); + pnp_set_logical_device(GPIO3_DEV); + /* Set GP37 (power LED) to output */ + pnp_write_config(GPIO3_DEV, 0xf0, 0x7f); + /* Set GP37 (power LED) on */ + pnp_write_config(GPIO3_DEV, 0xf1, 0x80); + /* Set pin 67 multiplex to GP37 */ + uint8_t cr2c = pnp_read_config(GPIO3_DEV, 0x2c); + pnp_write_config(GPIO3_DEV, 0x2c, (cr2c & 0xf3) | 0x04); + /* Restore default SuperIO access */ + outb(0xaa, port); + + post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. + post_code(0x43); // Should never see this post code. +} + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + return 0; +} diff --git a/src/mainboard/asus/kfsn4-dre/spd_notes.txt b/src/mainboard/asus/kfsn4-dre/spd_notes.txt new file mode 100644 index 0000000..ff49c18 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/spd_notes.txt @@ -0,0 +1,50 @@ +==================================================================================================== +SPD mux +==================================================================================================== + +DIMM_A1 SDA signal traced to U6 pin 1 +Destructive testing of failed board (removal of U7 northbridge!) yielded the following information: +U6 S0 <--> U7 W2 +U6 S1 <--> U7 W3 + +Proprietary BIOS enables the SPD during POST with: +S0: LOW +S1: LOW + +then temporarily switches to: +S0: LOW +S1: HIGH + +then switches to runtime mode with: +S0: HIGH +S1: LOW + +After probing with a custom GPIO-flipping tool under Linux the following GPIO mappings were found: +CK804 pin W2 <--> GPIO43 +CK804 pin W3 <--> GPIO44 + +==================================================================================================== +Other hardware +==================================================================================================== + +Power LED (-) is connected to U15 (SuperIO) pin 64 via U4 pins 5,6 and a small MOSFET +ID LED (-) is connected to a ??? via U4 pins 1,2,3,4 and U77 pins 5,6 +It appears that setting U15 (SuperIO) pin 88 LOW will override the ID LED and force it ON + +PCIe slot WAKE# connects to U7 pin E23 (PCIE_WAKE#) + +CPU_WARN1 is driven by (???) via a simple buffer (U13 pin 10) +MEM_WARN1 is driven by U7 pin AD3 (CPUVDD_EN) via a simple buffer (U101 pin 3) + +U7 pin AK3 is disconnected (routed to unpopulated capacitor/resistor) +PU1 pin 37 (VDDPWRGD) drives U7 pin AJ4 (CPU_VLD) +A small MOSFET directly above another small MOSFET directly above the right-hand edge of the PCIe slot drives U7 pin AK5 (HT_VLD) + +When > Barcelona CPU installed on PCB rev 1.04G: +U7 pin AK4 (MEM_VLD): HIGH +PU1 pin 37: LOW +U7 pin AK5: LOW + +HyperTransport 1.2V supply appears to be generated by a linear regulator containing Q191 and downconverting the CK804 1.5V supply +The enable pin appears to be tied to AUX_PANEL pin 1 (+5VSB) via a resistor +Through two MOSFETs the HT supply enable pin is tied to U7 pin AE3 (HTVDD_EN)

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Patch set updated for coreboot: 036c882 nvidia/ck804: Enable AMD Family 0Fh/10h dynamic ACPI _PSS objects
by Timothy Pearson 28 Jan '15

28 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8285 -gerrit commit 036c882ce266b19d786fba36634dca5d9a78bd7e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jan 27 01:44:37 2015 -0600 nvidia/ck804: Enable AMD Family 0Fh/10h dynamic ACPI _PSS objects Change-Id: I682e6c34d059ae21f9767302659bdfdbea86bcc8 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/nvidia/ck804/lpc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index b24da6d..105f5cb 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -35,6 +35,7 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <assert.h> +#include <cpu/amd/powernow.h> #include "ck804.h" #define CK804_CHIP_REV 2 @@ -317,11 +318,21 @@ static void ck804_lpc_enable_resources(device_t dev) ck804_lpc_enable_childrens_resources(dev); } +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + +static void southbridge_acpi_fill_ssdt_generator(void) +{ + amd_generate_powernow(0, 0, 0); +} + +#endif + static struct device_operations lpc_ops = { .read_resources = ck804_lpc_read_resources, .set_resources = ck804_lpc_set_resources, .enable_resources = ck804_lpc_enable_resources, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init,

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Patch set updated for coreboot: 7faa8fd mainboards: Add support for the Asus KFSN4-DRE series of motherboards
by Timothy Pearson 28 Jan '15

28 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8270 -gerrit commit 7faa8fd13cfe3493b88bc076d02cdf78c88bd9f4 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:35:48 2015 -0600 mainboards: Add support for the Asus KFSN4-DRE series of motherboards Status: Tested with KFSN4-DRE PCB v1.04G Booted Ubuntu Linux 14.04 and all onboard peripherals appear to work. Dual Opteron 8347 CPUs tested with 8GB RAM (4GB per bank). Dual Opteron 8356 CPUs tested with 1GB RAM in slot A1. AMD PowerNow! functions correctly via ACPI. Video, network, USB, SATA, and serial have received thorough testing. Tested with KFSN4-DRE PCB v1.05G Single Opteron 2419 CPU tested with 1GB RAM in slot A1. Booted to PXE configuration menu; not tested further. Known issues: RAM initialization is a bit flaky with multiple high-density modules; this could be a generic MCT training issue but is probably bad hardware. The XGI Volari option ROM crashes SeaBIOS v1.7.5, but the video device works after Linux boots and initializes the device. Suspend/resume functions at the S1 level but sometimes hangs on resume. Wake on LAN can be flaky; the strap(s) needed to have WoL work on power application were not physically installed by ASUS so the board needs to boot at least once after power application before it will work. Change-Id: I0709f822eea8ed877f55db9443143028a5400472 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/kfsn4-dre/Kconfig | 108 +++ src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl | 245 +++++++ src/mainboard/asus/kfsn4-dre/acpi_tables.c | 71 ++ src/mainboard/asus/kfsn4-dre/board_info.txt | 5 + src/mainboard/asus/kfsn4-dre/cmos.layout | 118 ++++ src/mainboard/asus/kfsn4-dre/devicetree.cb | 121 ++++ src/mainboard/asus/kfsn4-dre/dsdt.asl | 951 ++++++++++++++++++++++++++ src/mainboard/asus/kfsn4-dre/get_bus_conf.c | 134 ++++ src/mainboard/asus/kfsn4-dre/irq_tables.c | 184 +++++ src/mainboard/asus/kfsn4-dre/mptable.c | 156 +++++ src/mainboard/asus/kfsn4-dre/resourcemap.c | 284 ++++++++ src/mainboard/asus/kfsn4-dre/romstage.c | 394 +++++++++++ src/mainboard/asus/kfsn4-dre/spd_notes.txt | 50 ++ 14 files changed, 2824 insertions(+) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index edd8f5d..9bc4e35 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -33,6 +33,8 @@ config BOARD_ASUS_F2A85_M bool "F2A85-M" config BOARD_ASUS_F2A85_M_LE bool "F2A85-M LE" +config BOARD_ASUS_KFSN4_DRE + bool "KFSN4-DRE" config BOARD_ASUS_K8V_X bool "K8V-X" config BOARD_ASUS_M2N_E @@ -76,6 +78,7 @@ source "src/mainboard/asus/a8v-e_deluxe/Kconfig" source "src/mainboard/asus/f2a85-m/Kconfig" source "src/mainboard/asus/f2a85-m_le/Kconfig" source "src/mainboard/asus/k8v-x/Kconfig" +source "src/mainboard/asus/kfsn4-dre/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig new file mode 100644 index 0000000..07e01fd --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -0,0 +1,108 @@ +if BOARD_ASUS_KFSN4_DRE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_SOCKET_F_1207 + select DIMM_DDR2 + select DIMM_REGISTERED + select NORTHBRIDGE_AMD_AMDFAM10 + select SOUTHBRIDGE_NVIDIA_CK804 + select SUPERIO_WINBOND_W83627THG + select PARALLEL_CPU_INIT + select HAVE_HARD_RESET + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select LIFT_BSP_APIC_ID + select BOARD_ROMSIZE_KB_1024 + select ENABLE_APIC_EXT_ID + select AMDMCT + select MMCONF_SUPPORT_DEFAULT + +config MAINBOARD_DIR + string + default asus/kfsn4-dre + +config DCACHE_RAM_BASE + hex + default 0xc4000 + +config DCACHE_RAM_SIZE + hex + default 0x0c000 + +config APIC_ID_OFFSET + hex + default 0 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "KFSN4-DRE" + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + +config PCI_64BIT_PREF_MEM + bool + default n + +config MAX_CPUS + int + default 8 + +config MAX_PHYSICAL_CPUS + int + default 2 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config IRQ_SLOT_COUNT + int + default 13 + +config AMD_UCODE_PATCH_FILE + string + default "mc_patch_01000095.h" + +config CK804_PCI_E_X + int + default 1 + +config CK804_PCIE_PME_WAKE + bool + default y + +config DRIVERS_PS2_KEYBOARD + bool + default y + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n + +config VGA_BIOS_ID + string + depends on VGA_BIOS + default "18ca:0020" + +config AMDMCT_BACKGROUND_SCRUB_RATE + hex + default 0x06 + +endif # BOARD_ASUS_KFSN4_DRE diff --git a/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl b/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl new file mode 100644 index 0000000..c55835e --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl @@ -0,0 +1,245 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2010 - 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com> + * Copyright (C) 2007, 2008 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * WARNING: Sleep/Wake is a work in progress and is still somewhat flaky! + */ + + /* SuperIO control port */ + Name (SPIO, 0x2E) + + /* SuperIO control map */ + OperationRegion (SPIM, SystemIO, SPIO, 0x02) + Field (SPIM, ByteAcc, NoLock, Preserve) { + INDX, 8, + DATA, 8 + } + + /* SuperIO control registers */ + IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) { + Offset (0x07), + CR07, 8, /* Logical device number */ + Offset (0x2C), + CR2C, 8, /* GPIO3 multiplexed pin selection */ + Offset (0x30), + CR30, 8, /* Logical device activation control register */ + Offset (0xE0), + CRE0, 8, /* Wake control register */ + Offset (0xE6), + CRE6, 8, /* Mouse wake event configuration register */ + Offset (0xF1), + CRF1, 8, /* GPIO3 data register */ + Offset (0xF3), + CRF3, 8, /* SUSLED mode register */ + Offset (0xF6), + CRF6, 8, /* SMI/PME event generation control register */ + Offset (0xF9), + CRF9, 8, /* ACPI PME configuration register */ + } + + /* Southbridge control ports */ + /* Both are offsets from PM base address (0x2000) */ + Name (SBC1, 0x2090) /* Offset 0x90 */ + Name (SBC2, 0x2400) /* Offset 0x400 */ + + /* Southbridge control maps */ + OperationRegion (SBM1, SystemIO, SBC1, 0x10) + Field (SBM1, ByteAcc, NoLock, Preserve) { + S1CT, 2, + Offset (0x04), + S3CT, 2, + Offset (0x08), + S4CT, 2, + Offset (0x0C), + S5CT, 2, + } + OperationRegion (SBM2, SystemIO, SBC2, 0x08) + Field (SBM2, ByteAcc, NoLock, Preserve) { + , 15, + PS1S, 1, + , 31, + PS1E, 1, + } + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* Set up LEDs */ + /* Access SuperIO GPIO3/GPIO4 device */ + Store(0x87, INDX) + Store(0x87, INDX) + Store(0x09, CR07) + + /* Set GPIO3 pin 64 (power LED) to GP37 mode */ + And(CR2C, 0xF3, Local0) + Or(Local0, 0x04, CR2C) + + /* Set power LED to steady on */ + Or(CRF1, 0x80, CRF1) + + /* Restore default SuperIO access */ + Store(0xAA, INDX) + + /* Configure SuperIO for wake */ + /* Access SuperIO ACPI device */ + Store(0x87, INDX) + Store(0x87, INDX) + Store(0x0A, CR07) + + if (LEqual(Arg0, One)) /* Resuming from power state S1 */ + { + /* Set power management to SMI mode and disable SMI events */ + And(CRF9, 0xFA, CRF9) + + /* Deactivate the ACPI device */ + Store(Zero, CR30) + + /* Disable PS/2 SMI/PME events */ + And(CRF6, 0xCF, CRF6) + } + if (Lor(LEqual(Arg0, 0x03), LEqual(Arg0, 0x04))) /* Resuming from power state S3 or S4 */ + { + /* Disable PS/2 wake */ + And(CRE0, 0x1D, CRE0) + And(CRE6, 0x7F, CRE6) + } + + /* Restore default SuperIO access */ + Store(0xAA, INDX) + + /* Configure southbridge for wake */ + Store(Zero, PS1E) + Store(0x02, S1CT) + Store(0x02, S3CT) + Store(0x02, S4CT) + Store(0x02, S5CT) + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + + Return(WKST) + } /* End Method(\_WAK) */ + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(\_PTS, 1) { + /* Set up LEDs */ + if (LEqual(Arg0, One)) /* Power state S1 requested */ + { + /* Access SuperIO GPIO3/GPIO4 device */ + Store(0x87, INDX) + Store(0x87, INDX) + Store(0x09, CR07) + + /* Set GPIO3 pin 64 (power LED) to SUSLED mode */ + And(CR2C, 0xF3, CR2C) + + /* Set suspend LED to 1Hz toggle pulse with 50% duty cycle */ + Or(CRF3, 0x80, CRF3) + + /* Restore default SuperIO access */ + Store(0xAA, INDX) + } + + /* Configure SuperIO for sleep */ + /* Access SuperIO ACPI device */ + Store(0x87, INDX) + Store(0x87, INDX) + Store(0x0A, CR07) + + /* Disable PS/2 wakeup and connect PANSW_IN to PANSW_OUT */ + And(CRE0, 0x1F, CRE0) + + if (LEqual(Arg0, One)) /* Power state S1 requested */ + { + /* Set power management to PME mode and enable PME events */ + Or(CRF9, 0x05, CRF9) + + /* Activate the ACPI device */ + Store(One, CR30) + + /* Enable PS/2 keyboard SMI/PME events */ + And(CRF6, 0xEF, CRF6) + + /* Enable PS/2 keyboard wake */ + Or(CRE0, 0x40, CRE0) + + /* Enable PS/2 mouse SMI/PME events */ + And(CRF6, 0xDF, CRF6) + + /* Enable PS/2 mouse wake */ + Or(CRE0, 0x20, CRE0) + } + else { + /* Enable PS/2 keyboard wake on any keypress */ + Or(CRE0, 0x41, CRE0) + + /* Enable PS/2 mouse wake on any click */ + Or(CRE0, 0x22, CRE0) + Or(CRE6, 0x80, CRE6) + } + + /* Restore default SuperIO access */ + Store(0xAA, INDX) + + /* Configure southbridge for sleep */ + Store(One, PS1S) + Store(One, PS1E) + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + } /* End Method(\_PTS) */ diff --git a/src/mainboard/asus/kfsn4-dre/acpi_tables.c b/src/mainboard/asus/kfsn4-dre/acpi_tables.c new file mode 100644 index 0000000..904ad38 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/acpi_tables.c @@ -0,0 +1,71 @@ +/* + * ACPI support + * written by Stefan Reinauer <stepan(a)openbios.org> + * (C) 2005 Stefan Reinauer + * + * Copyright 2005 AMD + * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + */ + +#include <console/console.h> +#include <string.h> +#include <assert.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam10_sysconf.h> + +/* APIC */ +unsigned long acpi_fill_madt(unsigned long current) +{ + device_t dev; + struct resource *res; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write NVIDIA CK804 IOAPIC. */ + dev = dev_find_slot(0x0, PCI_DEVFN(sysconf.sbdn + 0x1, 0)); + ASSERT(dev != NULL); + + res = find_resource(dev, PCI_BASE_ADDRESS_1); + ASSERT(res != NULL); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, res->base, 0); + + /* Initialize interrupt mapping if mptable.c didn't. */ + if (!IS_ENABLED(CONFIG_GENERATE_MP_TABLE)) { + /* Copied from mptable.c */ + /* Enable interrupts for commonly used devices (USB, SATA, etc.) */ + pci_write_config32(dev, 0x7c, 0x0d800018); + pci_write_config32(dev, 0x80, 0xd8002009); + pci_write_config32(dev, 0x84, 0x00000001); + } + +// /* IRQ of timer (override IRQ0 --> APIC IRQ2) */ +// current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) +// current, 0, 0, 2, 0); + /* IRQ9 */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + /* IRQ14 */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 14, 14, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH); + /* IRQ15 */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 15, 15, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH); + + /* create all subtables for processors */ + /* acpi_create_madt_lapic_nmis returns current, not size. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} diff --git a/src/mainboard/asus/kfsn4-dre/board_info.txt b/src/mainboard/asus/kfsn4-dre/board_info.txt new file mode 100644 index 0000000..788888e --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/board_info.txt @@ -0,0 +1,5 @@ +Category: server +ROM package: PLCC-32 +ROM protocol: LPC +ROM socketed: y +Flashrom support: y \ No newline at end of file diff --git a/src/mainboard/asus/kfsn4-dre/cmos.layout b/src/mainboard/asus/kfsn4-dre/cmos.layout new file mode 100644 index 0000000..3bb6df3 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/cmos.layout @@ -0,0 +1,118 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering +## Copyright (C) 2007 AMD +## Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +446 1 e 1 power_on_after_fail +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/kfsn4-dre/devicetree.cb b/src/mainboard/asus/kfsn4-dre/devicetree.cb new file mode 100644 index 0000000..3e0e41e --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/devicetree.cb @@ -0,0 +1,121 @@ +chip northbridge/amd/amdfam10/root_complex # Root complex + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device domain 0 on # PCI domain + subsystemid 0x1043 0x8162 inherit + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on end # Link 0 == LDT 0 + device pci 18.0 on # Link 1 == LDT 1 [SB on link 1] + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627thg # Super I/O + device pnp 2e.0 on # Floppy + # Set up interface resources + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off end # Parallel port + device pnp 2e.2 on # Com1 + # Set up interface resources + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + # Set up interface resources + io 0x60 = 0x2f8 + irq 0x70 = 3 + # Select correct package I/O pins + io 0xf1 = 0x04 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + # Set up interface resources + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.7 off end # Game port, MIDI, GPIO 1 & 5 + device pnp 2e.8 off end # GPIO 2 + device pnp 2e.9 on end # GPIO 3, GPIO 4 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + # Set up interface resources + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM n-0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM n-0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM n-0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM n-0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM n-1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM n-1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM n-1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM n-1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on end # SM 1 + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 off end # AC'97 Audio (N/A) + device pci 4.1 off end # AC'97 Modem (N/A) + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 0 + device pci 8.0 on end # SATA 1 + device pci 9.0 on # Bridge + device pci 4.0 on end # VGA + end + device pci a.0 off end + device pci b.0 on # Bridge + device pci 0.0 on end # NIC A + end + device pci c.0 on # Bridge + device pci 0.0 on end # LSI SAS + end + device pci d.0 on # Bridge + device pci 0.0 on end # NIC B + end + device pci e.0 on # Bridge + # Slot # PCI E 0 + end + device pci f.0 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end + end + end +end diff --git a/src/mainboard/asus/kfsn4-dre/dsdt.asl b/src/mainboard/asus/kfsn4-dre/dsdt.asl new file mode 100644 index 0000000..9f66ffc --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/dsdt.asl @@ -0,0 +1,951 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2005 - 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com> + * Copyright (C) 2007, 2008 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * WARNING: Sleep/Wake is a work in progress and is still somewhat flaky! + * Everything else does to the best of my knowledge... (T.P. 01/26/2015) + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +/* + * PCI link routing templates taken from ck804.asl and modified for this board + */ + +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "ASUS ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00000001 /* OEM Revision */ + ) +{ + #include "northbridge/amd/amdfam10/amdfam10_util.asl" + + /* Some global data */ + Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PICM, One) /* Assume APIC */ + + /* HPET control */ + Name (SHPB, 0xFED00000) + Name (SHPL, 0x1000) + + /* Define power states */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) /* Normal operation */ + Name (_S1, Package () { 0x01, 0x00, 0x00, 0x00 }) /* Standby */ + /* Name (_S3, Package () { 0x05, 0x00, 0x00, 0x00 }) */ /* Not supported by hardware */ + /* Name (_S4, Package () { 0x06, 0x00, 0x00, 0x00 }) */ + Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 }) /* Hard power off */ + + /* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + Method (_PIC, 1, Serialized) { + Store (Arg0, PICM) + } + + /* _PR CPU0 is dynamically supplied by SSDT */ + /* CPU objects and _PSS entries are dynamically supplied by SSDT */ + + Scope(\_GPE) { /* Start Scope GPE */ + /* VGA controller PME# */ + Method(_L00) { + /* Level-Triggered GPE */ + Notify(\_SB.PCI0.VGAC, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Keyboard controller PME# */ + Method(_L03) { + /* Level-Triggered GPE */ + Notify(\_SB.PCI0.LPC.KBD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.LPC.MOU, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* USB2 PME# */ + Method(_L05) { + /* Level-Triggered GPE */ + Notify (\_SB.PCI0.USB2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Slot PME# */ + Method(_L0B) { + /* Level-Triggered GPE */ + Notify (\_SB.PCI0.PCIE.SLT1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.LSIC.SLT2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* USB0 PME# */ + Method(_L0D) { + /* Level-Triggered GPE */ + Notify (\_SB.PCI0.USB0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Keyboard controller PME# */ + Method(_L10) { + /* Level-Triggered GPE */ + Notify(\_SB.PCI0.LPC.KBD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.LPC.MOU, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* PCIe PME# */ + Method(_L11) { + /* Level-Triggered GPE */ + Notify (\_SB.PCI0.NICB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.PCIE, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.NICA, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.LSIC, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + } /* End Scope GPE */ + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device (CK804) */ + Device (PCI0) + { + /* BUS0 root bus */ + + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00180001) + Name (_UID, 0x00) + + Name (HCIN, 0x00) // HC1 + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + /* Operating System Capabilities Method */ + Method(_OSC,4) + { + /* Let OS control everything */ + Return (Arg3) + } + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + External (CBST) + + /* PCI Routing Tables */ + Name (PR00, Package () { + /* PIC */ + /* ISA Bridge */ + Package (0x04) { 0x0001FFFF, 0x00, LKSM, 0x00 }, + + /* USB */ + Package (0x04) { 0x0002FFFF, 0x00, LUB0, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, LUB2, 0x00 }, + + /* SATA 0 */ + Package (0x04) { 0x0007FFFF, 0x00, LSA0, 0x00 }, + + /* SATA 1 */ + Package (0x04) { 0x0008FFFF, 0x00, LSA1, 0x00 }, + + /* NIC A (Bridge) */ + Package (0x04) { 0x000BFFFF, 0x00, LNKB, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x01, LNKC, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x02, LNKD, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x03, LNKA, 0x00 }, + + /* NIC B (Bridge) */ + Package (0x04) { 0x000CFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x03, LNKD, 0x00 }, + + /* LSI SAS Controller (Bridge) */ + Package (0x04) { 0x000DFFFF, 0x00, LNKD, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x01, LNKA, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x02, LNKB, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x03, LNKC, 0x00 }, + + /* PCI-E Slot (Bridge) */ + Package (0x04) { 0x000EFFFF, 0x00, LNKC, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x01, LNKD, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x02, LNKA, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x03, LNKB, 0x00 }, + }) + + Name (AR00, Package () { + /* APIC */ + /* ISA Bridge */ + Package (0x04) { 0x0001FFFF, 0x00, LKSM, 0x00 }, + + /* USB */ + Package (0x04) { 0x0002FFFF, 0x00, LUB0, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, LUB2, 0x00 }, + + /* SATA 0 */ + Package (0x04) { 0x0007FFFF, 0x00, LSA0, 0x00 }, + + /* SATA 1 */ + Package (0x04) { 0x0008FFFF, 0x00, LSA1, 0x00 }, + + /* NIC A (Bridge) */ + Package (0x04) { 0x000BFFFF, 0x00, LNIB, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x01, LNIC, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x02, LNND, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x03, LNIA, 0x00 }, + + /* NIC B (Bridge) */ + Package (0x04) { 0x000CFFFF, 0x00, LNIA, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x01, LNIB, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x02, LNIC, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x03, LNND, 0x00 }, + + /* LSI SAS Controller (Bridge) */ + Package (0x04) { 0x000DFFFF, 0x00, LNND, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x01, LNIA, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x02, LNIB, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x03, LNIC, 0x00 }, + + /* PCI-E Slot (Bridge) */ + Package (0x04) { 0x000EFFFF, 0x00, LNIC, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x01, LNND, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x02, LNIA, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x03, LNIB, 0x00 }, + }) + + Name (PR01, Package () { + /* PIC */ + Package (0x04) { 0x0004FFFF, 0x00, LNKA, 0x00 }, + }) + + Name (AR01, Package () { + /* APIC */ + Package (0x04) { 0x0004FFFF, 0x00, LNIA, 0x00 }, + }) + + Name (PR02, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKD, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKA, 0x00 }, + }) + + Name (AR02, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, LNIB, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNIC, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNND, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNIA, 0x00 }, + }) + + Name (PR03, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, + }) + + Name (AR03, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, LNIA, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNIB, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNIC, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNND, 0x00 }, + }) + + Name (PR04, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKD, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKC, 0x00 }, + }) + + Name (AR04, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, LNND, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNIA, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNIB, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNIC, 0x00 }, + }) + + Name (PR05, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKD, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKB, 0x00 }, + }) + + Name (AR05, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, LNIC, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNND, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNIA, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNIB, 0x00 }, + }) + + /* PCI Resource Tables */ + + Name (RSIA, ResourceTemplate () { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) {8} + }) + + Name (RSMA, ResourceTemplate () { + /* APIC */ + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {16} + }) + + Name (RSIB, ResourceTemplate () { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) {1} + }) + + Name (RSMB, ResourceTemplate () { + /* APIC */ + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {17} + }) + + Name (RSIC, ResourceTemplate () { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) {2} + }) + + Name (RSMC, ResourceTemplate () { + /* APIC */ + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {18} + }) + + Name (RSND, ResourceTemplate () { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) {13} + }) + + Name (RSMD, ResourceTemplate () { + /* APIC */ + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {19} + }) + + Name (RSS2, ResourceTemplate () + { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) + {3, 4, 5, 7, 9, 10, 11, 12, 14, 15} + }) + + Name (RSA1, ResourceTemplate () + { + /* APIC */ + IRQ (Level, ActiveLow, Shared, ) + {3, 4, 5, 6, 7, 10, 11, 12, 14, 15} + }) + + Method (_CRS, 0, Serialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods below use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + +#include "southbridge/nvidia/ck804/acpi/ck804.asl" + + /* PCI Routing Table Access */ + Method (_PRT, 0, NotSerialized) { + If (PICM) { + Return (AR00) + } Else { + Return (PR00) + } + } + + /* USB0 */ + Device (LUB0) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTQ) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTQ) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (PRSC) + } Else { + Return (RSA1) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSC(\_SB.PCI0.LPCB.INTQ)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTQ)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTQ) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTQ) + } + } + } + + /* USB2 */ + Device (LUB2) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTL) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTL) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (PRSC) + } Else { + Return (RSA1) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSC(\_SB.PCI0.LPCB.INTL)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTL)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTL) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTL) + } + } + } + + /* ISA Bridge */ + Device (LKSM) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x0C) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTK) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTK) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSA1) + } Else { + Return (RSS2) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTK)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTK)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTK) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTK) + } + } + } + + /* Bridge device link (NIC A) */ + Device (LNIA) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTA) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTA) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSMA) + } Else { + Return (RSIA) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTA)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTA)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTA) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTA) + } + } + } + + /* Bridge device link (NIC B) */ + Device (LNIB) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTB) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTB) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSMB) + } Else { + Return (RSIB) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTB)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTB)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTB) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTB) + } + } + } + + /* Bridge device link */ + Device (LNIC) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTC) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTC) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSMC) + } Else { + Return (RSIC) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTC)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTC)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTC) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTC) + } + } + } + + /* Bridge device link */ + Device (LNND) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTD) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTD) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSMD) + } Else { + Return (RSND) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTD)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTD)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTD) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTD) + } + } + } + + /* 0:02.0 CK804 USB 0 */ + Device (USB0) + { + Name (_ADR, 0x00020000) // _ADR: Address + Name(_PRW, Package () {0x0D, 0x04}) // Wake from S1-S4 + } + + /* 0:02.0 CK804 USB 2 */ + Device (USB2) + { + Name (_ADR, 0x00020001) // _ADR: Address + Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 + } + + /* 1:04.0 VGA Controller */ + Device (VGAC) + { + Name (_ADR, 0x00090000) // _ADR: Address + Name(_PRW, Package () {0x00, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR01) + } Else { + Return (PR01) + } + } + } + + /* 2:00.0 PCIe NIC A */ + Device (NICA) + { + Name (_ADR, 0x000B0000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR02) + } Else { + Return (PR02) + } + } + Device (BDC1) + { + Name (_ADR, Zero) // _ADR: Address + } + } + + /* 3:00.0 PCIe NIC B */ + Device (NICB) + { + Name (_ADR, 0x000C0000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR03) + } Else { + Return (PR03) + } + } + Device (BDC2) + { + Name (_ADR, Zero) // _ADR: Address + } + } + + /* 4:00.0 PCIe LSI SAS Controller */ + Device (LSIC) + { + Name (_ADR, 0x000D0000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR04) + } Else { + Return (PR04) + } + } + + Device (SLT2) + { + Name (_ADR, 0xFFFF) // _ADR: Address + Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 + } + } + + /* 5:00.0 PCIe x16 */ + Device (PCIE) + { + Name (_ADR, 0x000E0000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR05) + } Else { + Return (PR05) + } + } + Device (SLT1) + { + Name (_ADR, 0xFFFF) // _ADR: Address + Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 + } + } + + Device (LPC) { + Name (_HID, EisaId ("PNP0A05")) + Name (_ADR, 0x00010000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Name (_CID, EisaId ("PNP030B")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, Serialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F03")) + Name (_CID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, Serialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + + /* UART 1 */ + Device (URT1) + { + Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART + Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4 + Method (_STA, 0, NotSerialized) + { + Return (0x0f) // Always enable + } + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + } EndDependentFn() + }) + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + }) + } + } + + /* UART 2 */ + Device (URT2) + { + Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART + Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4 + Method (_STA, 0, NotSerialized) + { + Return (0x0f) // Always enable + } + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + }) + } + } + + /* Floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, Serialized) + { + Name (BUF0, ResourceTemplate () { + FixedIO (0x03F0, 0x08) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + Device (HPET) + { + Name (_HID, EisaId ("PNP0103")) + Name (CRS, ResourceTemplate () + { + Memory32Fixed (ReadOnly, + 0x00000000, + 0x00001000, + _Y02) + IRQNoFlags () {0} + IRQNoFlags () {8} + }) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._BAS, HPT1) + CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._LEN, HPT2) + Store (SHPB, HPT1) + Store (SHPL, HPT2) + Return (CRS) + } + + } + } + } + + Device (PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } + +#include "acpi/pm_ctrl.asl" + +} diff --git a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c new file mode 100644 index 0000000..9d20d76 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#include <stdlib.h> +#if CONFIG_LOGICAL_CPUS +#include <cpu/amd/multicore.h> +#endif +#include <cpu/amd/amdfam10_sysconf.h> +#include <stdlib.h> + +/* + * Global variables for MB layouts and these will be shared by irqtable, + * mptable and acpi_tables. + */ +/* busnum is default */ +unsigned char bus_ck804[6]; +unsigned apicid_ck804; + +/* Here you only need to set value in pci1234 for HT-IO that could be +installed or not You may need to preset pci1234 for HTIO board, please +refer to src/northbridge/amd/amdfam10/get_pci1234.c for detail */ +static u32 pci1234x[] = { + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, + }; + + +/* HT Chain device num, actually it is unit id base of every ht device +in chain, assume every chain only have 4 ht device at most */ + +static unsigned hcdnx[] = { + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, +}; + +extern void get_pci1234(void); + +static unsigned get_bus_conf_done = 0; + +void get_bus_conf(void) +{ + unsigned apicid_base, sbdn; + device_t dev; + int i; + + if (get_bus_conf_done == 1) + return; /* Do it only once. */ + + get_bus_conf_done = 1; + + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_pci1234(); + + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sbdn = sysconf.sbdn; + + for (i = 0; i < 6; i++) + bus_ck804[i] = 0; + + /* CK804 */ + dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x09, 0)); + if (dev) { + bus_ck804[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804[2]++; + } else { + printk + (BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x09); + bus_ck804[1] = 2; + bus_ck804[2] = 3; + } + + for (i = 2; i < 6; i++) { + dev = dev_find_slot(bus_ck804[0], + PCI_DEVFN(sbdn + 0x0b + i - 2, 0)); + if (dev) { + bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_ck804[0], sbdn + 0x0b + i - 2); + } + } + + if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { + apicid_base = get_apicid_base(1); + printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==1: apicid_base: %08x\n", apicid_base); + } + else { + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==0: apicid_base: %08x\n", apicid_base); + } + apicid_ck804 = apicid_base + 0; +} diff --git a/src/mainboard/asus/kfsn4-dre/irq_tables.c b/src/mainboard/asus/kfsn4-dre/irq_tables.c new file mode 100644 index 0000000..437961c --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/irq_tables.c @@ -0,0 +1,184 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// WARNING +// These tables are INVALID for this mainboard! +// The ACPI tables are correct; a backport to these PIR tables is needed... + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam10_sysconf.h> + +extern unsigned char bus_isa; +extern unsigned char bus_ck804[6]; + + +/** + * Add one line to IRQ table. + */ +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, + uint8_t devfn, uint8_t link0, uint16_t bitmap0, + uint8_t link1, uint16_t bitmap1, uint8_t link2, + uint16_t bitmap2, uint8_t link3, uint16_t bitmap3, + uint8_t slot, uint8_t rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +/** + * Create the IRQ routing table. + * Values are derived from getpir generated code. + */ +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + unsigned slot_num, sbdn; + uint8_t *v, sum = 0; + int i; + + /* get_bus_conf() will find out all bus num and APIC that share with + * mptable.c and mptable.c. + */ + get_bus_conf(); + sbdn = sysconf.sbdn; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000. */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (uint8_t *)(addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + pirq->rtr_bus = bus_ck804[0]; + pirq->rtr_devfn = ((sbdn + 9) << 3) | 0; + pirq->exclusive_irqs = 0x828; + pirq->rtr_vendor = 0x10de; + pirq->rtr_device = 0x005c; + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* Slot1 PCIE 16x */ + write_pirq_info(pirq_info, bus_ck804[1], (0 << 3) | 0, 0x3, 0xdeb8, 0x4, + 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0); + pirq_info++; + slot_num++; + + + /* Slot2 PCIE 1x */ + write_pirq_info(pirq_info, bus_ck804[2], (0 << 3) | 0, 0x4, 0xdeb8, 0x1, + 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 5, 0); + pirq_info++; + slot_num++; + + /* Slot3 PCIE 1x */ + write_pirq_info(pirq_info, bus_ck804[3], (0 << 3) | 0, 0x1, 0xdeb8, 0x2, + 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 6, 0); + pirq_info++; + slot_num++; + + /* Slot4 PCIE 4x */ + write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0, 0x2, + 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 7, 0); + pirq_info++; + slot_num++; + + /* Slot5 - Slot7 PCI */ + for (i = 0; i < 3; i++) { + write_pirq_info(pirq_info, bus_ck804[5], (0 << (6 + i)) | 0, + ((i + 0) % 4) + 1, 0xdeb8, + ((i + 1) % 4) + 1, 0xdeb8, + ((i + 2) % 4) + 1, 0xdeb8, + ((i + 3) % 4) + 1, 0xdeb8, i, 0); + pirq_info++; + slot_num++; + } + + /* PCI bridge */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 9) << 3) | 0, 0x1, + 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0, 0); + pirq_info++; + slot_num++; + + /* SMBus */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 1) << 3) | 0, 0x2, + 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + /* USB */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 2) << 3) | 0, 0x1, + 0xdeb8, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + /* SATA */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 7) << 3) | 0, 0x1, + 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + /* SATA */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 8) << 3) | 0, 0x1, + 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + if (sum != pirq->checksum) + pirq->checksum = sum; + + printk(BIOS_INFO, "done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/asus/kfsn4-dre/mptable.c b/src/mainboard/asus/kfsn4-dre/mptable.c new file mode 100644 index 0000000..46ae594 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/mptable.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// WARNING +// These tables are INCOMPLETE for this mainboard! +// The ACPI tables are correct; a backport to these MP tables is needed... + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam10_sysconf.h> + +extern unsigned char bus_ck804[6]; +extern unsigned apicid_ck804; + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + unsigned sbdn; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + smp_write_processors(mc); + + get_bus_conf(); + sbdn = sysconf.sbdn; + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + { + device_t dev; + struct resource *res; + + dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_1); + if (res) { + smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); + } + + /* Initialize interrupt mapping. */ + + /* + LPC bridge PCI config registers: + + 0x7c:0x0000ffff + - bitmap of masked pci irqs? + - PIRQ[ABCD] possibly? + + 0x7c:0x00f00000 + - sata at f8 - port 1 + + 0x7c:0x0f000000 + - sata at f7 - port 1 + + 0x80:0xf0000000 + - sata at f7 - port 0 + + 0x80:0x0f000000 + - sata at f8 - port 0 + + 0x80:0x0000f000 + - EHCI + + 0x84:0x00000f00 + - NIC + + 0x84:0x0000000f + - OHCI + + known values of nibbles: + + 0 - unrouted? + 1 - irq 23 + 8 - irq 20 + c - irq 12 + d - irq 21 + e - irq 14 + f - irq 15 + */ + + // Enable interrupts for commonly used devices (USB, SATA, etc.) + pci_write_config32(dev, 0x7c, 0x0d800018); + pci_write_config32(dev, 0x80, 0xd8002009); + pci_write_config32(dev, 0x84, 0x00000001); + } + } + + mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0); + + // Onboard ck804 smbus + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804, + 0xa); + + // Onboard ck804 USB 1.1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804, + 0x15); + + // Onboard ck804 USB 2 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804, + 0x14); + + // Onboard ck804 SATA 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804, + 0x17); + + // Onboard ck804 SATA 1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804, + 0x16); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + mptable_lintsrc(mc, bus_ck804[0]); + + /* There is no extension information... */ + + /* Compute the checksums. */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/kfsn4-dre/resourcemap.c b/src/mainboard/asus/kfsn4-dre/resourcemap.c new file mode 100644 index 0000000..5ba0b01 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/resourcemap.c @@ -0,0 +1,284 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static void setup_mb_resource_map(void) +{ + static const unsigned int register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [31:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000, + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000, + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> Nvidia CK 804 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independent of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration region i + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> Nvidia CK 804 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + + }; + + int max; + max = ARRAY_SIZE(register_values); + setup_resource_map(register_values, max); +} diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c new file mode 100644 index 0000000..f38cc72 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -0,0 +1,394 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define FAM10_SCAN_PCI_BUS 0 +#define FAM10_ALLOCATE_IO_RANGE 1 + +unsigned int get_sbdn(unsigned bus); + +#include <stdint.h> +#include <string.h> +#include <reset.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <lib.h> +#include <spd.h> +#include <cpu/amd/model_10xxx_rev.h> +#include "southbridge/nvidia/ck804/early_smbus.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> +#include "lib/delay.c" +#include <cpu/x86/lapic.h> +#include "northbridge/amd/amdfam10/reset_test.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627thg/w83627thg.h> +#include <cpu/x86/bist.h> +// #include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdfam10/debug.c" +#include "northbridge/amd/amdfam10/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) + +static void activate_spd_rom(const struct mem_controller *ctrl); + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include <northbridge/amd/amdfam10/amdfam10.h> +#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" +#include "northbridge/amd/amdfam10/pci.c" +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" + +/* + * Avoid crash (complete with severe memory corruption!) during initial CAR boot + * in ck804_early_setup_x(). + * Interestingly once the system is fully booted into Linux this can be set, but + * not before! Apparently something isn't initialized but the amount of effort + * required to fix this is non-negligible and of unknown real-world benefit + */ +#define CK804_SKIP_PCI_REG_78_INIT 1 + +#define CK804_MB_SETUP \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/ + +#include <southbridge/nvidia/ck804/early_setup_ss.h> +#include "southbridge/nvidia/ck804/early_setup_car.c" +#include <cpu/amd/microcode.h> + +#include "cpu/amd/model_10xxx/init_cpus.c" +#include "northbridge/amd/amdfam10/early_ht.c" + +#define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3) + +/** + * @brief Get SouthBridge device number + * @param[in] bus target bus number + * @return southbridge device number + */ +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus); + return (dev >> 15) & 0x1f; +} + +/* + * ASUS KFSN4-DRE specific SPD enable/disable magic. + * + * Setting CK804 GPIO43 and GPIO44 to 0 and 0 respectively will make the + * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD + * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which + * will make RAM init fail. + * + * Disable SPD access after RAM init to allow access to standard SMBus/I2C offsets + * which is required e.g. by lm-sensors. + */ + +#define CK804_BOARD_BOOT_BASE_UNIT_UID 1 + +static const unsigned int ctrl_conf_enable_spd_node0[] = { + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/ +}; + +static const unsigned int ctrl_conf_enable_spd_node1[] = { + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x01),/* W3,GPIO44, U6 input S1*/ +}; + +static const unsigned int ctrl_conf_disable_spd[] = { + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x01),/* W2,GPIO43, U6 input S0*/ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/ +}; + +static const unsigned int ctrl_conf_fix_pci_numbering[] = { + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x44), ~(0x00010000), 0x00000000, /* Force CK804 to start its internal device numbering (Base Unit ID) at 0 instead of the power-on default of 1 */ +}; + +static const unsigned int ctrl_conf_enable_msi_mapping[] = { + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */ +}; + +static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id) +{ + unsigned busn[4], io_base[4]; + int i, ck804_num = 0; + + for (i = 0; i < 4; i++) { + u32 id; + device_t dev; + if (i == 0) /* SB chain */ + dev = PCI_DEV(i * 0x40, bus_unit_id, 0); + else + dev = 0; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (id == 0x005e10de) { + busn[ck804_num] = i * 0x40; + io_base[ck804_num] = i * 0x4000; + ck804_num++; + } + } + + if (ck804_num < 1) + printk(BIOS_WARNING, "CK804 not found at device base unit id %02x!\n", bus_unit_id); + + ck804_early_set_port(ck804_num, busn, io_base); + + setup_resource_map_x_offset(values, + size, + PCI_DEV(0, bus_unit_id, 0), io_base[0]); + + ck804_early_clear_port(ck804_num, busn, io_base); +} + +static void sio_setup(void) +{ + u32 dword; + u8 byte; + + /* Subject decoding */ + byte = pci_read_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b, byte); + + /* LPC Positive Decode 0 */ + dword = pci_read_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0); + /* Serial 0, Serial 1 */ + dword |= (1 << 0) | (1 << 1); + pci_write_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0, dword); +} + +static const uint8_t spd_addr[] = { + // Node 0 + RC00, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, + // Node 1 + RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, +}; + +static void activate_spd_rom(const struct mem_controller *ctrl) { + printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); + if (ctrl->node_id == 0) { + printk(BIOS_DEBUG, "enable_spd_node0()\n"); + ck804_control(ctrl_conf_enable_spd_node0, ARRAY_SIZE(ctrl_conf_enable_spd_node0), CK804_DEVN_BASE); + } + else if (ctrl->node_id == 1) { + printk(BIOS_DEBUG, "enable_spd_node1()\n"); + ck804_control(ctrl_conf_enable_spd_node1, ARRAY_SIZE(ctrl_conf_enable_spd_node1), CK804_DEVN_BASE); + } +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + struct sys_info *sysinfo = &sysinfo_car; + + u32 bsp_apicid = 0, val, wants_reset; + msr_t msr; + + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + set_bsp_node_CHtExtNodeCfgEn(); + enumerate_ht_chain(); + sio_setup(); + } + + post_code(0x30); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + post_code(0x32); + + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + if (CONFIG_MAX_PHYSICAL_CPUS != 2) + printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket board!\n", CONFIG_MAX_PHYSICAL_CPUS); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + /* Setup sysinfo defaults */ + set_sysinfo_in_ram(0); + + update_microcode(val); + + post_code(0x33); + + cpuSetAMDMSR(); + post_code(0x34); + + amd_ht_init(sysinfo); + post_code(0x35); + + /* Setup nodes PCI space and start core 0 AP init. */ + finalize_node_setup(sysinfo); + + /* Setup any mainboard PCI settings etc. */ + setup_mb_resource_map(); + post_code(0x36); + + /* wait for all the APs core0 started by finalize_node_setup. */ + /* FIXME: A bunch of cores are going to start output to serial at once. + * It would be nice to fix up prink spinlocks for ROM XIP mode. + * I think it could be done by putting the spinlock flag in the cache + * of the BSP located right after sysinfo. + */ + wait_all_core0_started(); + + if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); + start_other_cores(); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + } + + printk(BIOS_DEBUG, "set_ck804_base_unit_id()\n"); + ck804_control(ctrl_conf_fix_pci_numbering, ARRAY_SIZE(ctrl_conf_fix_pci_numbering), CK804_BOARD_BOOT_BASE_UNIT_UID); + + post_code(0x38); + + if (IS_ENABLED(CONFIG_SET_FIDVID)) { + msr = rdmsr(0xc0010071); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); + + post_code(0x39); + + if (!warm_reset_detect(0)) { // BSP is node 0 + init_fidvid_bsp(bsp_apicid, sysinfo->nodes); + } else { + init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + } + + post_code(0x3A); + + /* show final fid and vid */ + msr=rdmsr(0xc0010071); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); + } + + init_timer(); // Need to use TMICT to synconize FID/VID + + wants_reset = ck804_early_setup_x(); + + /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ + if (!warm_reset_detect(0)) { + printk(BIOS_INFO, "...WARM RESET...\n\n\n"); + soft_reset(); + die("After soft_reset_x - shouldn't see this message!!!\n"); + } + + if (wants_reset) { + printk(BIOS_DEBUG, "ck804_early_setup_x wanted additional reset!\n"); + } + + post_code(0x3B); + + /* It's the time to set ctrl in sysinfo now; */ + printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + post_code(0x3D); + + printk(BIOS_DEBUG, "enable_smbus()\n"); + enable_smbus(); + +#if 0 + /* FIXME + * After the AMD K10 code has been converted to use + * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block + */ + if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) { + dump_spd_registers(&cpu[0]); + dump_smbus_registers(); + } +#endif + + post_code(0x40); + + printk(BIOS_DEBUG, "raminit_amdmct()\n"); + raminit_amdmct(sysinfo); + post_code(0x41); + + printk(BIOS_DEBUG, "disable_spd()\n"); + ck804_control(ctrl_conf_disable_spd, ARRAY_SIZE(ctrl_conf_disable_spd), CK804_DEVN_BASE); + + printk(BIOS_DEBUG, "enable_msi_mapping()\n"); + ck804_control(ctrl_conf_enable_msi_mapping, ARRAY_SIZE(ctrl_conf_enable_msi_mapping), CK804_DEVN_BASE); + + /* Initialize GPIO */ + /* Access SuperIO GPI03 logical device */ + uint16_t port = GPIO3_DEV >> 8; + outb(0x87, port); + outb(0x87, port); + pnp_set_logical_device(GPIO3_DEV); + /* Set GP37 (power LED) to output */ + pnp_write_config(GPIO3_DEV, 0xf0, 0x7f); + /* Set GP37 (power LED) on */ + pnp_write_config(GPIO3_DEV, 0xf1, 0x80); + /* Set pin 67 multiplex to GP37 */ + uint8_t cr2c = pnp_read_config(GPIO3_DEV, 0x2c); + pnp_write_config(GPIO3_DEV, 0x2c, (cr2c & 0xf3) | 0x04); + /* Restore default SuperIO access */ + outb(0xaa, port); + + post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. + post_code(0x43); // Should never see this post code. +} + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + return 0; +} diff --git a/src/mainboard/asus/kfsn4-dre/spd_notes.txt b/src/mainboard/asus/kfsn4-dre/spd_notes.txt new file mode 100644 index 0000000..ff49c18 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/spd_notes.txt @@ -0,0 +1,50 @@ +==================================================================================================== +SPD mux +==================================================================================================== + +DIMM_A1 SDA signal traced to U6 pin 1 +Destructive testing of failed board (removal of U7 northbridge!) yielded the following information: +U6 S0 <--> U7 W2 +U6 S1 <--> U7 W3 + +Proprietary BIOS enables the SPD during POST with: +S0: LOW +S1: LOW + +then temporarily switches to: +S0: LOW +S1: HIGH + +then switches to runtime mode with: +S0: HIGH +S1: LOW + +After probing with a custom GPIO-flipping tool under Linux the following GPIO mappings were found: +CK804 pin W2 <--> GPIO43 +CK804 pin W3 <--> GPIO44 + +==================================================================================================== +Other hardware +==================================================================================================== + +Power LED (-) is connected to U15 (SuperIO) pin 64 via U4 pins 5,6 and a small MOSFET +ID LED (-) is connected to a ??? via U4 pins 1,2,3,4 and U77 pins 5,6 +It appears that setting U15 (SuperIO) pin 88 LOW will override the ID LED and force it ON + +PCIe slot WAKE# connects to U7 pin E23 (PCIE_WAKE#) + +CPU_WARN1 is driven by (???) via a simple buffer (U13 pin 10) +MEM_WARN1 is driven by U7 pin AD3 (CPUVDD_EN) via a simple buffer (U101 pin 3) + +U7 pin AK3 is disconnected (routed to unpopulated capacitor/resistor) +PU1 pin 37 (VDDPWRGD) drives U7 pin AJ4 (CPU_VLD) +A small MOSFET directly above another small MOSFET directly above the right-hand edge of the PCIe slot drives U7 pin AK5 (HT_VLD) + +When > Barcelona CPU installed on PCB rev 1.04G: +U7 pin AK4 (MEM_VLD): HIGH +PU1 pin 37: LOW +U7 pin AK5: LOW + +HyperTransport 1.2V supply appears to be generated by a linear regulator containing Q191 and downconverting the CK804 1.5V supply +The enable pin appears to be tied to AUX_PANEL pin 1 (+5VSB) via a resistor +Through two MOSFETs the HT supply enable pin is tied to U7 pin AE3 (HTVDD_EN)

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Patch set updated for coreboot: aebd51c device/device.c: Correct PCI register space location
by Timothy Pearson 28 Jan '15

28 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8261 -gerrit commit aebd51c64d64413a82ddf59ef4179a7fdd173fed Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:20:56 2015 -0600 device/device.c: Correct PCI register space location Fix the incorrect PCI register space location causing corruption with more than ~3.5GB physical RAM on AMD Family 10h systems. Change-Id: I66d1bfa1e977a6b492c1909079087a801c7e6a3a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 51cfee7..eaef7ba 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -677,6 +677,11 @@ static void amdfam10_domain_read_resources(device_t dev) res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ + msr_t msr = rdmsr(TOP_MEM); + u64 tom = msr.lo; + ram_resource(dev, 7, 0, tom >> 10); #endif }

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Patch merged into coreboot/master: b871687 nvidia/ck804: Add ability to override CK804 base unit ID
by gerrit＠coreboot.org 28 Jan '15

28 Jan '15

the following patch was just integrated into master: commit b8716879917c420d9e7e2618e48b1411a0c6bcc8 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Jan 24 13:45:52 2015 -0600 nvidia/ck804: Add ability to override CK804 base unit ID Change-Id: Ic1b35b6bdd9c6d9ab672242e40b73aff1d626e81 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8273 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> See http://review.coreboot.org/8273 for details. -gerrit

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Patch merged into coreboot/master: 6300b03 amd/amdfam10: Add runtime ACPI _PSS generation
by gerrit＠coreboot.org 28 Jan '15

28 Jan '15

the following patch was just integrated into master: commit 6300b034143cab98d472276054de2781eb3ce97a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Jan 26 17:53:22 2015 -0600 amd/amdfam10: Add runtime ACPI _PSS generation Skeleton and ACPI generator interface taken from model_fxx powernow_acpi.c Small portions of FIDVID MSR code taken from model_10xxx fidvid.c Nearly completely rewritten for the P-state-based K10 CPU TEST: KFSN4-DRE with dual Opteron 8356 CPUs Verified CPU per-core dynamic state change with system load Verified reported P-state count and frequencies Stress-tested each CPU (all cores simultaneously) to verify proper P0 transition and configuration. Change-Id: Icf620ec96a3f163b62d96b5988184996641dd439 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8284 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8284 for details. -gerrit

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Patch merged into coreboot/master: e916201 nvidia/ck804: Fix FTBFS with AMD Family 10h systems
by gerrit＠coreboot.org 28 Jan '15

28 Jan '15

the following patch was just integrated into master: commit e9162010049ce6135e67c9a3a11ddfdf8218a7fd Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:29:46 2015 -0600 nvidia/ck804: Fix FTBFS with AMD Family 10h systems The build failure stems from a missing function being called via a chain including setup_ss_table(), set_ht_link_ck804(), and st_ht_link_buffer_counts_chain(); the latter function is only available in the AMD K8 code. It appears that a bunch of K8-specific code snuck into the CK804 and MCP55 southbridge code in GIT commit 968bbe89 and GIT commit d4b278c0. Change-Id: I85d005edba44c503c49917d4b928e5c9c5900059 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8269 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8269 for details. -gerrit

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Patch merged into coreboot/master: 02112bd nvidia/ck804: Add ability to enable/disable PCIe PME# wake events
by gerrit＠coreboot.org 28 Jan '15

28 Jan '15

the following patch was just integrated into master: commit 02112bd280b3dbf5f5950e3a6e0c1ad83e8a8cc1 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Jan 26 02:15:57 2015 -0600 nvidia/ck804: Add ability to enable/disable PCIe PME# wake events Change-Id: Ie2937dd220464e3b168aa8a50a57c03b6258c189 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8283 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8283 for details. -gerrit

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coreboot-gerrit January 2015