New patch to review for coreboot: 8b16a9d fsp_baytrail: Get FSP reserved memory from the FSP HOB list
Martin Roth (gaumless@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8308
-gerrit
commit 8b16a9d9c0e6b32de6c685329e64c0a1247de194 Author: Martin Roth gaumless@gmail.com Date: Fri Jan 30 20:56:05 2015 -0700
fsp_baytrail: Get FSP reserved memory from the FSP HOB list
Because the pointer to the FSP HOB list is now being saved, we can use that to find the top of usable memory. This eliminates the need to hardcode the size of the FSP reserved memory area.
Tested on minnowboard max for baytrail.
The HOB structure used does not seem to be present for the rangeley or ivybridge/pantherpoint FSPs. At the very least, the GUID is not documented in the integration guides.
Change-Id: I643e57655f55bfada60075b55aad2ce010ec4f67 Signed-off-by: Martin Roth gaumless@gmail.com --- src/drivers/intel/fsp/fsp_util.c | 19 +++++++++++++++++++ src/drivers/intel/fsp/fsp_util.h | 9 +++++++-- src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h | 2 -- src/soc/intel/fsp_baytrail/memmap.c | 15 +++++++-------- src/soc/intel/fsp_baytrail/northcluster.c | 7 +------ 5 files changed, 34 insertions(+), 18 deletions(-)
diff --git a/src/drivers/intel/fsp/fsp_util.c b/src/drivers/intel/fsp/fsp_util.c index 0844b37..b59330f 100644 --- a/src/drivers/intel/fsp/fsp_util.c +++ b/src/drivers/intel/fsp/fsp_util.c @@ -195,6 +195,25 @@ void * find_saved_temp_mem(void *hob_list_ptr) return (void *) ((char *) saved_mem_hob + sizeof(EFI_HOB_GUID_TYPE)); }
+/** @brief locates the HOB containing the location of the fsp reserved mem area + * + * @param hob_list_ptr pointer to the start of the hob list + * @return pointer to the start of the FSP reserved memory or NULL if not found. + */ +void * find_fsp_reserved_mem(void *hob_list_ptr) +{ + EFI_GUID fsp_reserved_guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; + EFI_HOB_RESOURCE_DESCRIPTOR *fsp_reserved_mem = + (EFI_HOB_RESOURCE_DESCRIPTOR *) find_hob_by_guid( + hob_list_ptr, &fsp_reserved_guid); + + if (fsp_reserved_mem == NULL) + return NULL; + + return (void *)((uintptr_t)fsp_reserved_mem->PhysicalStart); +} + + #ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */
void print_fsp_info(void) { diff --git a/src/drivers/intel/fsp/fsp_util.h b/src/drivers/intel/fsp/fsp_util.h index a39f5a2..8b86ee9 100644 --- a/src/drivers/intel/fsp/fsp_util.h +++ b/src/drivers/intel/fsp/fsp_util.h @@ -20,6 +20,9 @@ #ifndef FSP_UTIL_H #define FSP_UTIL_H
+#define SIG_32_BIT(a,b,c,d) ((a<<0)|(b<<8)|(c<<16)|(d<<24)) +#define SIG_64_BIT(a,b,c,d,e,f,g,h) ((u64)SIG_32_BIT(a,b,c,d) | (u64)SIG_32_BIT(e,f,g,h)<<32) + #include <chipset_fsp_util.h> #include "fsp_values.h"
@@ -38,6 +41,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, FSP_INFO_HEADER *fsp_ptr); void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr); void * find_saved_temp_mem(void *hob_list_ptr); +void * find_fsp_reserved_mem(void *hob_list_ptr);
/* functions in hob.c */ void print_hob_mem_attributes(void *Hobptr); @@ -66,7 +70,7 @@ void printguid(EFI_GUID *guid);
#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) #define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) +#define MRC_DATA_SIGNATURE SIG_32_BIT('M','R','C','D')
struct mrc_data_container { u32 mrc_signature; // "MRCD" @@ -89,7 +93,8 @@ void update_mrc_cache(void *unused); #define FSP_IMAGE_ID_LOC 16 #define FSP_IMAGE_BASE_LOC 28
-#define FSP_SIG 0x48505346 /* 'FSPH' */ +#define FSP_SIG SIG_32_BIT('F','S','P','H') +#define FIRMWARE_VOLUME_SIGNATURE SIG_32_BIT('_','F','V','H')
#define ERROR_NO_FV_SIG 1 #define ERROR_NO_FFS_GUID 2 diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h index 1f4fa74..29309bf 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h @@ -32,8 +32,6 @@ #include <fspvpd.h> #include <azalia.h>
-#define FSP_RESERVE_MEMORY_SIZE 0x200000 - #define FSP_INFO_HEADER_GUID \ { \ 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c index 615916b..8a10ac8 100644 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ b/src/soc/intel/fsp_baytrail/memmap.c @@ -29,18 +29,17 @@ uintptr_t smm_region_start(void) return (iosf_bunit_read(BUNIT_SMRRL) << 20); }
-/* - * Calculate the top of usable (low) DRAM. - * The FSP's reserved memory sits just below the SMM region, - * allowing calculation of the top of usable memory. +/** @brief get the top of usable low memory from the FSP's HOB list + * + * The FSP's reserved memory sits just below the SMM region. The memory + * region below it is usable memory. * * The entire memory map is shown in northcluster.c + * + * @return pointer to the first byte of reserved memory */
void *cbmem_top(void) { - uintptr_t tom = smm_region_start(); - if (!tom) - tom = iosf_bunit_read(BUNIT_BMBOUND); - return (void *) tom - FSP_RESERVE_MEMORY_SIZE; + return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 838e554..b288388 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -149,8 +149,7 @@ static void mc_add_dram_resources(device_t dev) uint32_t fsp_mem_base = 0;
GetHighMemorySize(&highmem_size); - GetLowMemorySize(&fsp_mem_base); - + fsp_mem_base=(uint32_t)cbmem_top();
bmbound = iosf_bunit_read(BUNIT_BMBOUND); bsmmrrl = iosf_bunit_read(BUNIT_SMRRL) << 20; @@ -162,10 +161,6 @@ static void mc_add_dram_resources(device_t dev)
printk(BIOS_DEBUG, "FSP memory location: 0x%x\nFSP memory size: %dM\n", fsp_mem_base, (bsmmrrl - fsp_mem_base) >> 20); - - if ((bsmmrrl - fsp_mem_base ) != FSP_RESERVE_MEMORY_SIZE) - printk(BIOS_WARNING, "Warning: Fsp memory size does not match " - "expected memory size (%x).\n", FSP_RESERVE_MEMORY_SIZE); }
printk(BIOS_INFO, "Available memory below 4GB: 0x%08x (%dM)\n",
-
Martin Roth