coreboot-gerrit June 2014

coreboot-gerrit@coreboot.org

1 participants
922 discussions

New patch to review for coreboot: 42f9ebe southbridge/dmp/vortex86ex: Incorrect usage of logical vs. bitwise 'and'
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6153 -gerrit commit 42f9ebe9fcbd61f0081ce19410f3e08aabce8b2d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 18:30:06 2014 +1000 southbridge/dmp/vortex86ex: Incorrect usage of logical vs. bitwise 'and' We should be using a logical bitwise 'and' here with the LSB and CONFIG_ boolean. Spotted by Clang. Change-Id: I8f822fd2647f1912906064363dc452b25a0eecf9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/dmp/vortex86ex/southbridge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index c9b10b6..e66d350 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -231,7 +231,7 @@ static void pci_routing_fixup(struct device *dev) unsigned char irqs[4] = { OHCII_IRQ, EHCII_IRQ, 0, 0 }; pci_assign_irqs(0, 0xa, irqs); } - if (CONFIG_IDE_NATIVE_MODE && PIDE_IRQ) { + if (CONFIG_IDE_NATIVE_MODE & PIDE_IRQ) { /* IDE in native mode, setup PCI IRQ. */ unsigned char irqs[4] = { PIDE_IRQ, 0, 0, 0 }; pci_assign_irqs(0, 0xc, irqs);

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New patch to review for coreboot: b3f48d2 vendorcode/amd/agesa: Spell *sync* without *h* in comments
by Paul Menzel 28 Jun '14

28 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6152 -gerrit commit b3f48d226e15432797035a78cbe8cd085de13d82 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Jun 28 09:06:57 2014 +0200 vendorcode/amd/agesa: Spell *sync* without *h* in comments Run the following command to fix all occurrences in vendor code. $ git grep -l "synch " | xargs sed -i 's/synch /sync /g' Change-Id: I8395cd289c8d713cf89f186cc9bbc4c478dcb743 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h | 2 +- src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h | 2 +- src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h | 2 +- src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h | 2 +- src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h | 2 +- src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h | 2 +- src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h | 2 +- src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h | 2 +- src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h | 2 +- src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h | 2 +- src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h | 2 +- src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h index 475272d..bc4c5c3 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h @@ -182,7 +182,7 @@ typedef enum { } TABLE_CORE_SELECTOR; // Initializer bit pattern values for platform features. -// Keep in synch with the PLATFORM_FEATURES struct! +// Keep in sync with the PLATFORM_FEATURES struct! // The 5 control flow modes. #define AMD_PF_NFCM BIT0 diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h index 5059dce..79dd2b1 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h +++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h @@ -55,7 +55,7 @@ /// For event ::HT_EVENT_HW_SYNCFLOOD typedef struct { UINT32 Node; ///< The Node on which observed - UINT32 Link; ///< The Link on that Node which reported synch flood + UINT32 Link; ///< The Link on that Node which reported sync flood UINT32 Reserved1; ///< Reserved. UINT32 Reserved2; ///< Reserved. } HT_EVENT_DATA_HW_SYNCFLOOD; diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h index cb27aee..cde716f 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h @@ -186,7 +186,7 @@ typedef enum { } TABLE_CORE_SELECTOR; // Initializer bit pattern values for platform features. -// Keep in synch with the PLATFORM_FEATURES struct! +// Keep in sync with the PLATFORM_FEATURES struct! // The 5 control flow modes. #define AMD_PF_NFCM BIT0 diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h index b3b4a90..bc62f8a 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h +++ b/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h @@ -55,7 +55,7 @@ /// For event ::HT_EVENT_HW_SYNCFLOOD typedef struct { UINT32 Node; ///< The Node on which observed - UINT32 Link; ///< The Link on that Node which reported synch flood + UINT32 Link; ///< The Link on that Node which reported sync flood UINT32 Reserved1; ///< Reserved. UINT32 Reserved2; ///< Reserved. } HT_EVENT_DATA_HW_SYNCFLOOD; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h index 76ec4b0..24d2209 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h @@ -187,7 +187,7 @@ typedef enum { } TABLE_CORE_SELECTOR; // Initializer bit pattern values for platform features. -// Keep in synch with the PLATFORM_FEATURES struct! +// Keep in sync with the PLATFORM_FEATURES struct! // The 5 control flow modes. #define AMD_PF_NFCM BIT0 diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h index f7f846a..fd2267b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h +++ b/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h @@ -56,7 +56,7 @@ /// For event ::HT_EVENT_HW_SYNCFLOOD typedef struct { UINT32 Node; ///< The Node on which observed - UINT32 Link; ///< The Link on that Node which reported synch flood + UINT32 Link; ///< The Link on that Node which reported sync flood UINT32 Reserved1; ///< Reserved. UINT32 Reserved2; ///< Reserved. } HT_EVENT_DATA_HW_SYNCFLOOD; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h index 16c3baa..e3388ce 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h @@ -187,7 +187,7 @@ typedef enum { } TABLE_CORE_SELECTOR; // Initializer bit pattern values for platform features. -// Keep in synch with the PLATFORM_FEATURES struct! +// Keep in sync with the PLATFORM_FEATURES struct! // The 5 control flow modes. #define AMD_PF_NFCM BIT0 diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h index 9e28445..457cc02 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h +++ b/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h @@ -56,7 +56,7 @@ /// For event ::HT_EVENT_HW_SYNCFLOOD typedef struct { UINT32 Node; ///< The Node on which observed - UINT32 Link; ///< The Link on that Node which reported synch flood + UINT32 Link; ///< The Link on that Node which reported sync flood UINT32 Reserved1; ///< Reserved. UINT32 Reserved2; ///< Reserved. } HT_EVENT_DATA_HW_SYNCFLOOD; diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c index d154e2f..9448a7a 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c @@ -419,7 +419,7 @@ MemNAfterDQSTrainingOr ( MemNSwitchDCTNb (NBPtr, Dct); if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { if (!(NBPtr->DctCachePtr->Is__x4)) { - // Only synch when 1D training has been performed or training with x8 DIMMs + // Only sync when 1D training has been performed or training with x8 DIMMs for (Dimm = 0; Dimm < 4; Dimm++) { for (Byte = 0; Byte < 9; Byte++) { Dly = (UINT16) MemNGetTrainDlyNb (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, Byte)); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h index c21cb9c..48c5452 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h @@ -186,7 +186,7 @@ typedef enum { } TABLE_CORE_SELECTOR; // Initializer bit pattern values for platform features. -// Keep in synch with the PLATFORM_FEATURES struct! +// Keep in sync with the PLATFORM_FEATURES struct! // The 5 control flow modes. #define AMD_PF_NFCM BIT0 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h index 6507165..74ea10d 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h @@ -55,7 +55,7 @@ /// For event ::HT_EVENT_HW_SYNCFLOOD typedef struct { UINT32 Node; ///< The Node on which observed - UINT32 Link; ///< The Link on that Node which reported synch flood + UINT32 Link; ///< The Link on that Node which reported sync flood UINT32 Reserved1; ///< Reserved. UINT32 Reserved2; ///< Reserved. } HT_EVENT_DATA_HW_SYNCFLOOD; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h index 1f6341a..7696047 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h @@ -204,7 +204,7 @@ typedef enum { #define PERFORM_EARLY_ANY_CONDITION (PERFORM_EARLY_WARM_RESET | PERFORM_EARLY_COLD_BOOT) // Initializer bit pattern values for platform features. -// Keep in synch with the PLATFORM_FEATURES struct! +// Keep in sync with the PLATFORM_FEATURES struct! // The 5 control flow modes. #define AMD_PF_NFCM BIT0 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h index 58d0cbe..0c208cb 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h @@ -55,7 +55,7 @@ /// For event ::HT_EVENT_HW_SYNCFLOOD typedef struct { UINT32 Node; ///< The Node on which observed - UINT32 Link; ///< The Link on that Node which reported synch flood + UINT32 Link; ///< The Link on that Node which reported sync flood UINT32 Reserved1; ///< Reserved. UINT32 Reserved2; ///< Reserved. } HT_EVENT_DATA_HW_SYNCFLOOD; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c index be956bc..23969b3 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c @@ -403,7 +403,7 @@ MemNAfterDQSTrainingKB ( MemNSwitchDCTNb (NBPtr, Dct); if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { if (!(NBPtr->DctCachePtr->Is2Dx4)) { - // Only synch when 1D training has been performed or 2D training with x8 DIMMs + // Only sync when 1D training has been performed or 2D training with x8 DIMMs for (Dimm = 0; Dimm < 4; Dimm++) { for (Byte = 0; Byte < 9; Byte++) { Dly = (UINT16) MemNGetTrainDlyNb (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, Byte));

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New patch to review for coreboot: 3fe6d5b northbridge/amd: Spell *sync* without *h* in comments
by Paul Menzel 28 Jun '14

28 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6151 -gerrit commit 3fe6d5b31f83f682331b8481c2f821c9a85168a2 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Jun 28 09:06:57 2014 +0200 northbridge/amd: Spell *sync* without *h* in comments Run the following command to fix all occurrences in `src/northbridge`. $ git grep -l "synch " src/northbridge | xargs sed -i 's/synch /sync /g' Change-Id: I630aadae77524c3ab2171d721ad079a97b09e57f Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/northbridge/amd/amdht/h3ncmn.c | 10 +++++----- src/northbridge/amd/gx2/northbridgeinit.c | 2 +- src/northbridge/amd/lx/northbridgeinit.c | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index cba21b3..da41369 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -350,7 +350,7 @@ static BOOL verifyLinkIsCoherent(u8 node, u8 link, cNorthBridge *nb) * * Description: * Return the LinkFailed status AFTER an attempt is made to clear the bit. - * Also, call event notify if a Hardware Fault caused a synch flood on a previous boot. + * Also, call event notify if a Hardware Fault caused a sync flood on a previous boot. * * The table below summarizes correct responses of this routine. * Family before after unconnected Notify? return @@ -397,10 +397,10 @@ static BOOL readTrueLinkFailStatus(u8 node, u8 link, sMainData *pDat, cNorthBrid { if (crc != 0) { - /* A synch flood occurred due to HT CRC */ + /* A sync flood occurred due to HT CRC */ if (pDat->HtBlock->AMD_CB_EventNotify) { - /* Pass the node and link on which the generic synch flood event occurred. */ + /* Pass the node and link on which the generic sync flood event occurred. */ sHtEventHWHtCrc evt; evt.eSize = sizeof(sHtEventHWHtCrc); evt.node = node; @@ -414,10 +414,10 @@ static BOOL readTrueLinkFailStatus(u8 node, u8 link, sMainData *pDat, cNorthBrid } else { - /* Some synch flood occurred */ + /* Some sync flood occurred */ if (pDat->HtBlock->AMD_CB_EventNotify) { - /* Pass the node and link on which the generic synch flood event occurred. */ + /* Pass the node and link on which the generic sync flood event occurred. */ sHtEventHWSynchFlood evt; evt.eSize = sizeof(sHtEventHWSynchFlood); evt.node = node; diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index 47611bf..7b49737 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -659,7 +659,7 @@ void northbridge_init_early(void) GLIUInit(gliutables[i]); /* Now that the descriptor to memory is set up. */ - /* The memory controller needs one read to synch its lines before it can be used. */ + /* The memory controller needs one read to sync its lines before it can be used. */ i = *(int *) 0; GeodeLinkPriority(); diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index 42b91d6..7bd3285 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -741,7 +741,7 @@ void northbridge_init_early(void) GLIUInit(gliutables[i]); /* Now that the descriptor to memory is set up. */ - /* The memory controller needs one read to synch its lines before it can be used. */ + /* The memory controller needs one read to sync its lines before it can be used. */ i = *(int *)0; GeodeLinkPriority();

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New patch to review for coreboot: 6b17c89 southbridge/dmp/vortex86ex: Incorrect usage of logical vs. bitwise 'or'
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6150 -gerrit commit 6b17c89c98a39a852c325b30e329e0fc78bafdf7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 18:00:27 2014 +1000 southbridge/dmp/vortex86ex: Incorrect usage of logical vs. bitwise 'or' Spotted by Clang. Change-Id: If91f26affb7782348f8ede1d3f0b3badc6cde309 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/dmp/vortex86ex/southbridge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index b9432f0..c9b10b6 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -572,7 +572,7 @@ static void southbridge_init_func1(struct device *dev) pci_write_config32(dev, SB1_REG_EXT_PIRQ_ROUTE2, ext_int_routing2); /* Assign in-chip PCI device IRQs. */ - if (SPI1_IRQ || MOTOR_IRQ) { + if (SPI1_IRQ | MOTOR_IRQ) { unsigned char irqs[4] = { MOTOR_IRQ, SPI1_IRQ, 0, 0 }; pci_assign_irqs(0, 0x10, irqs); }

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New patch to review for coreboot: 66abdd2 northbridge/amd: Remove some extraneous parentheses from if-statements
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6149 -gerrit commit 66abdd233235e012361f969f8aafd0678521643e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 17:52:34 2014 +1000 northbridge/amd: Remove some extraneous parentheses from if-statements Spotted by Clang. Change-Id: I38832da7b93d4ee18b8de3e80dc39513a8910221 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/agesa/family10/northbridge.c | 2 +- src/northbridge/amd/agesa/family12/amdfam12_conf.c | 4 ++-- src/northbridge/amd/agesa/family14/amdfam14_conf.c | 4 ++-- src/northbridge/amd/amdfam10/conf.c | 7 ++----- 4 files changed, 7 insertions(+), 10 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 886d112..78404ee 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -191,7 +191,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) u32 index; for (index=0; index<64; index++) { - if ((sysconf.conf_mmio_addrx[index+8] == 0)) { + if (sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); return index; diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index eb539d6..00ff641 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -195,7 +195,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) u32 index; for(index=0; index<256; index++) { - if((sysconf.conf_io_addrx[index+4] == 0)){ + if(sysconf.conf_io_addrx[index+4] == 0) { sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); return index; @@ -211,7 +211,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) u32 index; for(index=0; index<64; index++) { - if((sysconf.conf_mmio_addrx[index+8] == 0)){ + if(sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); return index; diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index d302db3..c255213 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -195,7 +195,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) u32 index; for(index=0; index<256; index++) { - if((sysconf.conf_io_addrx[index+4] == 0)){ + if(sysconf.conf_io_addrx[index+4] == 0) { sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); return index; @@ -211,7 +211,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) u32 index; for(index=0; index<64; index++) { - if((sysconf.conf_mmio_addrx[index+8] == 0)){ + if(sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); return index; diff --git a/src/northbridge/amd/amdfam10/conf.c b/src/northbridge/amd/amdfam10/conf.c index cfb914a..971e319 100644 --- a/src/northbridge/amd/amdfam10/conf.c +++ b/src/northbridge/amd/amdfam10/conf.c @@ -689,7 +689,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) u32 index; for(index=0; index<256; index++) { - if((sysconf.conf_io_addrx[index+4] == 0)){ + if(sysconf.conf_io_addrx[index+4] == 0) { sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); return index; @@ -697,16 +697,14 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) } return 0; - } static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) { u32 index; - for(index=0; index<64; index++) { - if((sysconf.conf_mmio_addrx[index+8] == 0)){ + if(sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); return index; @@ -714,7 +712,6 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) } return 0; - } static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,

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New patch to review for coreboot: 96f13d6 northbridge/amd/{gx2, lx}: qualifying pointer with 'volatile'
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6148 -gerrit commit 96f13d6839377b63684143150cdbb53aec969088 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 17:31:58 2014 +1000 northbridge/amd/{gx2,lx}: qualifying pointer with 'volatile' There is no guarante reading a dereferenced null pointer will not be optimised away. Qualify the integer storage type with volatile. Clang enfoces this. Change-Id: I31524141d70632cade0490c820936a3a8b570346 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/gx2/northbridgeinit.c | 2 +- src/northbridge/amd/lx/northbridgeinit.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index 47611bf..ef5277c 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -660,7 +660,7 @@ void northbridge_init_early(void) /* Now that the descriptor to memory is set up. */ /* The memory controller needs one read to synch its lines before it can be used. */ - i = *(int *) 0; + i = *(volatile int *) 0; GeodeLinkPriority(); diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index 42b91d6..82b3f48 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -742,7 +742,7 @@ void northbridge_init_early(void) /* Now that the descriptor to memory is set up. */ /* The memory controller needs one read to synch its lines before it can be used. */ - i = *(int *)0; + i = *(volatile int *)0; GeodeLinkPriority();

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New patch to review for coreboot: b6e55f3 southbridge/amd/rsXY0/cmn.c: Incorrect usage of logical vs. bitwise and
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6147 -gerrit commit b6e55f35d144595e311a0d2690b0a85838796576 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 15:36:57 2014 +1000 southbridge/amd/rsXY0/cmn.c: Incorrect usage of logical vs. bitwise and Spotted by Clang. Change-Id: I26e7acddbff32e978c2bf984c21d9a63337067f8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/rs690/cmn.c | 2 +- src/southbridge/amd/rs780/cmn.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index 36870b3..b00c72b 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -289,7 +289,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); - tmp = (reg >> 4) && 0x3; /* get bit4-6 */ + tmp = (reg >> 4) & 0x3; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ reg += tmp; /* merge */ reg |= 1 << 8; diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index cf09b9a..a5b3c81 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -330,7 +330,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); - tmp = (reg >> 4) && 0x3; /* get bit4-6 */ + tmp = (reg >> 4) & 0x3; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ reg += tmp; /* merge */ reg |= 1 << 8;

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New patch to review for coreboot: 78b780e cpu/x86/pae/pgtbl.c: comparision always false
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6146 -gerrit commit 78b780ecf5e9f5bf4409bbd0e241fe6744aad741 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 15:33:30 2014 +1000 cpu/x86/pae/pgtbl.c: comparision always false Comparison of unsigned expression < 0 is always false. Change-Id: Idf4e7846b50f4376a5d33515681efbd773d1caca Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/x86/pae/pgtbl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 9354738..9be415d 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -61,7 +61,7 @@ void *map_2M_page(unsigned long page) void *result; int i; index = cpu_index(); - if ((index < 0) || (index >= CONFIG_MAX_CPUS)) { + if (index >= CONFIG_MAX_CPUS) { return MAPPING_ERROR; } window = page >> 10;

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New patch to review for coreboot: 6750f9e northbridge/amd/{gx2, lx}/raminit.c: spd_byte can end up uninitialised
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6145 -gerrit commit 6750f9e0e0836f3e9010fd615651180cc73de00d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 15:29:26 2014 +1000 northbridge/amd/{gx2,lx}/raminit.c: spd_byte can end up uninitialised If the if-else construct falls though to 'else' then spd_byte is used before initialised. Set it to zero to be safe. Change-Id: I514dc3d673758f8f546d43a7a0868485d1d8d5ab Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/gx2/raminit.c | 2 +- src/northbridge/amd/lx/raminit.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index 71d0a16..a73b389 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -290,7 +290,7 @@ static void setCAS(void) * Destroys: We really use everything ! */ uint16_t glspeed; - uint8_t spd_byte, casmap0, casmap1; + uint8_t spd_byte, casmap0, casmap1 = 0; msr_t msr; glspeed = GeodeLinkSpeed(); diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index 6dfb073..389af11 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -303,7 +303,7 @@ static void setCAS(void) ;* Destroys: We really use everything ! ;*****************************************************************************/ uint16_t glspeed; - uint8_t spd_byte, casmap0, casmap1; + uint8_t spd_byte, casmap0, casmap1 = 0; msr_t msr; glspeed = GeodeLinkSpeed();

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New patch to review for coreboot: 4195b3a build: Allow clang build linkage to use libcompiler-rt
by Edward O'Callaghan 27 Jun '14

27 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6144 -gerrit commit 4195b3a89764e06a3fc4e8f7b63db1d3a9f0e667 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 03:02:52 2014 +1000 build: Allow clang build linkage to use libcompiler-rt NOTFORMERGE: (pending one more patch upstream) NOTE: *** Requires at least clang 3.5.0 r211866. Change-Id: I7f63284473d6067bf775409970c8dd98f5d5a8d5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile | 4 +++- src/arch/x86/Makefile.inc | 6 +++--- toolchain.inc | 1 + 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 195bfe6..44913dc 100644 --- a/Makefile +++ b/Makefile @@ -109,7 +109,9 @@ include $(HAVE_DOTCONFIG) ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) # FIXME: armv7/aarch64 won't build right now -CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-elf -m32 +# NOTE: clang puts compiler-rt under lib/linux/libclang_rt.builtins-i386.a +# this means the triple is i386-linux-elf instead of i386-none-elf +CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 CC_x86_32:=clang ifneq ($(CONFIG_MMX),y) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index c0e908d..251471b 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -209,7 +209,7 @@ romstage-libs ?= $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) --end-group -T $(objgenerated)/romstage_null.ld + $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) --start-group $(romstage-objs) $(romstage-libs) $(LIBCLANG_RT_FILE_NAME_romstage) --end-group -T $(objgenerated)/romstage_null.ld else $(CC_romstage) $(CFLAGS_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group endif @@ -221,7 +221,7 @@ endif $(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) --end-group -T $(objgenerated)/romstage_xip.ld + $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) --start-group $(romstage-objs) $(romstage-libs) $(LIBCLANG_RT_FILE_NAME_romstage) --end-group -T $(objgenerated)/romstage_xip.ld else $(CC_romstage) $(CFLAGS_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group endif @@ -332,7 +332,7 @@ endif $(objgenerated)/ramstage.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_ramstage) -m elf_i386 -r -o $@ --start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME_ramstage) --end-group + $(LD_ramstage) -m elf_i386 -r -o $@ --start-group $(ramstage-objs) $(ramstage-libs) $(LIBCLANG_RT_FILE_NAME_ramstage) --end-group else $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group endif diff --git a/toolchain.inc b/toolchain.inc index 2375f17..de40978 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -98,6 +98,7 @@ READELF_$(1) := $(READELF_$(2)) CFLAGS_$(1) = $$(CFLAGS_common) $$(CFLAGS_$(2)) CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2)) LIBGCC_FILE_NAME_$(1) = $(wildcard $(shell $(CC_$(2)) $(CFLAGS_$(2)) -print-libgcc-file-name)) +LIBCLANG_RT_FILE_NAME_$(1) = $(shell $(CC_$(2)) $(CFLAGS_$(2)) -print-librt-file-name) endef # initialize standard toolchain (CC,AS and others) for give stage

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coreboot-gerrit June 2014