coreboot-gerrit June 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 14dd5a1 southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loop
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6147 -gerrit commit 14dd5a174f175ec5384b982e90bcac4eacba9317 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 15:36:57 2014 +1000 southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loop First brought to attention by Clang: Correct mask to select bits 4-6 inclusively as per comment and use bitwise operations while working with bits. Be sure to write back out the data on the retrain. Change-Id: I26e7acddbff32e978c2bf984c21d9a63337067f8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/rs690/cmn.c | 9 ++++----- src/southbridge/amd/rs780/cmn.c | 9 ++++----- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index 36870b3..bd3ee63 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -286,13 +286,12 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; - reg = - nbpcie_p_read_index(dev, - PCIE_LC_LINK_WIDTH); - tmp = (reg >> 4) && 0x3; /* get bit4-6 */ + reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); + tmp = (reg >> 4) & 0x07; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ - reg += tmp; /* merge */ + reg |= tmp; /* merge */ reg |= 1 << 8; + nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg); count++; /* CIM said "keep in loop"? */ } else { res = 1; diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index cf09b9a..eb3b025 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -327,13 +327,12 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; - reg = - nbpcie_p_read_index(dev, - PCIE_LC_LINK_WIDTH); - tmp = (reg >> 4) && 0x3; /* get bit4-6 */ + reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); + tmp = (reg >> 4) & 0x07; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ - reg += tmp; /* merge */ + reg |= tmp; /* merge */ reg |= 1 << 8; + nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg); count++; /* CIM said "keep in loop"? */ } else { res = 1;

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Patch set updated for coreboot: 47fd4ff southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loop
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6147 -gerrit commit 47fd4ffc849c71a4f31ddbcaf9795f60d901bb0f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 15:36:57 2014 +1000 southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loop Correct mask to select bits 4-6 inclusively as per comment and use bitwise operations while working with bits. First brought to attention by Clang. Change-Id: I26e7acddbff32e978c2bf984c21d9a63337067f8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/rs690/cmn.c | 4 ++-- src/southbridge/amd/rs780/cmn.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index 36870b3..1716188 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -289,9 +289,9 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); - tmp = (reg >> 4) && 0x3; /* get bit4-6 */ + tmp = (reg >> 4) & 0x07; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ - reg += tmp; /* merge */ + reg |= tmp; /* merge */ reg |= 1 << 8; count++; /* CIM said "keep in loop"? */ } else { diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index cf09b9a..4aa935f 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -330,9 +330,9 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); - tmp = (reg >> 4) && 0x3; /* get bit4-6 */ + tmp = (reg >> 4) & 0x07; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ - reg += tmp; /* merge */ + reg |= tmp; /* merge */ reg |= 1 << 8; count++; /* CIM said "keep in loop"? */ } else {

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New patch to review for coreboot: 5c76dae northbridge/amd/gx2/raminit.c Halt func needs noreturn attrib
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6157 -gerrit commit 5c76daed53f13a09741b26f6b409ba04c77a4951 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jun 29 02:27:19 2014 +1000 northbridge/amd/gx2/raminit.c Halt func needs noreturn attrib Missing "__attribute__((noreturn))" on halt function. This sync's the implementation to be the same as that of amd/lx thereby avoiding compiler warnings. Change-Id: Iead16125805eb36ff875fba767cf8d4e5aa86715 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/gx2/raminit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index 71d0a16..d9af161 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -26,7 +26,7 @@ static const unsigned char NumColAddr[] = { 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, }; -static void hcf(void) +static void __attribute__((noreturn)) hcf(void) { printk(BIOS_EMERG, "DIE\n"); /* this guarantees we flush the UART fifos (if any) and also

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New patch to review for coreboot: 8d4a56a include/cpu/amd/mtrr.h: Missing header for 'msr_t' type
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6156 -gerrit commit 8d4a56ae2452ae971d0f5ac22c56e570e2b09684 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jun 29 02:04:21 2014 +1000 include/cpu/amd/mtrr.h: Missing header for 'msr_t' type Permuting inclusion of this header with others can result in build failures. Change-Id: Ied453a432b64801646e2a40df014a522db643aae Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/include/cpu/amd/mtrr.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index a9e672b..d8d1513 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -1,6 +1,8 @@ #ifndef CPU_AMD_MTRR_H #define CPU_AMD_MTRR_H +#include <cpu/x86/msr.h> + #define IORR_FIRST 0xC0010016 #define IORR_LAST 0xC0010019

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Patch set updated for coreboot: e609499 southbridge/amd/rsXY0/cmn.c: Trivial - Style fixes
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6155 -gerrit commit e60949941cef7d084225a049b031121f578d102c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 22:47:22 2014 +1000 southbridge/amd/rsXY0/cmn.c: Trivial - Style fixes Alphabetize headers, remove some ASCII art past 80 columns. Change-Id: I00ad79f2e1ddd78935efcfab19d9e166f0349ae3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/rs690/cmn.c | 52 ++++++++++++++++++---------------------- src/southbridge/amd/rs780/cmn.c | 53 +++++++++++++++++++---------------------- 2 files changed, 47 insertions(+), 58 deletions(-) diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index 36870b3..6c8b3e6 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -17,17 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> - #include <arch/io.h> - +#include <cpu/amd/mtrr.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> -#include <delay.h> + #include "rs690.h" static u32 nb_read_index(device_t dev, u32 index_reg, u32 index) @@ -47,7 +46,7 @@ static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) /* extension registers */ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) { - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn); @@ -60,7 +59,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask { u32 reg_old, reg; - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn);*/ @@ -191,12 +190,12 @@ void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val) } } -/*********************************************************** -* To access bar3 we need to program PCI MMIO 7 in K8. -* in_out: -* 1: enable/enter k8 temp mmio base -* 0: disable/restore -***********************************************************/ +/* + * To access bar3 we need to program PCI MMIO 7 in K8. + * in_out: + * 1: enable/enter k8 temp mmio base + * 0: disable/restore + */ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) { /* K8 Function1 is address map */ @@ -245,11 +244,11 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) } } -/******************************************************************************************************** -* Output: -* 0: no device is present. -* 1: device is present and is trained. -********************************************************************************************************/ +/* + * Output: + * 0: no device is present. + * 1: device is present and is trained. + */ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) { u16 count = 5000; @@ -278,17 +277,13 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) count = 0; break; case 0x10: - reg = - pci_ext_read_config32(nb_dev, dev, - PCIE_VC0_RESOURCE_STATUS); + reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS); printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); /* check bit1 */ if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; - reg = - nbpcie_p_read_index(dev, - PCIE_LC_LINK_WIDTH); + reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); tmp = (reg >> 4) && 0x3; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ reg += tmp; /* merge */ @@ -309,9 +304,9 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) } /* -* Compliant with CIM_33's ATINB_SetToms. -* Set Top Of Memory below and above 4G. -*/ + * Compliant with CIM_33's ATINB_SetToms. + * Set Top Of Memory below and above 4G. + */ void rs690_set_tom(device_t nb_dev) { /* set TOM */ @@ -324,4 +319,3 @@ void rs690_set_tom(device_t nb_dev) nbmc_write_index(nb_dev, 0x1e, 0x38000000); #endif } - diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index cf09b9a..ce81374 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -17,18 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> - #include <arch/io.h> - +#include <console/console.h> +#include <cpu/amd/mtrr.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> -#include <delay.h> -#include <cpu/cpu.h> + #include "rs780.h" static u32 nb_read_index(device_t dev, u32 index_reg, u32 index) @@ -46,7 +45,7 @@ static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) /* extension registers */ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) { - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn); @@ -59,7 +58,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask { u32 reg_old, reg; - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn);*/ @@ -190,12 +189,12 @@ void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val) } } -/*********************************************************** -* To access bar3 we need to program PCI MMIO 7 in K8. -* in_out: -* 1: enable/enter k8 temp mmio base -* 0: disable/restore -***********************************************************/ +/* + * To access bar3 we need to program PCI MMIO 7 in K8. + * in_out: + * 1: enable/enter k8 temp mmio base + * 0: disable/restore + */ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) { /* K8 Function1 is address map */ @@ -249,11 +248,11 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) } } -/******************************************************************************************************** -* Output: -* 0: no device is present. -* 1: device is present and is trained. -********************************************************************************************************/ +/* + * Output: + * 0: no device is present. + * 1: device is present and is trained. + */ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) { u16 count = 5000; @@ -319,17 +318,13 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) count = 0; break; case 0x10: - reg = - pci_ext_read_config32(nb_dev, dev, - PCIE_VC0_RESOURCE_STATUS); + reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS); printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); /* check bit1 */ if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; - reg = - nbpcie_p_read_index(dev, - PCIE_LC_LINK_WIDTH); + reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); tmp = (reg >> 4) && 0x3; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ reg += tmp; /* merge */ @@ -350,9 +345,9 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) } /* -* Compliant with CIM_33's ATINB_SetToms. -* Set Top Of Memory below and above 4G. -*/ + * Compliant with CIM_33's ATINB_SetToms. + * Set Top Of Memory below and above 4G. + */ void rs780_set_tom(device_t nb_dev) { /* set TOM */

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Patch set updated for coreboot: c009c80 build: remove -ccopts mechanism
by Patrick Georgi 28 Jun '14

28 Jun '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5875 -gerrit commit c009c807c720915c1ccd6353e6a84fae04819e52 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun May 25 00:11:35 2014 +0200 build: remove -ccopts mechanism We now use the slightly more familiar CFLAGS_* and CPPFLAGS_* for the same purpose. Change-Id: Ifd2bd13f67f71fa0a15611a6d11a6a4c7994271b Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile | 9 ++++----- Makefile.inc | 20 ++++++++------------ src/arch/armv7/Makefile.inc | 8 ++++---- toolchain.inc | 4 ++-- 4 files changed, 18 insertions(+), 23 deletions(-) diff --git a/Makefile b/Makefile index 195bfe6..67c43e9 100644 --- a/Makefile +++ b/Makefile @@ -212,13 +212,12 @@ alldirs:=$(sort $(abspath $(dir $(allobjs)))) define create_cc_template # $1 obj class # $2 source suffix (c, S) -# $3 additional compiler flags -# $4 additional dependencies +# $3 additional dependencies ifn$(EMPTY)def $(1)-objs_$(2)_template de$(EMPTY)fine $(1)-objs_$(2)_template -$(obj)/$$(1).$(1).o: src/$$(1).$(2) $(obj)/config.h $(4) +$(obj)/$$(1).$(1).o: src/$$(1).$(2) $(obj)/config.h $(3) @printf " CC $$$$(subst $$$$(obj)/,,$$$$(@))\n" - $(CC_$(1)) $(3) -MMD $$$$(CPPFLAGS_$(1)) $$$$(CFLAGS_$(1)) -c -o $$$$@ $$$$< + $(CC_$(1)) -MMD $$$$(CPPFLAGS_$(1)) $$$$(CFLAGS_$(1)) -c -o $$$$@ $$$$< en$(EMPTY)def end$(EMPTY)if endef @@ -226,7 +225,7 @@ endef filetypes-of-class=$(subst .,,$(sort $(suffix $($(1)-srcs)))) $(foreach class,$(classes), \ $(foreach type,$(call filetypes-of-class,$(class)), \ - $(eval $(call create_cc_template,$(class),$(type),$($(class)-$(type)-ccopts),$($(class)-$(type)-deps))))) + $(eval $(call create_cc_template,$(class),$(type),$($(class)-$(type)-deps))))) foreach-src=$(foreach file,$($(1)-srcs),$(eval $(call $(1)-objs_$(subst .,,$(suffix $(file)))_template,$(subst src/,,$(basename $(file)))))) $(eval $(foreach class,$(classes),$(call foreach-src,$(class)))) diff --git a/Makefile.inc b/Makefile.inc index b9a3fe9..7d1c4ae 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -111,31 +111,27 @@ ramstage-postprocess=$(foreach d,$(sort $(dir $(1))), \ $(eval $(d)ramstage.o: $(call files-in-dir,$(d),$(1)); $$(LD_ramstage) -o $$@ -r $$^ ) \ $(eval ramstage-objs:=$(d)ramstage.o $(filter-out $(call files-in-dir,$(d),$(1)),$(ramstage-objs)))) -romstage-c-ccopts:=-D__PRE_RAM__ -romstage-S-ccopts:=-D__PRE_RAM__ +CPPFLAGS_romstage += -D__PRE_RAM__ ifeq ($(CONFIG_TRACE),y) -ramstage-c-ccopts:= -finstrument-functions +CFLAGS_ramstage += -finstrument-functions endif ifeq ($(CONFIG_COVERAGE),y) -ramstage-c-ccopts+=-fprofile-arcs -ftest-coverage +CFLAGS_ramstage += -fprofile-arcs -ftest-coverage endif ifeq ($(CONFIG_USE_BLOBS),y) forgetthis:=$(shell git submodule update --init --checkout 3rdparty) endif -bootblock-c-ccopts:=-D__BOOT_BLOCK__ -D__PRE_RAM__ -bootblock-S-ccopts:=-D__BOOT_BLOCK__ -D__PRE_RAM__ +CPPFLAGS_bootblock += -D__BOOT_BLOCK__ -D__PRE_RAM__ -smmstub-c-ccopts:=-D__SMM__ -smmstub-S-ccopts:=-D__SMM__ -smm-c-ccopts:=-D__SMM__ -smm-S-ccopts:=-D__SMM__ +CPPFLAGS_smmstub += -D__SMM__ +CPPFLAGS_smm += -D__SMM__ # SMM TSEG base is dynamic ifneq ($(CONFIG_SMM_MODULES),y) ifeq ($(CONFIG_SMM_TSEG),y) -smm-c-ccopts += -fpic +CFLAGS_smm += -fpic endif endif @@ -325,7 +321,7 @@ $(obj)/%.romstage.o $(abspath $(obj))/%.romstage.o: $(obj)/%.c $(obj)/config.h $ $(obj)/%.bootblock.o $(abspath $(obj))/%.bootblock.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) -MMD $(bootblock-c-ccopts) $(CFLAGS_bootblock) $(CPPFLAGS_bootblock) -c -o $@ $< + $(CC_bootblock) -MMD $(CFLAGS_bootblock) $(CPPFLAGS_bootblock) -c -o $@ $< ####################################################################### # Clean up rules diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 590be07..a611b09 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -78,18 +78,18 @@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc) $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) $(bootblock-S-ccopts) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm + $(CC_bootblock) $(CPPFLAGS_bootblock) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) $(bootblock-S-ccopts) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC_bootblock) $(CPPFLAGS_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ $(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(bootblock_custom) $(OPTION_TABLE_H) $(obj)/config.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) $(bootblock-c-ccopts) $(CPPFLAGS_bootblock) -MM \ + $(CC_bootblock) $(CFLAGS_bootblock) $(CPPFLAGS_bootblock) -MM \ -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d - $(CC_bootblock) $(bootblock-c-ccopts) -c -S $(CFLAGS_bootblock) -I. $(CPPFLAGS_bootblock) $< -o $@ + $(CC_bootblock) -c -S $(CFLAGS_bootblock) -I. $(CPPFLAGS_bootblock) $< -o $@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld $$(bootblock-objs) $(stages) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" diff --git a/toolchain.inc b/toolchain.inc index 2375f17..b5b4fe0 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -95,8 +95,8 @@ OBJCOPY_$(1) := $(OBJCOPY_$(2)) OBJDUMP_$(1) := $(OBJDUMP_$(2)) STRIP_$(1) := $(STRIP_$(2)) READELF_$(1) := $(READELF_$(2)) -CFLAGS_$(1) = $$(CFLAGS_common) $$(CFLAGS_$(2)) -CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2)) +CFLAGS_$(1) += $$(CFLAGS_common) $$(CFLAGS_$(2)) +CPPFLAGS_$(1) += $$(CPPFLAGS_common) $$(CPPFLAGS_$(2)) LIBGCC_FILE_NAME_$(1) = $(wildcard $(shell $(CC_$(2)) $(CFLAGS_$(2)) -print-libgcc-file-name)) endef

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Patch merged into coreboot/master: 9c41063 Don't add .eh_frame sections to SMM image
by gerrit＠coreboot.org 28 Jun '14

28 Jun '14

the following patch was just integrated into master: commit 9c41063713c64994083a4baddb22d41a685a95b8 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed Jun 25 17:54:54 2014 +0200 Don't add .eh_frame sections to SMM image We don't need exception handlers and they waste space. Change-Id: I98a34d1c9638e8c4168edbfb4b1cddde8a64623f Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/6105 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6105 for details. -gerrit

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Patch merged into coreboot/master: 91d6fc8 armv7: We don't use CPPFLAGS anymore
by gerrit＠coreboot.org 28 Jun '14

28 Jun '14

the following patch was just integrated into master: commit 91d6fc8118d1b469ca8a9fa2da66e4819edf41c4 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun May 25 00:05:20 2014 +0200 armv7: We don't use CPPFLAGS anymore CPPFLAGS is only used as qualified variant (like CPPFLAGS_armv7) now. Change-Id: If8b570ace4ac92d1fdb38ca3f7fef6c79d513a95 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/5874 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> See http://review.coreboot.org/5874 for details. -gerrit

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New patch to review for coreboot: 6b56c4c southbridge/amd/rsXY0/cmn.c: Trivial - Style fixes
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6155 -gerrit commit 6b56c4c4c3296eb65e2cf69699775eae89e37c67 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 22:47:22 2014 +1000 southbridge/amd/rsXY0/cmn.c: Trivial - Style fixes Alphabetize headers, remove some ASCII art past 80 columns. Change-Id: I00ad79f2e1ddd78935efcfab19d9e166f0349ae3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/rs690/cmn.c | 52 ++++++++++++++++++---------------------- src/southbridge/amd/rs780/cmn.c | 53 +++++++++++++++++++---------------------- 2 files changed, 47 insertions(+), 58 deletions(-) diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index 36870b3..6c8b3e6 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -17,17 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> - #include <arch/io.h> - +#include <cpu/amd/mtrr.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> -#include <delay.h> + #include "rs690.h" static u32 nb_read_index(device_t dev, u32 index_reg, u32 index) @@ -47,7 +46,7 @@ static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) /* extension registers */ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) { - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn); @@ -60,7 +59,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask { u32 reg_old, reg; - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn);*/ @@ -191,12 +190,12 @@ void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val) } } -/*********************************************************** -* To access bar3 we need to program PCI MMIO 7 in K8. -* in_out: -* 1: enable/enter k8 temp mmio base -* 0: disable/restore -***********************************************************/ +/* + * To access bar3 we need to program PCI MMIO 7 in K8. + * in_out: + * 1: enable/enter k8 temp mmio base + * 0: disable/restore + */ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) { /* K8 Function1 is address map */ @@ -245,11 +244,11 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) } } -/******************************************************************************************************** -* Output: -* 0: no device is present. -* 1: device is present and is trained. -********************************************************************************************************/ +/* + * Output: + * 0: no device is present. + * 1: device is present and is trained. + */ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) { u16 count = 5000; @@ -278,17 +277,13 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) count = 0; break; case 0x10: - reg = - pci_ext_read_config32(nb_dev, dev, - PCIE_VC0_RESOURCE_STATUS); + reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS); printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); /* check bit1 */ if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; - reg = - nbpcie_p_read_index(dev, - PCIE_LC_LINK_WIDTH); + reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); tmp = (reg >> 4) && 0x3; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ reg += tmp; /* merge */ @@ -309,9 +304,9 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) } /* -* Compliant with CIM_33's ATINB_SetToms. -* Set Top Of Memory below and above 4G. -*/ + * Compliant with CIM_33's ATINB_SetToms. + * Set Top Of Memory below and above 4G. + */ void rs690_set_tom(device_t nb_dev) { /* set TOM */ @@ -324,4 +319,3 @@ void rs690_set_tom(device_t nb_dev) nbmc_write_index(nb_dev, 0x1e, 0x38000000); #endif } - diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index cf09b9a..ce81374 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -17,18 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> - #include <arch/io.h> - +#include <console/console.h> +#include <cpu/amd/mtrr.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> -#include <delay.h> -#include <cpu/cpu.h> + #include "rs780.h" static u32 nb_read_index(device_t dev, u32 index_reg, u32 index) @@ -46,7 +45,7 @@ static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) /* extension registers */ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) { - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn); @@ -59,7 +58,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask { u32 reg_old, reg; - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn);*/ @@ -190,12 +189,12 @@ void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val) } } -/*********************************************************** -* To access bar3 we need to program PCI MMIO 7 in K8. -* in_out: -* 1: enable/enter k8 temp mmio base -* 0: disable/restore -***********************************************************/ +/* + * To access bar3 we need to program PCI MMIO 7 in K8. + * in_out: + * 1: enable/enter k8 temp mmio base + * 0: disable/restore + */ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) { /* K8 Function1 is address map */ @@ -249,11 +248,11 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) } } -/******************************************************************************************************** -* Output: -* 0: no device is present. -* 1: device is present and is trained. -********************************************************************************************************/ +/* + * Output: + * 0: no device is present. + * 1: device is present and is trained. + */ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) { u16 count = 5000; @@ -319,17 +318,13 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) count = 0; break; case 0x10: - reg = - pci_ext_read_config32(nb_dev, dev, - PCIE_VC0_RESOURCE_STATUS); + reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS); printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); /* check bit1 */ if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; - reg = - nbpcie_p_read_index(dev, - PCIE_LC_LINK_WIDTH); + reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); tmp = (reg >> 4) && 0x3; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ reg += tmp; /* merge */ @@ -350,9 +345,9 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) } /* -* Compliant with CIM_33's ATINB_SetToms. -* Set Top Of Memory below and above 4G. -*/ + * Compliant with CIM_33's ATINB_SetToms. + * Set Top Of Memory below and above 4G. + */ void rs780_set_tom(device_t nb_dev) { /* set TOM */

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Patch set updated for coreboot: 709eb48 northbridge/amd: Fix `synch` to `sync` in comments
by Paul Menzel 28 Jun '14

28 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6151 -gerrit commit 709eb48ff804f8f84286893c8df5f29e9f3de0a8 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Jun 28 09:06:57 2014 +0200 northbridge/amd: Fix `synch` to `sync` in comments Run the following command to fix all occurrences in `src/northbridge`. $ git grep -l "synch " src/northbridge | xargs sed -i 's/synch /sync /g' Change-Id: I630aadae77524c3ab2171d721ad079a97b09e57f Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/northbridge/amd/amdht/h3ncmn.c | 10 +++++----- src/northbridge/amd/gx2/northbridgeinit.c | 2 +- src/northbridge/amd/lx/northbridgeinit.c | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index cba21b3..da41369 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -350,7 +350,7 @@ static BOOL verifyLinkIsCoherent(u8 node, u8 link, cNorthBridge *nb) * * Description: * Return the LinkFailed status AFTER an attempt is made to clear the bit. - * Also, call event notify if a Hardware Fault caused a synch flood on a previous boot. + * Also, call event notify if a Hardware Fault caused a sync flood on a previous boot. * * The table below summarizes correct responses of this routine. * Family before after unconnected Notify? return @@ -397,10 +397,10 @@ static BOOL readTrueLinkFailStatus(u8 node, u8 link, sMainData *pDat, cNorthBrid { if (crc != 0) { - /* A synch flood occurred due to HT CRC */ + /* A sync flood occurred due to HT CRC */ if (pDat->HtBlock->AMD_CB_EventNotify) { - /* Pass the node and link on which the generic synch flood event occurred. */ + /* Pass the node and link on which the generic sync flood event occurred. */ sHtEventHWHtCrc evt; evt.eSize = sizeof(sHtEventHWHtCrc); evt.node = node; @@ -414,10 +414,10 @@ static BOOL readTrueLinkFailStatus(u8 node, u8 link, sMainData *pDat, cNorthBrid } else { - /* Some synch flood occurred */ + /* Some sync flood occurred */ if (pDat->HtBlock->AMD_CB_EventNotify) { - /* Pass the node and link on which the generic synch flood event occurred. */ + /* Pass the node and link on which the generic sync flood event occurred. */ sHtEventHWSynchFlood evt; evt.eSize = sizeof(sHtEventHWSynchFlood); evt.node = node; diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index 47611bf..7b49737 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -659,7 +659,7 @@ void northbridge_init_early(void) GLIUInit(gliutables[i]); /* Now that the descriptor to memory is set up. */ - /* The memory controller needs one read to synch its lines before it can be used. */ + /* The memory controller needs one read to sync its lines before it can be used. */ i = *(int *) 0; GeodeLinkPriority(); diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index 42b91d6..7bd3285 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -741,7 +741,7 @@ void northbridge_init_early(void) GLIUInit(gliutables[i]); /* Now that the descriptor to memory is set up. */ - /* The memory controller needs one read to synch its lines before it can be used. */ + /* The memory controller needs one read to sync its lines before it can be used. */ i = *(int *)0; GeodeLinkPriority();

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coreboot-gerrit June 2014