June 2014 - coreboot-gerrit - mail.coreboot.org

Patch set updated for coreboot: e250634 Makefile: HOSTCC set too late in clang builds
by Edward O'Callaghan June 29, 2014

June 29, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6140 -gerrit commit e25063497e6347ee380e0fa2450f996ee4d9c5f8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Jun 27 18:14:47 2014 +1000 Makefile: HOSTCC set too late in clang builds Currently we set HOSTCC=clang a little late meaning some minor bits (utils/kconfig) are built with GCC. Move the assignment up the Makefile. Change-Id: Ic72ad808eba0c0bf508bde34fb9bf0390c0b1d4d Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 195bfe6..aacd425 100644 --- a/Makefile +++ b/Makefile @@ -69,6 +69,9 @@ endif endif HOSTCC = gcc +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) +HOSTCC := clang +endif HOSTCXX = g++ HOSTCFLAGS := -g HOSTCXXFLAGS := -g @@ -126,8 +129,6 @@ CC_armv7:=clang CFLAGS_aarch64 = -no-integrated-as -Qunused-arguments -target aarch64-eabi -ccc-gcc-name $(CC_aarch64) CC_aarch64:=clang - -HOSTCC:=clang endif include toolchain.inc

1 0

Patch merged into coreboot/master: 44fd0a0 utils/cbfstool: No need to pass -g flag twice
by gerrit＠coreboot.org June 29, 2014

June 29, 2014

the following patch was just integrated into master: commit 44fd0a00318a6408f77ace75ed09628eba50c0a4 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Jun 27 18:07:05 2014 +1000 utils/cbfstool: No need to pass -g flag twice Spotted by building with Clang. Change-Id: I7ab97278d8bd586a71e453c8cc9d26dd6938c8d2 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6139 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> See http://review.coreboot.org/6139 for details. -gerrit

1 0

Patch merged into coreboot/master: efe2435 cpu/amd/geode_gx2/cache_as_ram.inc: Remove illegal ASCII art
by gerrit＠coreboot.org June 29, 2014

June 29, 2014

the following patch was just integrated into master: commit efe2435fec15866d803579a2b84ec299e8b42fb5 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 19:07:33 2014 +1000 cpu/amd/geode_gx2/cache_as_ram.inc: Remove illegal ASCII art Embedding comments inside comments is illegal in the C specification, Clang enforces this. Change-Id: I0a468e4196034b00dfc5860fdbbab7788e4fef77 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6154 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/6154 for details. -gerrit

1 0

Patch set updated for coreboot: 704d4ab drivers/spi: Reduce the per loop delay of spi_flash_cmd_poll_bit()
by Edward O'Callaghan June 29, 2014

June 29, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5973 -gerrit commit 704d4abad3f6d71d2272381c2ecd00ca52739a9b Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Wed Jun 11 12:53:47 2014 -0600 drivers/spi: Reduce the per loop delay of spi_flash_cmd_poll_bit() At the end of some SPI operations the SPI device needs to be polled to determine if it is done with the operation. For SPI data writes the predicted time of that operation could be less than 10us. The current per loop delay of 500us is adding too much delay. This change replaces the delay(x) in the do-while loop with a timer so that the actual timeout value won't be lengthened by the delay of reading the SPI device. Change-Id: Ia8b00879135f926c402bbd9d08953c77a2dcc84e Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/drivers/spi/spi_flash.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 33588d5..6d92836 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -16,6 +16,7 @@ #include <cpu/x86/smm.h> #endif #include "spi_flash_internal.h" +#include <timer.h> static void spi_flash_addr(u32 addr, u8 *cmd) { @@ -106,27 +107,24 @@ int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout, u8 cmd, u8 poll_bit) { struct spi_slave *spi = flash->spi; - unsigned long timebase; int ret; u8 status; + struct mono_time current, end; + + timer_monotonic_get(&current); + end = current; + mono_time_add_msecs(&end, timeout); - timebase = timeout; do { ret = spi_flash_cmd_read(spi, &cmd, 1, &status, 1); if (ret) return -1; - if ((status & poll_bit) == 0) - break; - - udelay(500); - } while (timebase--); - - if ((status & poll_bit) == 0) - return 0; + return 0; + timer_monotonic_get(&current); + } while (!mono_time_after(&current, &end)); - /* Timed out */ - printk(BIOS_DEBUG, "SF: time out!\n"); + printk(BIOS_DEBUG, "SF: timeout at %ld msec\n",timeout); return -1; }

1 0

Patch set updated for coreboot: 277e322 intel: Make monotonic timer a first class citizen
by Edward O'Callaghan June 29, 2014

June 29, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6135 -gerrit commit 277e3229d92dea1fa4da75709652b3c529a3e502 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Jun 27 12:13:30 2014 +1000 intel: Make monotonic timer a first class citizen The monotonic time now needs to be a first class citizen in Coreboot as it is a hard dependency of the drivers/spi flash command polling function. Change-Id: I4e43d2680bf84bc525138f71c2b813b0f6be5265 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 2 ++ src/cpu/intel/haswell/Kconfig | 1 + src/cpu/intel/model_2065x/Kconfig | 2 ++ src/cpu/intel/model_206ax/Kconfig | 2 ++ src/mainboard/intel/baskingridge/Kconfig | 2 +- src/mainboard/intel/bayleybay_fsp/Kconfig | 2 ++ src/northbridge/intel/nehalem/Kconfig | 2 ++ 7 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 0fb4437..01eda1b 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -39,6 +39,8 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE + select HAVE_MONOTONIC_TIMER + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index fa02cba..9cda140 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -24,6 +24,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select PARALLEL_CPU_INIT select PARALLEL_MP + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 3ef314d..4030df5 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -18,6 +18,8 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select HAVE_MONOTONIC_TIMER + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index a679e00..1456f94 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -19,6 +19,8 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select HAVE_MONOTONIC_TIMER + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index b52df97..acf4a75 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select LAPIC_MONOTONIC_TIMER + select MONOTONIC_TIMER_MSR config MAINBOARD_DIR string diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index 772cc70..bbde40f 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -31,6 +31,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select DEFAULT_CONSOLE_LOGLEVEL_7 if FSP_PACKAGE_DEFAULT + select HAVE_MONOTONIC_TIMER + select TSC_MONOTONIC_TIMER config MAINBOARD_DIR string diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 1da2ef9..df749eb 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -25,6 +25,8 @@ config NORTHBRIDGE_INTEL_NEHALEM select DYNAMIC_CBMEM select VGA select INTEL_EDID + select HAVE_MONOTONIC_TIMER + select TSC_MONOTONIC_TIMER if NORTHBRIDGE_INTEL_NEHALEM

1 0

Patch set updated for coreboot: dff3c1c intel: Make monotonic timer a first class citizen
by David Hendricks June 29, 2014

June 29, 2014

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6136 -gerrit commit dff3c1cc487af40444fb6616a3f512e485b09c2f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Jun 27 12:13:30 2014 +1000 intel: Make monotonic timer a first class citizen NOTFORMERGE Change-Id: I9df6d209e512f187c061adb7ebceffd424c6a4f7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 2 ++ src/cpu/intel/haswell/Kconfig | 1 + src/cpu/intel/model_2065x/Kconfig | 2 ++ src/cpu/intel/model_206ax/Kconfig | 2 ++ src/mainboard/intel/baskingridge/Kconfig | 2 +- src/mainboard/intel/bayleybay_fsp/Kconfig | 2 ++ src/northbridge/intel/nehalem/Kconfig | 2 ++ 7 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 0fb4437..01eda1b 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -39,6 +39,8 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE + select HAVE_MONOTONIC_TIMER + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index fa02cba..9cda140 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -24,6 +24,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select PARALLEL_CPU_INIT select PARALLEL_MP + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 3ef314d..4030df5 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -18,6 +18,8 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select HAVE_MONOTONIC_TIMER + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index a679e00..1456f94 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -19,6 +19,8 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select HAVE_MONOTONIC_TIMER + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index b52df97..acf4a75 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select LAPIC_MONOTONIC_TIMER + select MONOTONIC_TIMER_MSR config MAINBOARD_DIR string diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index 772cc70..bbde40f 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -31,6 +31,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select DEFAULT_CONSOLE_LOGLEVEL_7 if FSP_PACKAGE_DEFAULT + select HAVE_MONOTONIC_TIMER + select TSC_MONOTONIC_TIMER config MAINBOARD_DIR string diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 1da2ef9..df749eb 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -25,6 +25,8 @@ config NORTHBRIDGE_INTEL_NEHALEM select DYNAMIC_CBMEM select VGA select INTEL_EDID + select HAVE_MONOTONIC_TIMER + select TSC_MONOTONIC_TIMER if NORTHBRIDGE_INTEL_NEHALEM

1 0

Patch set updated for coreboot: 84bdcf2 drivers/spi: Reduce the per loop delay of spi_flash_cmd_poll_bit()
by David Hendricks June 29, 2014

June 29, 2014

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6137 -gerrit commit 84bdcf2221429ecf24f6192e03351c13f3234037 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Wed Jun 11 12:53:47 2014 -0600 drivers/spi: Reduce the per loop delay of spi_flash_cmd_poll_bit() At the end of some SPI operations the SPI device needs to be polled to determine if it is done with the operation. For SPI data writes the predicted time of that operation could be less than 10us. The current per loop delay of 500us is adding too much delay. This change replaces the delay(x) in the do-while loop with a timer so that the actual timeout value won't be lengthened by the delay of reading the SPI device. Change-Id: Idf5a70182d66fc6a4b760ddae5f15a9fb654c9ff Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/drivers/spi/spi_flash.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 33588d5..6d92836 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -16,6 +16,7 @@ #include <cpu/x86/smm.h> #endif #include "spi_flash_internal.h" +#include <timer.h> static void spi_flash_addr(u32 addr, u8 *cmd) { @@ -106,27 +107,24 @@ int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout, u8 cmd, u8 poll_bit) { struct spi_slave *spi = flash->spi; - unsigned long timebase; int ret; u8 status; + struct mono_time current, end; + + timer_monotonic_get(&current); + end = current; + mono_time_add_msecs(&end, timeout); - timebase = timeout; do { ret = spi_flash_cmd_read(spi, &cmd, 1, &status, 1); if (ret) return -1; - if ((status & poll_bit) == 0) - break; - - udelay(500); - } while (timebase--); - - if ((status & poll_bit) == 0) - return 0; + return 0; + timer_monotonic_get(&current); + } while (!mono_time_after(&current, &end)); - /* Timed out */ - printk(BIOS_DEBUG, "SF: time out!\n"); + printk(BIOS_DEBUG, "SF: timeout at %ld msec\n",timeout); return -1; }

1 0

Patch set updated for coreboot: 6fafbc8 intel: Make monotonic timer a first class citizen
by David Hendricks June 29, 2014

June 29, 2014

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6136 -gerrit commit 6fafbc8769fb472693062e34bcd5f78b6b952d1e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Jun 27 12:13:30 2014 +1000 intel: Make monotonic timer a first class citizen NOTFORMERGE Change-Id: I9df6d209e512f187c061adb7ebceffd424c6a4f7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 2 ++ src/cpu/intel/haswell/Kconfig | 1 + src/cpu/intel/model_2065x/Kconfig | 2 ++ src/cpu/intel/model_206ax/Kconfig | 2 ++ src/mainboard/intel/baskingridge/Kconfig | 2 +- src/mainboard/intel/bayleybay_fsp/Kconfig | 2 ++ src/northbridge/intel/nehalem/Kconfig | 2 ++ 7 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 0fb4437..01eda1b 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -39,6 +39,8 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE + select HAVE_MONOTONIC_TIMER + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index fa02cba..9cda140 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -24,6 +24,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select PARALLEL_CPU_INIT select PARALLEL_MP + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 3ef314d..4030df5 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -18,6 +18,8 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select HAVE_MONOTONIC_TIMER + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index a679e00..1456f94 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -19,6 +19,8 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select HAVE_MONOTONIC_TIMER + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index b52df97..acf4a75 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select LAPIC_MONOTONIC_TIMER + select MONOTONIC_TIMER_MSR config MAINBOARD_DIR string diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index 772cc70..bbde40f 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -31,6 +31,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select DEFAULT_CONSOLE_LOGLEVEL_7 if FSP_PACKAGE_DEFAULT + select HAVE_MONOTONIC_TIMER + select TSC_MONOTONIC_TIMER config MAINBOARD_DIR string diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 1da2ef9..df749eb 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -25,6 +25,8 @@ config NORTHBRIDGE_INTEL_NEHALEM select DYNAMIC_CBMEM select VGA select INTEL_EDID + select HAVE_MONOTONIC_TIMER + select TSC_MONOTONIC_TIMER if NORTHBRIDGE_INTEL_NEHALEM

1 0

Patch set updated for coreboot: cbb2237 drivers/spi: Reduce the per loop delay of spi_flash_cmd_poll_bit()
by David Hendricks June 29, 2014

June 29, 2014

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6137 -gerrit commit cbb22370caeda28565f79605ffa68bb19b8f7d58 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Wed Jun 11 12:53:47 2014 -0600 drivers/spi: Reduce the per loop delay of spi_flash_cmd_poll_bit() At the end of some SPI operations the SPI device needs to be polled to determine if it is done with the operation. For SPI data writes the predicted time of that operation could be less than 10us. The current per loop delay of 500us is adding too much delay. This change replaces the delay(x) in the do-while loop with a timer so that the actual timeout value won't be lengthened by the delay of reading the SPI device. Change-Id: Idf5a70182d66fc6a4b760ddae5f15a9fb654c9ff Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/drivers/spi/spi_flash.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 33588d5..6d92836 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -16,6 +16,7 @@ #include <cpu/x86/smm.h> #endif #include "spi_flash_internal.h" +#include <timer.h> static void spi_flash_addr(u32 addr, u8 *cmd) { @@ -106,27 +107,24 @@ int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout, u8 cmd, u8 poll_bit) { struct spi_slave *spi = flash->spi; - unsigned long timebase; int ret; u8 status; + struct mono_time current, end; + + timer_monotonic_get(&current); + end = current; + mono_time_add_msecs(&end, timeout); - timebase = timeout; do { ret = spi_flash_cmd_read(spi, &cmd, 1, &status, 1); if (ret) return -1; - if ((status & poll_bit) == 0) - break; - - udelay(500); - } while (timebase--); - - if ((status & poll_bit) == 0) - return 0; + return 0; + timer_monotonic_get(&current); + } while (!mono_time_after(&current, &end)); - /* Timed out */ - printk(BIOS_DEBUG, "SF: time out!\n"); + printk(BIOS_DEBUG, "SF: timeout at %ld msec\n",timeout); return -1; }

1 0

Patch set updated for coreboot: 655250d intel: Make monotonic timer a first class citizen
by David Hendricks June 29, 2014

June 29, 2014

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6136 -gerrit commit 655250d9c0ff61bbd27ee466a070864ecf239a77 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Jun 27 12:13:30 2014 +1000 intel: Make monotonic timer a first class citizen NOTFORMERGE Change-Id: I9df6d209e512f187c061adb7ebceffd424c6a4f7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 2 ++ src/cpu/intel/haswell/Kconfig | 1 + src/cpu/intel/model_2065x/Kconfig | 2 ++ src/cpu/intel/model_206ax/Kconfig | 2 ++ src/mainboard/intel/baskingridge/Kconfig | 2 +- src/northbridge/intel/nehalem/Kconfig | 2 ++ 6 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 0fb4437..01eda1b 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -39,6 +39,8 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE + select HAVE_MONOTONIC_TIMER + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index fa02cba..9cda140 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -24,6 +24,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select PARALLEL_CPU_INIT select PARALLEL_MP + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 3ef314d..4030df5 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -18,6 +18,8 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select HAVE_MONOTONIC_TIMER + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index a679e00..1456f94 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -19,6 +19,8 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select HAVE_MONOTONIC_TIMER + select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index b52df97..acf4a75 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select LAPIC_MONOTONIC_TIMER + select MONOTONIC_TIMER_MSR config MAINBOARD_DIR string diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 1da2ef9..df749eb 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -25,6 +25,8 @@ config NORTHBRIDGE_INTEL_NEHALEM select DYNAMIC_CBMEM select VGA select INTEL_EDID + select HAVE_MONOTONIC_TIMER + select TSC_MONOTONIC_TIMER if NORTHBRIDGE_INTEL_NEHALEM

1 0