coreboot-gerrit June 2014

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Patch set updated for coreboot: 3ba45c5 vendorcode/amd/agesa: Fix `synch` to `sync` in comments
by Paul Menzel 28 Jun '14

28 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6152 -gerrit commit 3ba45c52e7e6c2b031046d7331c995922afe84b5 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Jun 28 09:06:57 2014 +0200 vendorcode/amd/agesa: Fix `synch` to `sync` in comments Run the following command to fix all occurrences in vendor code. $ git grep -l "synch " | xargs sed -i 's/synch /sync /g' Change-Id: I8395cd289c8d713cf89f186cc9bbc4c478dcb743 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h | 2 +- src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h | 2 +- src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h | 2 +- src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h | 2 +- src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h | 2 +- src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h | 2 +- src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h | 2 +- src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h | 2 +- src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h | 2 +- src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h | 2 +- src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h | 2 +- src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h index 475272d..bc4c5c3 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h @@ -182,7 +182,7 @@ typedef enum { } TABLE_CORE_SELECTOR; // Initializer bit pattern values for platform features. -// Keep in synch with the PLATFORM_FEATURES struct! +// Keep in sync with the PLATFORM_FEATURES struct! // The 5 control flow modes. #define AMD_PF_NFCM BIT0 diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h index 5059dce..79dd2b1 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h +++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h @@ -55,7 +55,7 @@ /// For event ::HT_EVENT_HW_SYNCFLOOD typedef struct { UINT32 Node; ///< The Node on which observed - UINT32 Link; ///< The Link on that Node which reported synch flood + UINT32 Link; ///< The Link on that Node which reported sync flood UINT32 Reserved1; ///< Reserved. UINT32 Reserved2; ///< Reserved. } HT_EVENT_DATA_HW_SYNCFLOOD; diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h index cb27aee..cde716f 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h @@ -186,7 +186,7 @@ typedef enum { } TABLE_CORE_SELECTOR; // Initializer bit pattern values for platform features. -// Keep in synch with the PLATFORM_FEATURES struct! +// Keep in sync with the PLATFORM_FEATURES struct! // The 5 control flow modes. #define AMD_PF_NFCM BIT0 diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h index b3b4a90..bc62f8a 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h +++ b/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h @@ -55,7 +55,7 @@ /// For event ::HT_EVENT_HW_SYNCFLOOD typedef struct { UINT32 Node; ///< The Node on which observed - UINT32 Link; ///< The Link on that Node which reported synch flood + UINT32 Link; ///< The Link on that Node which reported sync flood UINT32 Reserved1; ///< Reserved. UINT32 Reserved2; ///< Reserved. } HT_EVENT_DATA_HW_SYNCFLOOD; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h index 76ec4b0..24d2209 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h @@ -187,7 +187,7 @@ typedef enum { } TABLE_CORE_SELECTOR; // Initializer bit pattern values for platform features. -// Keep in synch with the PLATFORM_FEATURES struct! +// Keep in sync with the PLATFORM_FEATURES struct! // The 5 control flow modes. #define AMD_PF_NFCM BIT0 diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h index f7f846a..fd2267b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h +++ b/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h @@ -56,7 +56,7 @@ /// For event ::HT_EVENT_HW_SYNCFLOOD typedef struct { UINT32 Node; ///< The Node on which observed - UINT32 Link; ///< The Link on that Node which reported synch flood + UINT32 Link; ///< The Link on that Node which reported sync flood UINT32 Reserved1; ///< Reserved. UINT32 Reserved2; ///< Reserved. } HT_EVENT_DATA_HW_SYNCFLOOD; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h index 16c3baa..e3388ce 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h @@ -187,7 +187,7 @@ typedef enum { } TABLE_CORE_SELECTOR; // Initializer bit pattern values for platform features. -// Keep in synch with the PLATFORM_FEATURES struct! +// Keep in sync with the PLATFORM_FEATURES struct! // The 5 control flow modes. #define AMD_PF_NFCM BIT0 diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h index 9e28445..457cc02 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h +++ b/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h @@ -56,7 +56,7 @@ /// For event ::HT_EVENT_HW_SYNCFLOOD typedef struct { UINT32 Node; ///< The Node on which observed - UINT32 Link; ///< The Link on that Node which reported synch flood + UINT32 Link; ///< The Link on that Node which reported sync flood UINT32 Reserved1; ///< Reserved. UINT32 Reserved2; ///< Reserved. } HT_EVENT_DATA_HW_SYNCFLOOD; diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c index d154e2f..9448a7a 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c @@ -419,7 +419,7 @@ MemNAfterDQSTrainingOr ( MemNSwitchDCTNb (NBPtr, Dct); if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { if (!(NBPtr->DctCachePtr->Is__x4)) { - // Only synch when 1D training has been performed or training with x8 DIMMs + // Only sync when 1D training has been performed or training with x8 DIMMs for (Dimm = 0; Dimm < 4; Dimm++) { for (Byte = 0; Byte < 9; Byte++) { Dly = (UINT16) MemNGetTrainDlyNb (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, Byte)); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h index c21cb9c..48c5452 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h @@ -186,7 +186,7 @@ typedef enum { } TABLE_CORE_SELECTOR; // Initializer bit pattern values for platform features. -// Keep in synch with the PLATFORM_FEATURES struct! +// Keep in sync with the PLATFORM_FEATURES struct! // The 5 control flow modes. #define AMD_PF_NFCM BIT0 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h index 6507165..74ea10d 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h @@ -55,7 +55,7 @@ /// For event ::HT_EVENT_HW_SYNCFLOOD typedef struct { UINT32 Node; ///< The Node on which observed - UINT32 Link; ///< The Link on that Node which reported synch flood + UINT32 Link; ///< The Link on that Node which reported sync flood UINT32 Reserved1; ///< Reserved. UINT32 Reserved2; ///< Reserved. } HT_EVENT_DATA_HW_SYNCFLOOD; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h index 1f6341a..7696047 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h @@ -204,7 +204,7 @@ typedef enum { #define PERFORM_EARLY_ANY_CONDITION (PERFORM_EARLY_WARM_RESET | PERFORM_EARLY_COLD_BOOT) // Initializer bit pattern values for platform features. -// Keep in synch with the PLATFORM_FEATURES struct! +// Keep in sync with the PLATFORM_FEATURES struct! // The 5 control flow modes. #define AMD_PF_NFCM BIT0 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h index 58d0cbe..0c208cb 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h @@ -55,7 +55,7 @@ /// For event ::HT_EVENT_HW_SYNCFLOOD typedef struct { UINT32 Node; ///< The Node on which observed - UINT32 Link; ///< The Link on that Node which reported synch flood + UINT32 Link; ///< The Link on that Node which reported sync flood UINT32 Reserved1; ///< Reserved. UINT32 Reserved2; ///< Reserved. } HT_EVENT_DATA_HW_SYNCFLOOD; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c index be956bc..23969b3 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c @@ -403,7 +403,7 @@ MemNAfterDQSTrainingKB ( MemNSwitchDCTNb (NBPtr, Dct); if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { if (!(NBPtr->DctCachePtr->Is2Dx4)) { - // Only synch when 1D training has been performed or 2D training with x8 DIMMs + // Only sync when 1D training has been performed or 2D training with x8 DIMMs for (Dimm = 0; Dimm < 4; Dimm++) { for (Byte = 0; Byte < 9; Byte++) { Dly = (UINT16) MemNGetTrainDlyNb (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, Byte));

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Patch set updated for coreboot: b8db3c8 cpu/amd/geode_gx2/cache_as_ram.inc: Remove illegal ASCII art
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6154 -gerrit commit b8db3c831ef3c10ffc7fcdfc19c0d0330e4165f6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 19:07:33 2014 +1000 cpu/amd/geode_gx2/cache_as_ram.inc: Remove illegal ASCII art Embedding comments inside comments is illegal in the C specification, Clang enforces this. Change-Id: I0a468e4196034b00dfc5860fdbbab7788e4fef77 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/amd/geode_gx2/cache_as_ram.inc | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc index 6a107fe..45a04f8 100644 --- a/src/cpu/amd/geode_gx2/cache_as_ram.inc +++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc @@ -26,17 +26,17 @@ #define GX2_CACHEWAY_SIZE (GX2_NUM_CACHELINES * GX2_CACHELINE_SIZE) #define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ #define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ + #include <cpu/amd/gx2def.h> #include <cpu/x86/post_code.h> -/*************************************************************************** -/** -/** DCacheSetup -/** -/** Setup data cache for use as RAM for a stack. -/** -/** Max. size data cache =0x4000 (16KB) -/** -/***************************************************************************/ + +/* + * DCacheSetup + * + * Setup data cache for use as RAM for a stack. + * + * Max. size data cache =0x4000 (16KB) + */ DCacheSetup: /* Save the BIST result */ movl %eax, %ebx @@ -201,4 +201,3 @@ __main: post_code(POST_DEAD_CODE) hlt jmp .Lhlt -

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Patch set updated for coreboot: df65507 southbridge/dmp/vortex86ex: Incorrect usage of logical vs. bitwise 'and'
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6153 -gerrit commit df65507bc32344151d54bece14cc15336d140077 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 18:30:06 2014 +1000 southbridge/dmp/vortex86ex: Incorrect usage of logical vs. bitwise 'and' We should be using a logical bitwise 'and' here with the LSB and CONFIG_ boolean. Spotted by Clang. Change-Id: I8f822fd2647f1912906064363dc452b25a0eecf9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/dmp/vortex86ex/southbridge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index c9b10b6..e66d350 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -231,7 +231,7 @@ static void pci_routing_fixup(struct device *dev) unsigned char irqs[4] = { OHCII_IRQ, EHCII_IRQ, 0, 0 }; pci_assign_irqs(0, 0xa, irqs); } - if (CONFIG_IDE_NATIVE_MODE && PIDE_IRQ) { + if (CONFIG_IDE_NATIVE_MODE & PIDE_IRQ) { /* IDE in native mode, setup PCI IRQ. */ unsigned char irqs[4] = { PIDE_IRQ, 0, 0, 0 }; pci_assign_irqs(0, 0xc, irqs);

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Patch set updated for coreboot: 7606cdb southbridge/dmp/vortex86ex: Incorrect usage of logical vs. bitwise 'or'
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6150 -gerrit commit 7606cdbd54709e1697b0da1b39935b7e3bd1d791 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 18:00:27 2014 +1000 southbridge/dmp/vortex86ex: Incorrect usage of logical vs. bitwise 'or' Spotted by Clang. Change-Id: If91f26affb7782348f8ede1d3f0b3badc6cde309 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/dmp/vortex86ex/southbridge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index b9432f0..c9b10b6 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -572,7 +572,7 @@ static void southbridge_init_func1(struct device *dev) pci_write_config32(dev, SB1_REG_EXT_PIRQ_ROUTE2, ext_int_routing2); /* Assign in-chip PCI device IRQs. */ - if (SPI1_IRQ || MOTOR_IRQ) { + if (SPI1_IRQ | MOTOR_IRQ) { unsigned char irqs[4] = { MOTOR_IRQ, SPI1_IRQ, 0, 0 }; pci_assign_irqs(0, 0x10, irqs); }

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Patch set updated for coreboot: 4ff9953 northbridge/amd/{gx2, lx}: Qualify pointer with `volatile`
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6148 -gerrit commit 4ff9953d1f35e61d109ed5334fb4d42f0e2dc201 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 17:31:58 2014 +1000 northbridge/amd/{gx2,lx}: Qualify pointer with `volatile` There is no guarantee reading a dereferenced null pointer will not be optimised away. Qualify the integer storage type with volatile. Clang enforces this explicitness. Change-Id: I31524141d70632cade0490c820936a3a8b570346 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/gx2/northbridgeinit.c | 2 +- src/northbridge/amd/lx/northbridgeinit.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index 47611bf..ef5277c 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -660,7 +660,7 @@ void northbridge_init_early(void) /* Now that the descriptor to memory is set up. */ /* The memory controller needs one read to synch its lines before it can be used. */ - i = *(int *) 0; + i = *(volatile int *) 0; GeodeLinkPriority(); diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index 42b91d6..82b3f48 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -742,7 +742,7 @@ void northbridge_init_early(void) /* Now that the descriptor to memory is set up. */ /* The memory controller needs one read to synch its lines before it can be used. */ - i = *(int *)0; + i = *(volatile int *)0; GeodeLinkPriority();

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Patch set updated for coreboot: c7febc9 northbridge/amd: Remove some extraneous parentheses from if-statements
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6149 -gerrit commit c7febc94eb0f974802e50510aa1c34e7e89ccdd6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 17:52:34 2014 +1000 northbridge/amd: Remove some extraneous parentheses from if-statements Spotted by Clang. Change-Id: I38832da7b93d4ee18b8de3e80dc39513a8910221 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/agesa/family10/northbridge.c | 2 +- src/northbridge/amd/agesa/family12/amdfam12_conf.c | 4 ++-- src/northbridge/amd/agesa/family14/amdfam14_conf.c | 4 ++-- src/northbridge/amd/amdfam10/conf.c | 7 ++----- 4 files changed, 7 insertions(+), 10 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 886d112..78404ee 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -191,7 +191,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) u32 index; for (index=0; index<64; index++) { - if ((sysconf.conf_mmio_addrx[index+8] == 0)) { + if (sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); return index; diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index eb539d6..00ff641 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -195,7 +195,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) u32 index; for(index=0; index<256; index++) { - if((sysconf.conf_io_addrx[index+4] == 0)){ + if(sysconf.conf_io_addrx[index+4] == 0) { sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); return index; @@ -211,7 +211,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) u32 index; for(index=0; index<64; index++) { - if((sysconf.conf_mmio_addrx[index+8] == 0)){ + if(sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); return index; diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index d302db3..c255213 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -195,7 +195,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) u32 index; for(index=0; index<256; index++) { - if((sysconf.conf_io_addrx[index+4] == 0)){ + if(sysconf.conf_io_addrx[index+4] == 0) { sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); return index; @@ -211,7 +211,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) u32 index; for(index=0; index<64; index++) { - if((sysconf.conf_mmio_addrx[index+8] == 0)){ + if(sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); return index; diff --git a/src/northbridge/amd/amdfam10/conf.c b/src/northbridge/amd/amdfam10/conf.c index cfb914a..971e319 100644 --- a/src/northbridge/amd/amdfam10/conf.c +++ b/src/northbridge/amd/amdfam10/conf.c @@ -689,7 +689,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) u32 index; for(index=0; index<256; index++) { - if((sysconf.conf_io_addrx[index+4] == 0)){ + if(sysconf.conf_io_addrx[index+4] == 0) { sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); return index; @@ -697,16 +697,14 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) } return 0; - } static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) { u32 index; - for(index=0; index<64; index++) { - if((sysconf.conf_mmio_addrx[index+8] == 0)){ + if(sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); return index; @@ -714,7 +712,6 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) } return 0; - } static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,

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Patch set updated for coreboot: abb2d0b cpu/x86/pae/pgtbl.c: Unsigned comparison < 0 always false
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6146 -gerrit commit abb2d0b75dbee3b89ce7fa015cf18c10c055d46e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 15:33:30 2014 +1000 cpu/x86/pae/pgtbl.c: Unsigned comparison < 0 always false Comparison of unsigned expression < 0 is always false. Change-Id: Idf4e7846b50f4376a5d33515681efbd773d1caca Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/x86/pae/pgtbl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 9354738..9be415d 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -61,7 +61,7 @@ void *map_2M_page(unsigned long page) void *result; int i; index = cpu_index(); - if ((index < 0) || (index >= CONFIG_MAX_CPUS)) { + if (index >= CONFIG_MAX_CPUS) { return MAPPING_ERROR; } window = page >> 10;

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Patch set updated for coreboot: 785a1f1 southbridge/amd/rsXY0/cmn.c: Incorrect usage of logical vs. bitwise and
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6147 -gerrit commit 785a1f1ae1f67ac962dec063e4bb0f97bf538cdc Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 15:36:57 2014 +1000 southbridge/amd/rsXY0/cmn.c: Incorrect usage of logical vs. bitwise and Spotted by Clang. Change-Id: I26e7acddbff32e978c2bf984c21d9a63337067f8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/rs690/cmn.c | 2 +- src/southbridge/amd/rs780/cmn.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index 36870b3..b00c72b 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -289,7 +289,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); - tmp = (reg >> 4) && 0x3; /* get bit4-6 */ + tmp = (reg >> 4) & 0x3; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ reg += tmp; /* merge */ reg |= 1 << 8; diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index cf09b9a..a5b3c81 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -330,7 +330,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); - tmp = (reg >> 4) && 0x3; /* get bit4-6 */ + tmp = (reg >> 4) & 0x3; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ reg += tmp; /* merge */ reg |= 1 << 8;

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Patch set updated for coreboot: a032be4 northbridge/amd/{gx2, lx}/raminit.c: Initialise `spd_byte`
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6145 -gerrit commit a032be417ccb6f7b906760eb10029bf3e1d2b534 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 15:29:26 2014 +1000 northbridge/amd/{gx2,lx}/raminit.c: Initialise `spd_byte` If the if-else construct falls through to 'else' then spd_byte is used before being initialised. In reality the machine halts before this can happen by 'hcf()' so just initialise to zero to avoid compiler warn. Change-Id: I514dc3d673758f8f546d43a7a0868485d1d8d5ab Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/gx2/raminit.c | 1 + src/northbridge/amd/lx/raminit.c | 1 + 2 files changed, 2 insertions(+) diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index 71d0a16..4de25c9 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -306,6 +306,7 @@ static void setCAS(void) } else if ((casmap0 &= casmap1)) { spd_byte = CASDDR[__builtin_ctz(casmap0)]; } else { + spd_byte = 0; printk(BIOS_EMERG, "DIMM CAS Latencies not compatible\n"); post_code(ERROR_DIFF_DIMMS); hcf(); diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index 6dfb073..4b44d56 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -319,6 +319,7 @@ static void setCAS(void) } else if ((casmap0 &= casmap1)) { spd_byte = CASDDR[__builtin_ctz(casmap0)]; } else { + spd_byte = 0; print_emerg("DIMM CAS Latencies not compatible\n"); post_code(ERROR_DIFF_DIMMS); hcf();

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New patch to review for coreboot: 33dd46b cpu/amd/geode_gx2/cache_as_ram.inc: Illegal ASCII art is illegal
by Edward O'Callaghan 28 Jun '14

28 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6154 -gerrit commit 33dd46b4fe7b2ed17829163784251bbf4df6813b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 19:07:33 2014 +1000 cpu/amd/geode_gx2/cache_as_ram.inc: Illegal ASCII art is illegal Embedding comments inside comments is illegal in the C specification, Clang enforces this. Change-Id: I0a468e4196034b00dfc5860fdbbab7788e4fef77 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/amd/geode_gx2/cache_as_ram.inc | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc index 6a107fe..b01d8c1 100644 --- a/src/cpu/amd/geode_gx2/cache_as_ram.inc +++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc @@ -29,14 +29,14 @@ #include <cpu/amd/gx2def.h> #include <cpu/x86/post_code.h> /*************************************************************************** -/** -/** DCacheSetup -/** -/** Setup data cache for use as RAM for a stack. -/** -/** Max. size data cache =0x4000 (16KB) -/** -/***************************************************************************/ + ** + ** DCacheSetup + ** + ** Setup data cache for use as RAM for a stack. + ** + ** Max. size data cache =0x4000 (16KB) + ** + ***************************************************************************/ DCacheSetup: /* Save the BIST result */ movl %eax, %ebx

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coreboot-gerrit June 2014