coreboot-gerrit June 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: ceaf0fa build: Use clang driver to invocate linker and link compiler-rt
by Edward O'Callaghan 27 Jun '14

27 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5823 -gerrit commit ceaf0fa4b8233cd8d6b5ef5fd9526a6fafc4ea73 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri May 23 10:57:52 2014 +1000 build: Use clang driver to invocate linker and link compiler-rt NOTFORMERGE: This does not _yet_ work with the current clang driver, pending upstream fixes. *** Let the Clang driver frontend invocate the correct target linker and runtime symbols from compiler-rt. *** Requires at least clang 3.5.0 r211866. Change-Id: I8b5a824eab98568a77df82596c175a8f0129c5e7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile | 4 +++- src/arch/x86/Makefile.inc | 6 +++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 195bfe6..3023de4 100644 --- a/Makefile +++ b/Makefile @@ -109,7 +109,9 @@ include $(HAVE_DOTCONFIG) ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) # FIXME: armv7/aarch64 won't build right now -CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-elf -m32 +# NOTE: clang puts compiler-rt under lib/linux/libclang_rt.builtins-i386.a +# this means the triple is i386-linux-elf instead of i386-none-elf +CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 -rtlib=compiler-rt CC_x86_32:=clang ifneq ($(CONFIG_MMX),y) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index c0e908d..fe21cd6 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -209,7 +209,7 @@ romstage-libs ?= $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) --end-group -T $(objgenerated)/romstage_null.ld + $(CC_romstage) $(CFLAGS_romstage) -Wl,-nostartfiles -static -o $@ -L$(obj) -Wl,--start-group $(romstage-objs) $(romstage-libs) -Wl,--end-group -Wl,-T $(objgenerated)/romstage_null.ld else $(CC_romstage) $(CFLAGS_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group endif @@ -221,7 +221,7 @@ endif $(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) --end-group -T $(objgenerated)/romstage_xip.ld + $(CC_romstage) $(CFLAGS_romstage) -Wl,-nostartfiles -static -o $@ -L$(obj) -Wl,--start-group $(romstage-objs) $(romstage-libs) -Wl,--end-group -Wl,-T $(objgenerated)/romstage_xip.ld else $(CC_romstage) $(CFLAGS_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group endif @@ -332,7 +332,7 @@ endif $(objgenerated)/ramstage.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_ramstage) -m elf_i386 -r -o $@ --start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME_ramstage) --end-group + $(CC_ramstage) $(CFLAGS_ramstage) -r -o $@ -Wl,--start-group $(ramstage-objs) $(ramstage-libs) -Wl,--end-group else $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group endif

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Patch merged into coreboot/master: b0195a3 build: Pass correct disassembly flags in Clang build
by gerrit＠coreboot.org 27 Jun '14

27 Jun '14

the following patch was just integrated into master: commit b0195a3325b838bc9bdaa62a76b5125e4b694169 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri May 23 01:32:44 2014 +1000 build: Pass correct disassembly flags in Clang build On SVR4-derived platforms, the character `/' is treated as a comment character, which means that it cannot be used in expressions. The `--divide' option turns `/' into a normal character. This seems to be needed with our local build of binutils since we don't yet use the internal assembler/disassembler of the Clang tooling. Change-Id: I344fc8670fd5d994f3b63308a513dd367aefc7f9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5813 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5813 for details. -gerrit

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Patch merged into coreboot/master: 9b22985 lib/Makefile.inc: Stop gcc.c getting into SMM clang builds
by gerrit＠coreboot.org 27 Jun '14

27 Jun '14

the following patch was just integrated into master: commit 9b229858b2b0887511ae78e1535a422795e77736 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jun 26 18:12:11 2014 +1000 lib/Makefile.inc: Stop gcc.c getting into SMM clang builds The libgcc runtime workarounds found in gcc.c are not needed for compiler-rt used by the Clang toolchain. Stop gcc.c from sneaking into Clang builds while processing boards that use SMM code. Change-Id: I51e8d517784721d28b4d951bd0bebc8b52682a8e Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6121 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> See http://review.coreboot.org/6121 for details. -gerrit

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Patch set updated for coreboot: bbcdbc7 ACPI: Recover type of wakeup in acpi_is_wakeup()
by Kyösti Mälkki 27 Jun '14

27 Jun '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6142 -gerrit commit bbcdbc70425f54e1a40f8509444d41196d884502 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 19 23:29:07 2014 +0300 ACPI: Recover type of wakeup in acpi_is_wakeup() Update acpi_slp_type early in ramstage. Change-Id: I30ec2680d28b880171217e896f48606f8691b099 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/acpi.c | 12 ++++++++++++ src/arch/x86/include/arch/acpi.h | 2 +- src/lib/hardwaremain.c | 5 +++++ 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 012c101..d76882a 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -645,14 +645,26 @@ void acpi_resume(void *wake_vec) /* This is to be filled by SB code - startup value what was found. */ u8 acpi_slp_type = 0; +static void acpi_handoff_wakeup(void) +{ + static int once = 0; + if (once) + return; + if (acpi_get_sleep_type) + acpi_slp_type = acpi_get_sleep_type(); + once = 1; +} + int acpi_is_wakeup(void) { + acpi_handoff_wakeup(); /* Both resume from S2 and resume from S3 restart at CPU reset */ return (acpi_slp_type == 3 || acpi_slp_type == 2); } int acpi_is_wakeup_s3(void) { + acpi_handoff_wakeup(); return (acpi_slp_type == 3); } diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 226957d..9039a90 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -569,7 +569,7 @@ void *acpi_find_wakeup_vector(void); void *acpi_get_wakeup_rsdp(void); void acpi_jump_to_wakeup(void *wakeup_addr); -int acpi_get_sleep_type(void); +int __attribute__((weak)) acpi_get_sleep_type(void); #endif /* IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) */ /* northbridge/amd/amdfam10/amdfam10_acpi.c */ diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index d90e0f6..277d9b7 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -464,6 +464,11 @@ void main(void) post_code(POST_CONSOLE_BOOT_MSG); + /* Handoff sleep type from romstage. */ +#if CONFIG_HAVE_ACPI_RESUME + acpi_is_wakeup(); +#endif + threads_initialize(); /* Schedule the static boot state entries. */

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Patch set updated for coreboot: 0043e88 AGESA boards: Use acpi_is_wakeup_s3()
by Kyösti Mälkki 27 Jun '14

27 Jun '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6143 -gerrit commit 0043e880483346887658cf04de3ed5089194ec33 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jun 27 13:32:59 2014 +0300 AGESA boards: Use acpi_is_wakeup_s3() Change-Id: Ib76ec433710b3a7c26360329a9403585d6f4fe4c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/olivehill/mainboard.c | 10 ++-------- src/mainboard/amd/parmer/mainboard.c | 10 ++-------- src/mainboard/amd/persimmon/mainboard.c | 8 -------- src/mainboard/amd/thatcher/mainboard.c | 10 +--------- src/mainboard/asrock/imb-a180/mainboard.c | 10 ++-------- src/mainboard/asus/f2a85-m/mainboard.c | 10 +--------- src/mainboard/gizmosphere/gizmo/mainboard.c | 8 -------- src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 10 ++-------- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 8 -------- src/mainboard/lippert/frontrunner-af/mainboard.c | 8 -------- src/mainboard/lippert/toucan-af/mainboard.c | 8 -------- 11 files changed, 10 insertions(+), 90 deletions(-) diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c index 3913898..cc6d9f8 100644 --- a/src/mainboard/amd/olivehill/mainboard.c +++ b/src/mainboard/amd/olivehill/mainboard.c @@ -35,15 +35,9 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* - * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the appropriate AGESA/CIMx resume functions. - */ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = acpi_get_sleep_type(); - if (acpi_slp_type == 3) + + if (acpi_is_wakeup_s3()) agesawrapper_fchs3earlyrestore(); -#endif } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index 8aa76ff..214cb21 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -35,15 +35,9 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* - * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the appropriate AGESA/CIMx resume functions. - */ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = acpi_get_sleep_type(); - if (acpi_slp_type == 3) + + if (acpi_is_wakeup_s3()) agesawrapper_fchs3earlyrestore(); -#endif } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index fda503d..6c3e81d 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -154,14 +154,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); -/* - * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the appropriate AGESA/CIMx resume functions. - */ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = acpi_get_sleep_type(); -#endif - /* enable GPP CLK0 thru CLK1 */ /* disable GPP CLK2 thru SLT_GFX_CLK */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c index bfb664f..2eacf76 100644 --- a/src/mainboard/amd/thatcher/mainboard.c +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -51,16 +51,8 @@ static void mainboard_enable(device_t dev) msr.lo &= ~(1 << 23); wrmsr(0xC0011023, msr); - /* - * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the appropriate AGESA/CIMx resume functions. - */ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = acpi_get_sleep_type(); - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) agesawrapper_fchs3earlyrestore(); - -#endif } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/asrock/imb-a180/mainboard.c b/src/mainboard/asrock/imb-a180/mainboard.c index 3913898..cc6d9f8 100644 --- a/src/mainboard/asrock/imb-a180/mainboard.c +++ b/src/mainboard/asrock/imb-a180/mainboard.c @@ -35,15 +35,9 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* - * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the appropriate AGESA/CIMx resume functions. - */ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = acpi_get_sleep_type(); - if (acpi_slp_type == 3) + + if (acpi_is_wakeup_s3()) agesawrapper_fchs3earlyrestore(); -#endif } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c index c37fd76..1a64874 100644 --- a/src/mainboard/asus/f2a85-m/mainboard.c +++ b/src/mainboard/asus/f2a85-m/mainboard.c @@ -51,16 +51,8 @@ static void mainboard_enable(device_t dev) msr.lo &= ~(1 << 23); wrmsr(0xC0011023, msr); - /* - * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the appropriate AGESA/CIMx resume functions. - */ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = acpi_get_sleep_type(); - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) agesawrapper_fchs3earlyrestore(); - -#endif } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index e24b016..78bb6fa 100755 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -59,14 +59,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); -/* - * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the appropriate AGESA/CIMx resume functions. - */ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = acpi_get_sleep_type(); -#endif - /* enable GPP CLK0 thru CLK1 */ /* disable GPP CLK2 thru SLT_GFX_CLK */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index 60a8a55..53c5342 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -47,16 +47,10 @@ static void mainboard_enable(device_t dev) hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH); hudson_enable_smi_generation(); - /* - * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the appropriate AGESA/CIMx resume functions. - */ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = acpi_get_sleep_type(); - if (acpi_slp_type == 3) + + if (acpi_is_wakeup_s3()) agesawrapper_fchs3earlyrestore(); else -#endif pavilion_cold_boot_init(); } diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index 6053550..41f418c 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -156,14 +156,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); -/* - * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the appropriate AGESA/CIMx resume functions. - */ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = acpi_get_sleep_type(); -#endif /* CONFIG_HAVE_ACPI_RESUME */ - /* enable GPP CLK0 thru CLK3 (interleaved) */ /* disable GPP CLK4 thru SLT_GFX_CLK */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 4e16b3e..f813358 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -167,14 +167,6 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); dev->ops->init = init; -/* - * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the appropriate AGESA/CIMx resume functions. - */ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = acpi_get_sleep_type(); -#endif - /* enable GPP CLK0 */ /* disable GPP CLK1 thru SLT_GFX_CLK */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index 7518203..6608930 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -134,14 +134,6 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); dev->ops->init = init; -/* - * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the appropriate AGESA/CIMx resume functions. - */ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = acpi_get_sleep_type(); -#endif - /* enable GPP CLK0 thru CLK1 */ /* disable GPP CLK2 thru SLT_GFX_CLK */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);

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Patch set updated for coreboot: 46a5c64 AGESA: Clean separation of SPI flash
by Kyösti Mälkki 27 Jun '14

27 Jun '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6085 -gerrit commit 46a5c64a9109d75167d14b0a9e9ef345b29c6f3c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 19 16:51:54 2014 +0300 AGESA: Clean separation of SPI flash To be precise, wakeup from S3 does not involve SPI writing, while preparing for it on cold power-ons currently does. For S3DataTypeMtrr storage is changed such that the first 4 bytes is the length of data stored like with the other two S3DataType. Change-Id: Id920650474530d4191075da4ef70daa66c904c5b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/Makefile.inc | 2 + src/cpu/amd/agesa/s3_resume.c | 110 +++++++------------------- src/cpu/amd/agesa/s3_resume.h | 2 + src/cpu/amd/agesa/spi.c | 54 +++++++++++++ src/southbridge/amd/agesa/hudson/Makefile.inc | 2 +- src/southbridge/amd/cimx/sb800/Makefile.inc | 2 +- 6 files changed, 90 insertions(+), 82 deletions(-) diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index f403d30..d6d2f24 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -25,6 +25,8 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c +ramstage-$(CONFIG_SPI_FLASH) += spi.c + cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc romstage-y += heapmanager.c diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 4244786..1899408 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -35,11 +35,6 @@ #include "s3_resume.h" #include "agesawrapper.h" -#ifndef __PRE_RAM__ -#include <spi-generic.h> -#include <spi_flash.h> -#endif - /* The size needs to be 4k aligned, which is the sector size of most flashes. */ #define S3_DATA_VOLATILE_SIZE 0x6000 #define S3_DATA_MTRR_SIZE 0x1000 @@ -85,7 +80,7 @@ void restore_mtrr(void) u32 pos, size; get_s3nv_data(S3DataTypeMTRR, &pos, &size); - msrPtr = (UINT32 *)pos; + msrPtr = (UINT32 *)(pos + sizeof(UINT32)); disable_cache(); @@ -178,46 +173,24 @@ static void move_stack_high_mem(void) #endif #ifndef __PRE_RAM__ -static void write_mtrr(struct spi_flash *flash, u32 *p_nvram_pos, unsigned idx) +/* FIXME: Why store MTRR in SPI, just use CBMEM ? */ +static u8 mtrr_store[S3_DATA_MTRR_SIZE]; + +static void write_mtrr(u8 **p_nvram_pos, unsigned idx) { msr_t msr_data; msr_data = rdmsr(idx); -#if CONFIG_AMD_SB_SPI_TX_LEN >= 8 - flash->write(flash, *p_nvram_pos, 8, &msr_data); - *p_nvram_pos += 8; -#else - flash->write(flash, *p_nvram_pos, 4, &msr_data.lo); - *p_nvram_pos += 4; - flash->write(flash, *p_nvram_pos, 4, &msr_data.hi); - *p_nvram_pos += 4; -#endif + memcpy(*p_nvram_pos, &msr_data, sizeof(msr_data)); + *p_nvram_pos += sizeof(msr_data); } -#endif void OemAgesaSaveMtrr(void) { -#ifndef __PRE_RAM__ msr_t msr_data; u32 i; - struct spi_flash *flash; - u32 pos, size; - get_s3nv_data(S3DataTypeMTRR, &pos, &size); - - spi_init(); - - flash = spi_flash_probe(0, 0, 0, 0); - if (!flash) { - printk(BIOS_DEBUG, "Could not find SPI device\n"); - return; - } - - flash->spi->rw = SPI_WRITE_FLAG; - spi_claim_bus(flash->spi); - - flash->erase(flash, pos, size); - u32 nvram_pos = pos; + u8 *nvram_pos = (u8 *) mtrr_store; /* Enable access to AMD RdDram and WrDram extension bits */ msr_data = rdmsr(SYS_CFG); @@ -225,12 +198,12 @@ void OemAgesaSaveMtrr(void) wrmsr(SYS_CFG, msr_data); /* Fixed MTRRs */ - write_mtrr(flash, &nvram_pos, 0x250); - write_mtrr(flash, &nvram_pos, 0x258); - write_mtrr(flash, &nvram_pos, 0x259); + write_mtrr(&nvram_pos, 0x250); + write_mtrr(&nvram_pos, 0x258); + write_mtrr(&nvram_pos, 0x259); for (i = 0x268; i < 0x270; i++) - write_mtrr(flash, &nvram_pos, i); + write_mtrr(&nvram_pos, i); /* Disable access to AMD RdDram and WrDram extension bits */ msr_data = rdmsr(SYS_CFG); @@ -239,20 +212,32 @@ void OemAgesaSaveMtrr(void) /* Variable MTRRs */ for (i = 0x200; i < 0x210; i++) - write_mtrr(flash, &nvram_pos, i); + write_mtrr(&nvram_pos, i); /* SYS_CFG */ - write_mtrr(flash, &nvram_pos, 0xC0010010); + write_mtrr(&nvram_pos, 0xC0010010); /* TOM */ - write_mtrr(flash, &nvram_pos, 0xC001001A); + write_mtrr(&nvram_pos, 0xC001001A); /* TOM2 */ - write_mtrr(flash, &nvram_pos, 0xC001001D); + write_mtrr(&nvram_pos, 0xC001001D); - flash->spi->rw = SPI_WRITE_FLAG; - spi_release_bus(flash->spi); +#if IS_ENABLED(CONFIG_SPI_FLASH) + u32 pos, size; + get_s3nv_data(S3DataTypeMTRR, &pos, &size); + spi_SaveS3info(pos, size, mtrr_store, nvram_pos - (u8 *) mtrr_store); +#endif +} +u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) +{ +#if IS_ENABLED(CONFIG_SPI_FLASH) + u32 pos, size; + get_s3nv_data(S3DataType, &pos, &size); + spi_SaveS3info(pos, size, Data, DataSize); #endif + return AGESA_SUCCESS; } +#endif void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data) { @@ -274,41 +259,6 @@ void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data) } } -#ifndef __PRE_RAM__ -u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) -{ - struct spi_flash *flash; - - u32 pos, size; - get_s3nv_data(S3DataType, &pos, &size); - - spi_init(); - flash = spi_flash_probe(0, 0, 0, 0); - if (!flash) { - printk(BIOS_DEBUG, "Could not find SPI device\n"); - /* Dont make flow stop. */ - return AGESA_SUCCESS; - } - - flash->spi->rw = SPI_WRITE_FLAG; - spi_claim_bus(flash->spi); - - flash->erase(flash, pos, size); - flash->write(flash, pos, sizeof(DataSize), &DataSize); - - u32 nvram_pos; - for (nvram_pos = 0; nvram_pos < DataSize - CONFIG_AMD_SB_SPI_TX_LEN; nvram_pos += CONFIG_AMD_SB_SPI_TX_LEN) { - flash->write(flash, nvram_pos + pos + 4, CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(Data + nvram_pos)); - } - flash->write(flash, nvram_pos + pos + 4, DataSize % CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(Data + nvram_pos)); - - flash->spi->rw = SPI_WRITE_FLAG; - spi_release_bus(flash->spi); - - return AGESA_SUCCESS; -} -#endif - #ifdef __PRE_RAM__ static void set_resume_cache(void) { diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index b72e8a2..14984df 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -33,4 +33,6 @@ u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data); void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data); void OemAgesaSaveMtrr (void); +void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len); + #endif diff --git a/src/cpu/amd/agesa/spi.c b/src/cpu/amd/agesa/spi.c new file mode 100644 index 0000000..f4ffa62 --- /dev/null +++ b/src/cpu/amd/agesa/spi.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <spi-generic.h> +#include <spi_flash.h> + +#include "s3_resume.h" + +void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) +{ + struct spi_flash *flash; + + spi_init(); + flash = spi_flash_probe(0, 0, 0, 0); + if (!flash) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + /* Dont make flow stop. */ + return; + } + + flash->spi->rw = SPI_WRITE_FLAG; + spi_claim_bus(flash->spi); + + flash->erase(flash, pos, size); + flash->write(flash, pos, sizeof(len), &len); + + u32 nvram_pos; + for (nvram_pos = 0; nvram_pos < len - CONFIG_AMD_SB_SPI_TX_LEN; nvram_pos += CONFIG_AMD_SB_SPI_TX_LEN) { + flash->write(flash, nvram_pos + pos + 4, CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(buf + nvram_pos)); + } + flash->write(flash, nvram_pos + pos + 4, len % CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(buf + nvram_pos)); + + flash->spi->rw = SPI_WRITE_FLAG; + spi_release_bus(flash->spi); + + return; +} diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 398ca90..b0437d9 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -16,7 +16,7 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c -ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c +ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += resume.c romstage-y += imc.c diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 2ed5096..5cf989f 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -31,7 +31,7 @@ ramstage-y += reset.c ramstage-$(CONFIG_SB800_MANUAL_FAN_CONTROL) += fan.c ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c -ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c +ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ../../sb800/enable_usbdebug.c

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Patch set updated for coreboot: aa2e63d AGESA boards: Add prepare_for_resume()
by Kyösti Mälkki 27 Jun '14

27 Jun '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6084 -gerrit commit aa2e63ddaa06d55f854c34f8a4a08d8a6f6337eb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jun 18 09:55:26 2014 +0300 AGESA boards: Add prepare_for_resume() Use one common implementation for all AGESA platforms. Change-Id: I410f8e0a9c75445882d67659cde00004eb7ad6b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 42 ++++++++++++++++++------- src/cpu/amd/agesa/s3_resume.h | 5 +-- src/mainboard/amd/olivehill/romstage.c | 25 +-------------- src/mainboard/amd/parmer/romstage.c | 25 +-------------- src/mainboard/amd/persimmon/romstage.c | 26 +-------------- src/mainboard/amd/thatcher/romstage.c | 25 +-------------- src/mainboard/asrock/imb-a180/romstage.c | 25 +-------------- src/mainboard/asus/f2a85-m/romstage.c | 25 +-------------- src/mainboard/gizmosphere/gizmo/romstage.c | 26 +-------------- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 25 +-------------- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 26 +-------------- src/mainboard/lippert/frontrunner-af/romstage.c | 26 +-------------- src/mainboard/lippert/toucan-af/romstage.c | 26 +-------------- 13 files changed, 42 insertions(+), 285 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 2efe6be..4244786 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/amd/car.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/cache.h> #include <cbmem.h> @@ -142,7 +143,8 @@ void restore_mtrr(void) wrmsr(SYS_CFG, msr_data); } -void *backup_resume(void) +#ifdef __PRE_RAM__ +static void *backup_resume(void) { void *resume_backup_memory; @@ -160,7 +162,7 @@ void *backup_resume(void) return resume_backup_memory; } -void move_stack_high_mem(void) +static void move_stack_high_mem(void) { void *high_stack; @@ -173,6 +175,7 @@ void move_stack_high_mem(void) (high_stack - BSP_STACK_BASE_ADDR) :); } +#endif #ifndef __PRE_RAM__ static void write_mtrr(struct spi_flash *flash, u32 *p_nvram_pos, unsigned idx) @@ -306,7 +309,8 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) } #endif -void set_resume_cache(void) +#ifdef __PRE_RAM__ +static void set_resume_cache(void) { msr_t msr; @@ -331,14 +335,28 @@ void set_resume_cache(void) enable_cache(); } -void s3_resume(void) +void prepare_for_resume(void) { - int status; - - printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); - status = agesawrapper_amds3laterestore(); - if (status) - printk(BIOS_DEBUG, "error level: %x \n", (u32) status); - else - printk(BIOS_DEBUG, "passed.\n"); + printk(BIOS_DEBUG, "Find resume memory location\n"); + void *resume_backup_memory = backup_resume(); + + post_code(0x62); + printk(BIOS_DEBUG, "Move CAR stack.\n"); + move_stack_high_mem(); + printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); + + post_code(0x63); + disable_cache_as_ram(); + printk(BIOS_DEBUG, "CAR disabled.\n"); + set_resume_cache(); + + /* + * Copy the system memory that is in the ramstage area to the + * reserved area. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); + + printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); } +#endif diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index fd3f29e..b72e8a2 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -27,10 +27,7 @@ typedef enum { } S3_DATA_TYPE; void restore_mtrr(void); -void s3_resume(void); -void *backup_resume(void); -void set_resume_cache(void); -void move_stack_high_mem(void); +void prepare_for_resume(void); u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data); void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 8d2156e..dc52d16 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -41,9 +41,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA @@ -133,27 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); - printk(BIOS_DEBUG, "Find resume memory location\n"); - resume_backup_memory = (void *)backup_resume(); - - post_code(0x62); - printk(BIOS_DEBUG, "Move CAR stack.\n"); - move_stack_high_mem(); - printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); - - post_code(0x63); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "CAR disabled.\n"); - set_resume_cache(); - - /* - * Copy the system memory that is in the ramstage area to the - * reserved area. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); - - printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + prepare_for_resume(); } #endif diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 36a6b8a..8c0afa5 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -41,9 +41,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif val = agesawrapper_amdinitmmio(); hudson_lpc_port80(); @@ -116,27 +113,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); - printk(BIOS_DEBUG, "Find resume memory location\n"); - resume_backup_memory = (void *)backup_resume(); - - post_code(0x62); - printk(BIOS_DEBUG, "Move CAR stack.\n"); - move_stack_high_mem(); - printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); - - post_code(0x63); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "CAR disabled.\n"); - set_resume_cache(); - - /* - * Copy the system memory that is in the ramstage area to the - * reserved area. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); - - printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + prepare_for_resume(); } #endif diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 5908421..32b85c3 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -50,10 +50,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif - /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) @@ -145,27 +141,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); - printk(BIOS_DEBUG, "Find resume memory location\n"); - resume_backup_memory = backup_resume(); - - post_code(0x62); - printk(BIOS_DEBUG, "Move CAR stack.\n"); - move_stack_high_mem(); - printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); - - post_code(0x63); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "CAR disabled.\n"); - set_resume_cache(); - - /* - * Copy the system memory that is in the ramstage area to the - * reserved area. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); - - printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + prepare_for_resume(); } #endif diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 1461c4c..063d2d9 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; u8 byte; device_t dev; -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif val = agesawrapper_amdinitmmio(); hudson_lpc_port80(); @@ -133,27 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); - printk(BIOS_DEBUG, "Find resume memory location\n"); - resume_backup_memory = (void *)backup_resume(); - - post_code(0x62); - printk(BIOS_DEBUG, "Move CAR stack.\n"); - move_stack_high_mem(); - printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); - - post_code(0x63); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "CAR disabled.\n"); - set_resume_cache(); - - /* - * Copy the system memory that is in the ramstage area to the - * reserved area. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); - - printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + prepare_for_resume(); } #endif diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 382ad5b..8ed5e05 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val, t32; u32 *addr32; -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA @@ -157,27 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); - printk(BIOS_DEBUG, "Find resume memory location\n"); - resume_backup_memory = (void *)backup_resume(); - - post_code(0x62); - printk(BIOS_DEBUG, "Move CAR stack.\n"); - move_stack_high_mem(); - printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); - - post_code(0x63); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "CAR disabled.\n"); - set_resume_cache(); - - /* - * Copy the system memory that is in the ramstage area to the - * reserved area. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); - - printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + prepare_for_resume(); } #endif diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 03f4bb1..c8e102b 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -75,9 +75,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); #endif -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif val = agesawrapper_amdinitmmio(); if (!cpu_init_detectedx && boot_cpu()) { @@ -181,27 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); - printk(BIOS_DEBUG, "Find resume memory location\n"); - resume_backup_memory = (void *)backup_resume(); - - post_code(0x62); - printk(BIOS_DEBUG, "Move CAR stack.\n"); - move_stack_high_mem(); - printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); - - post_code(0x63); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "CAR disabled.\n"); - set_resume_cache(); - - /* - * Copy the system memory that is in the ramstage area to the - * reserved area. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); - - printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + prepare_for_resume(); } #endif diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 63a2be8..c611992 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -51,10 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; msr_t msr; -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif - /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) @@ -153,27 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); - printk(BIOS_DEBUG, "Find resume memory location\n"); - resume_backup_memory = backup_resume(); - - post_code(0x62); - printk(BIOS_DEBUG, "Move CAR stack.\n"); - move_stack_high_mem(); - printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); - - post_code(0x63); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "CAR disabled.\n"); - set_resume_cache(); - - /* - * Copy the system memory that is in the ramstage area to the - * reserved area. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); - - printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + prepare_for_resume(); } #endif diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index cb4268c..4b433c9 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -38,9 +38,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif val = agesawrapper_amdinitmmio(); hudson_lpc_port80(); @@ -113,27 +110,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); - printk(BIOS_DEBUG, "Find resume memory location\n"); - resume_backup_memory = (void *)backup_resume(); - - post_code(0x62); - printk(BIOS_DEBUG, "Move CAR stack.\n"); - move_stack_high_mem(); - printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); - - post_code(0x63); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "CAR disabled.\n"); - set_resume_cache(); - - /* - * Copy the system memory that is in the ramstage area to the - * reserved area. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); - - printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + prepare_for_resume(); } #endif diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 25459d7..b49ea81 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -66,10 +66,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif - /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) @@ -161,27 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); - printk(BIOS_DEBUG, "Find resume memory location\n"); - resume_backup_memory = backup_resume(); - - post_code(0x62); - printk(BIOS_DEBUG, "Move CAR stack.\n"); - move_stack_high_mem(); - printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); - - post_code(0x63); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "CAR disabled.\n"); - set_resume_cache(); - - /* - * Copy the system memory that is in the ramstage area to the - * reserved area. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); - - printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + prepare_for_resume(); } #endif /* CONFIG_HAVE_ACPI_RESUME */ diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 7945883..06b365a 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -49,10 +49,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif - /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) @@ -148,27 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); - printk(BIOS_DEBUG, "Find resume memory location\n"); - resume_backup_memory = backup_resume(); - - post_code(0x62); - printk(BIOS_DEBUG, "Move CAR stack.\n"); - move_stack_high_mem(); - printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); - - post_code(0x63); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "CAR disabled.\n"); - set_resume_cache(); - - /* - * Copy the system memory that is in the ramstage area to the - * reserved area. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); - - printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + prepare_for_resume(); } #endif diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index b8bd744..6a5c580 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -50,10 +50,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif - /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) @@ -149,27 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); - printk(BIOS_DEBUG, "Find resume memory location\n"); - resume_backup_memory = backup_resume(); - - post_code(0x62); - printk(BIOS_DEBUG, "Move CAR stack.\n"); - move_stack_high_mem(); - printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); - - post_code(0x63); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "CAR disabled.\n"); - set_resume_cache(); - - /* - * Copy the system memory that is in the ramstage area to the - * reserved area. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); - - printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + prepare_for_resume(); } #endif

1 0

Patch set updated for coreboot: 95caf61 AGESA boards: Use acpi_s3_resume_allowed()
by Kyösti Mälkki 27 Jun '14

27 Jun '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6067 -gerrit commit 95caf611361542ee6fe971c55d365438143e150d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jun 18 09:10:53 2014 +0300 AGESA boards: Use acpi_s3_resume_allowed() This adds use of BROKEN_CAR_MIGRATE to include CBMEM symbols for the build of romstage also for boards without HAVE_ACPI_RESUME. These symbols got exposed as the use of preprocessor directives was reduced. We expect the linker to do a fair job and optimize away function bodies that are on unreachable execution paths. Change-Id: Ibf5181d3eecb87ce647abe0be01072594b05aa5f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/Kconfig | 1 + src/cpu/amd/agesa/Makefile.inc | 4 ++-- src/mainboard/amd/olivehill/agesawrapper.c | 2 -- src/mainboard/amd/olivehill/romstage.c | 7 ++----- src/mainboard/amd/parmer/agesawrapper.c | 2 -- src/mainboard/amd/parmer/romstage.c | 7 ++----- src/mainboard/amd/persimmon/agesawrapper.c | 2 -- src/mainboard/amd/persimmon/romstage.c | 7 ++----- src/mainboard/amd/thatcher/agesawrapper.c | 2 -- src/mainboard/amd/thatcher/romstage.c | 7 ++----- src/mainboard/asrock/imb-a180/agesawrapper.c | 2 -- src/mainboard/asrock/imb-a180/romstage.c | 7 ++----- src/mainboard/asus/f2a85-m/agesawrapper.c | 2 -- src/mainboard/asus/f2a85-m/romstage.c | 7 ++----- src/mainboard/gizmosphere/gizmo/agesawrapper.c | 2 -- src/mainboard/gizmosphere/gizmo/romstage.c | 7 ++----- src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c | 2 -- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 7 ++----- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 2 -- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 7 ++----- src/mainboard/lippert/frontrunner-af/agesawrapper.c | 2 -- src/mainboard/lippert/frontrunner-af/romstage.c | 7 ++----- src/mainboard/lippert/toucan-af/agesawrapper.c | 2 -- src/mainboard/lippert/toucan-af/romstage.c | 7 ++----- 24 files changed, 25 insertions(+), 79 deletions(-) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index b53e4b0..e982a83 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -32,6 +32,7 @@ config CPU_AMD_AGESA select TSC_SYNC_LFENCE select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER + select BROKEN_CAR_MIGRATE select SPI_FLASH if HAVE_ACPI_RESUME if CPU_AMD_AGESA diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index d6d2f24..1f29664 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -23,8 +23,8 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb -romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c -ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c +romstage-y += s3_resume.c +ramstage-y += s3_resume.c ramstage-$(CONFIG_SPI_FLASH) += spi.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c index 158e758..8e3cb61 100644 --- a/src/mainboard/amd/olivehill/agesawrapper.c +++ b/src/mainboard/amd/olivehill/agesawrapper.c @@ -425,7 +425,6 @@ agesawrapper_amdlaterunaptask ( return (UINT32)Status; } -#if CONFIG_HAVE_ACPI_RESUME UINT32 agesawrapper_amdinitresume(VOID) { @@ -627,7 +626,6 @@ UINT32 agesawrapper_amdS3Save(VOID) } #endif /* #ifndef __PRE_RAM__ */ -#endif /* CONFIG_HAVE_ACPI_RESUME */ UINT32 agesawrapper_amdreadeventlog ( diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index dc52d16..c979456 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -92,9 +92,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); -#if CONFIG_HAVE_ACPI_RESUME - if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ -#endif + int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + if (!s3resume) { post_code(0x40); val = agesawrapper_amdinitpost (); if(val) { @@ -110,7 +109,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); -#if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); @@ -132,7 +130,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x61); prepare_for_resume(); } -#endif outb(0xEA, 0xCD6); outb(0x1, 0xcd7); diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index 55b31e1..85c1474 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -426,7 +426,6 @@ agesawrapper_amdlaterunaptask ( return (UINT32)Status; } -#if CONFIG_HAVE_ACPI_RESUME UINT32 agesawrapper_amdinitresume(VOID) { @@ -630,7 +629,6 @@ UINT32 agesawrapper_amdS3Save(VOID) } #endif /* #ifndef __PRE_RAM__ */ -#endif /* CONFIG_HAVE_ACPI_RESUME */ UINT32 agesawrapper_amdreadeventlog ( diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 8c0afa5..b0fa5d9 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -76,9 +76,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); -#if CONFIG_HAVE_ACPI_RESUME - if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ -#endif + int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + if (!s3resume) { post_code(0x40); val = agesawrapper_amdinitpost (); if(val) { @@ -93,7 +92,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); disable_cache_as_ram(); -#if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); @@ -115,7 +113,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x61); prepare_for_resume(); } -#endif post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 8b7e48d..cfd0eee 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -433,7 +433,6 @@ agesawrapper_amdinitlate ( return (UINT32)Status; } -#if CONFIG_HAVE_ACPI_RESUME UINT32 agesawrapper_amdinitresume ( VOID @@ -565,7 +564,6 @@ agesawrapper_amdS3Save ( return (UINT32)Status; } #endif /* #ifndef __PRE_RAM__ */ -#endif /* CONFIG_HAVE_ACPI_RESUME */ UINT32 agesawrapper_amdlaterunaptask ( diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 32b85c3..f6f2309 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -102,9 +102,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); -#if CONFIG_HAVE_ACPI_RESUME - if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ -#endif + int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + if (!s3resume) { post_code(0x40); printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost (); @@ -121,7 +120,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); -#if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); @@ -143,7 +141,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x61); prepare_for_resume(); } -#endif post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index 4a97a40..7ab9e44 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -423,7 +423,6 @@ agesawrapper_amdlaterunaptask ( return (UINT32)Status; } -#if CONFIG_HAVE_ACPI_RESUME UINT32 agesawrapper_amdinitresume(VOID) { @@ -632,7 +631,6 @@ UINT32 agesawrapper_amdS3Save(VOID) } #endif /* #ifndef __PRE_RAM__ */ -#endif /* CONFIG_HAVE_ACPI_RESUME */ UINT32 agesawrapper_amdreadeventlog ( diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 063d2d9..10dac12 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -93,9 +93,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); -#if CONFIG_HAVE_ACPI_RESUME - if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ -#endif + int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + if (!s3resume) { post_code(0x40); val = agesawrapper_amdinitpost (); if(val) { @@ -110,7 +109,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); disable_cache_as_ram(); -#if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); @@ -132,7 +130,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x61); prepare_for_resume(); } -#endif post_code(0x50); copy_and_run(); diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c index 4e9e77b..083de3d 100644 --- a/src/mainboard/asrock/imb-a180/agesawrapper.c +++ b/src/mainboard/asrock/imb-a180/agesawrapper.c @@ -454,7 +454,6 @@ agesawrapper_amdlaterunaptask ( return (UINT32)Status; } -#if CONFIG_HAVE_ACPI_RESUME UINT32 agesawrapper_amdinitresume(VOID) { @@ -656,7 +655,6 @@ UINT32 agesawrapper_amdS3Save(VOID) } #endif /* #ifndef __PRE_RAM__ */ -#endif /* CONFIG_HAVE_ACPI_RESUME */ UINT32 agesawrapper_amdreadeventlog ( diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 8ed5e05..a818e03 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -116,9 +116,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); -#if CONFIG_HAVE_ACPI_RESUME - if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ -#endif + int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + if (!s3resume) { post_code(0x40); val = agesawrapper_amdinitpost (); if(val) { @@ -134,7 +133,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); -#if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); @@ -156,7 +154,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x61); prepare_for_resume(); } -#endif outb(0xEA, 0xCD6); outb(0x1, 0xcd7); diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c index 7a25719..2a3502a 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.c +++ b/src/mainboard/asus/f2a85-m/agesawrapper.c @@ -438,7 +438,6 @@ agesawrapper_amdlaterunaptask ( return (UINT32)Status; } -#if CONFIG_HAVE_ACPI_RESUME UINT32 agesawrapper_amdinitresume(VOID) { @@ -647,7 +646,6 @@ UINT32 agesawrapper_amdS3Save(VOID) } #endif /* #ifndef __PRE_RAM__ */ -#endif /* CONFIG_HAVE_ACPI_RESUME */ UINT32 agesawrapper_amdreadeventlog ( diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index c8e102b..f50f334 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -141,9 +141,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); -#if CONFIG_HAVE_ACPI_RESUME - if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ -#endif + int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + if (!s3resume) { post_code(0x40); val = agesawrapper_amdinitpost (); if(val) { @@ -158,7 +157,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); disable_cache_as_ram(); -#if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); @@ -180,7 +178,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x61); prepare_for_resume(); } -#endif post_code(0x50); copy_and_run(); diff --git a/src/mainboard/gizmosphere/gizmo/agesawrapper.c b/src/mainboard/gizmosphere/gizmo/agesawrapper.c index becfb45..4b29128 100755 --- a/src/mainboard/gizmosphere/gizmo/agesawrapper.c +++ b/src/mainboard/gizmosphere/gizmo/agesawrapper.c @@ -453,7 +453,6 @@ agesawrapper_amdinitlate ( return (UINT32)Status; } -#if CONFIG_HAVE_ACPI_RESUME UINT32 agesawrapper_amdinitresume ( VOID @@ -585,7 +584,6 @@ agesawrapper_amdS3Save ( return (UINT32)Status; } #endif /* #ifndef __PRE_RAM__ */ -#endif /* CONFIG_HAVE_ACPI_RESUME */ UINT32 agesawrapper_amdlaterunaptask ( diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index c611992..5def470 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -110,9 +110,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); -#if CONFIG_HAVE_ACPI_RESUME - if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ -#endif + int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + if (!s3resume) { post_code(0x40); printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost (); @@ -129,7 +128,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); -#if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); @@ -151,7 +149,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x61); prepare_for_resume(); } -#endif post_code(0x50); copy_and_run(); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c index 0174d42..23cdbfa 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c @@ -436,7 +436,6 @@ agesawrapper_amdlaterunaptask ( return (UINT32)Status; } -#if CONFIG_HAVE_ACPI_RESUME UINT32 agesawrapper_amdinitresume(VOID) { @@ -640,7 +639,6 @@ UINT32 agesawrapper_amdS3Save(VOID) } #endif /* #ifndef __PRE_RAM__ */ -#endif /* CONFIG_HAVE_ACPI_RESUME */ UINT32 agesawrapper_amdreadeventlog ( diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index 4b433c9..38991af 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -73,9 +73,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); -#if CONFIG_HAVE_ACPI_RESUME - if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ -#endif + int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + if (!s3resume) { post_code(0x40); val = agesawrapper_amdinitpost (); if(val) { @@ -90,7 +89,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); disable_cache_as_ram(); -#if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); @@ -112,7 +110,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x61); prepare_for_resume(); } -#endif post_code(0x50); copy_and_run(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index 7cd3899..ed70fc8 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -394,7 +394,6 @@ AGESA_STATUS agesawrapper_amdinitlate(void) return status; } -#if CONFIG_HAVE_ACPI_RESUME AGESA_STATUS agesawrapper_amdinitresume(void) { AGESA_STATUS status; @@ -517,7 +516,6 @@ AGESA_STATUS agesawrapper_amdS3Save(void) return status; } #endif /* #ifndef __PRE_RAM__ */ -#endif /* CONFIG_HAVE_ACPI_RESUME */ AGESA_STATUS agesawrapper_amdlaterunaptask ( uint32_t Func, diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index b49ea81..7f9cb18 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -118,9 +118,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); -#if CONFIG_HAVE_ACPI_RESUME - if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ -#endif + int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + if (!s3resume) { post_code(0x40); printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost (); @@ -137,7 +136,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); -#if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); @@ -159,7 +157,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x61); prepare_for_resume(); } -#endif /* CONFIG_HAVE_ACPI_RESUME */ post_code(0x50); copy_and_run(); diff --git a/src/mainboard/lippert/frontrunner-af/agesawrapper.c b/src/mainboard/lippert/frontrunner-af/agesawrapper.c index 14c6cd0..99a32f4 100644 --- a/src/mainboard/lippert/frontrunner-af/agesawrapper.c +++ b/src/mainboard/lippert/frontrunner-af/agesawrapper.c @@ -452,7 +452,6 @@ agesawrapper_amdinitlate ( return (UINT32)Status; } -#if CONFIG_HAVE_ACPI_RESUME UINT32 agesawrapper_amdinitresume ( VOID @@ -584,7 +583,6 @@ agesawrapper_amdS3Save ( return (UINT32)Status; } #endif /* #ifndef __PRE_RAM__ */ -#endif /* CONFIG_HAVE_ACPI_RESUME */ UINT32 agesawrapper_amdlaterunaptask ( diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 06b365a..b65834e 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -101,9 +101,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); -#if CONFIG_HAVE_ACPI_RESUME - if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ -#endif + int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + if (!s3resume) { post_code(0x40); printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost (); @@ -124,7 +123,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); -#if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); @@ -146,7 +144,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x61); prepare_for_resume(); } -#endif post_code(0x50); copy_and_run(); diff --git a/src/mainboard/lippert/toucan-af/agesawrapper.c b/src/mainboard/lippert/toucan-af/agesawrapper.c index 14c6cd0..99a32f4 100644 --- a/src/mainboard/lippert/toucan-af/agesawrapper.c +++ b/src/mainboard/lippert/toucan-af/agesawrapper.c @@ -452,7 +452,6 @@ agesawrapper_amdinitlate ( return (UINT32)Status; } -#if CONFIG_HAVE_ACPI_RESUME UINT32 agesawrapper_amdinitresume ( VOID @@ -584,7 +583,6 @@ agesawrapper_amdS3Save ( return (UINT32)Status; } #endif /* #ifndef __PRE_RAM__ */ -#endif /* CONFIG_HAVE_ACPI_RESUME */ UINT32 agesawrapper_amdlaterunaptask ( diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 6a5c580..ff2697b 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -102,9 +102,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); -#if CONFIG_HAVE_ACPI_RESUME - if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ -#endif + int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + if (!s3resume) { post_code(0x40); printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost (); @@ -125,7 +124,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); -#if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); @@ -147,7 +145,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x61); prepare_for_resume(); } -#endif post_code(0x50); copy_and_run();

1 0

Patch set updated for coreboot: c36664a AGESA: Add agesawrapper_post_device()
by Kyösti Mälkki 27 Jun '14

27 Jun '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6132 -gerrit commit c36664a61f58416af28c5f1b975c7d6717b00a78 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 19 23:12:15 2014 +0300 AGESA: Add agesawrapper_post_device() NOTE: The procedure is moved across a collected timestamp TS_WRITE_TABLES, so the delay of SPI erase/write will be accounted for in an earlier entry in cbmem -t output. Change-Id: I0f082e7af1769c8d7d03cdd51fdb5dacbf3402b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/Makefile.inc | 1 + src/cpu/amd/agesa/amd_late_init.c | 51 ++++++++++++++++++++++ src/mainboard/amd/dinar/agesawrapper.h | 1 + src/mainboard/amd/dinar/get_bus_conf.c | 22 ---------- src/mainboard/amd/inagua/agesawrapper.h | 1 + src/mainboard/amd/inagua/get_bus_conf.c | 21 --------- src/mainboard/amd/olivehill/get_bus_conf.c | 35 --------------- src/mainboard/amd/parmer/get_bus_conf.c | 35 --------------- src/mainboard/amd/persimmon/get_bus_conf.c | 34 --------------- src/mainboard/amd/south_station/agesawrapper.h | 1 + src/mainboard/amd/south_station/get_bus_conf.c | 21 --------- src/mainboard/amd/thatcher/get_bus_conf.c | 35 --------------- src/mainboard/amd/torpedo/agesawrapper.h | 1 + src/mainboard/amd/torpedo/get_bus_conf.c | 23 ---------- src/mainboard/amd/union_station/agesawrapper.h | 1 + src/mainboard/amd/union_station/get_bus_conf.c | 21 --------- src/mainboard/asrock/e350m1/agesawrapper.h | 1 + src/mainboard/asrock/e350m1/get_bus_conf.c | 21 --------- src/mainboard/asrock/imb-a180/get_bus_conf.c | 35 --------------- src/mainboard/asus/f2a85-m/get_bus_conf.c | 35 --------------- src/mainboard/gizmosphere/gizmo/get_bus_conf.c | 34 --------------- src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c | 35 --------------- src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c | 37 ---------------- .../lippert/frontrunner-af/get_bus_conf.c | 34 --------------- src/mainboard/lippert/toucan-af/get_bus_conf.c | 34 --------------- src/mainboard/supermicro/h8qgi/agesawrapper.h | 1 + src/mainboard/supermicro/h8qgi/get_bus_conf.c | 22 ---------- src/mainboard/supermicro/h8scm/agesawrapper.h | 1 + src/mainboard/supermicro/h8scm/get_bus_conf.c | 22 ---------- src/mainboard/tyan/s8226/agesawrapper.h | 1 + src/mainboard/tyan/s8226/get_bus_conf.c | 22 ---------- 31 files changed, 61 insertions(+), 578 deletions(-) diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 1f29664..beba040 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -31,6 +31,7 @@ cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc romstage-y += heapmanager.c ramstage-y += heapmanager.c +ramstage-y += amd_late_init.c ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c new file mode 100644 index 0000000..e08b159 --- /dev/null +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <bootstate.h> +#include <console/console.h> + +#include "agesawrapper.h" + +void get_bus_conf(void); + +static void agesawrapper_post_device(void *unused) +{ + u32 status; + if (acpi_is_wakeup_s3()) + return; + + status = agesawrapper_amdinitlate(); + if (status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + + if (!acpi_s3_resume_allowed()) + return; + + status = agesawrapper_amdS3Save(); + if (status) { + printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); + } +} + +BOOT_STATE_INIT_ENTRIES(agesa_bscb) = { + BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, + agesawrapper_post_device, NULL), +}; diff --git a/src/mainboard/amd/dinar/agesawrapper.h b/src/mainboard/amd/dinar/agesawrapper.h index c42b2b0..b8b8db8 100644 --- a/src/mainboard/amd/dinar/agesawrapper.h +++ b/src/mainboard/amd/dinar/agesawrapper.h @@ -95,4 +95,5 @@ UINT32 agesawrapper_amdinitmmio (void); void *agesawrapper_getlateinitptr (int pick); UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +static inline UINT32 agesawrapper_amdS3Save(void) { return 0; } #endif diff --git a/src/mainboard/amd/dinar/get_bus_conf.c b/src/mainboard/amd/dinar/get_bus_conf.c index a59bc43..a4d627b 100644 --- a/src/mainboard/amd/dinar/get_bus_conf.c +++ b/src/mainboard/amd/dinar/get_bus_conf.c @@ -66,8 +66,6 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { - u32 status; - device_t dev; int i, j; @@ -77,26 +75,6 @@ void get_bus_conf(void) get_bus_conf_done = 1; printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n"); - /* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "main". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ - status = agesawrapper_amdinitlate(); - if(status) { - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n"); sbdn_sb700 = 0; diff --git a/src/mainboard/amd/inagua/agesawrapper.h b/src/mainboard/amd/inagua/agesawrapper.h index 50b6a30..6e15a25 100644 --- a/src/mainboard/amd/inagua/agesawrapper.h +++ b/src/mainboard/amd/inagua/agesawrapper.h @@ -53,4 +53,5 @@ UINT32 agesawrapper_amdinitmmio (void); UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); void *agesawrapper_getlateinitptr (int pick); +static inline UINT32 agesawrapper_amdS3Save(void) { return 0; } #endif diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c index be281055..8ab41d1 100644 --- a/src/mainboard/amd/inagua/get_bus_conf.c +++ b/src/mainboard/amd/inagua/get_bus_conf.c @@ -55,7 +55,6 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - u32 status; device_t dev; int i, j; @@ -65,26 +64,6 @@ void get_bus_conf(void) get_bus_conf_done = 1; - /* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "main". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ - status = agesawrapper_amdinitlate(); - if(status) { - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c index df6ebb7..3addc97 100644 --- a/src/mainboard/amd/olivehill/get_bus_conf.c +++ b/src/mainboard/amd/olivehill/get_bus_conf.c @@ -50,13 +50,9 @@ u32 sbdn_yangtze; static u32 get_bus_conf_done = 0; -#if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; -#endif void get_bus_conf(void) { u32 apicid_base; - u32 status; u32 value; device_t dev; @@ -67,37 +63,6 @@ void get_bus_conf(void) get_bus_conf_done = 1; - /* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "hardwaremain". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type != 3) { - status = agesawrapper_amdinitlate(); - if(status) { - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - status = agesawrapper_amdS3Save(); - if (status) { - printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); - } - } -#else - status = agesawrapper_amdinitlate(); - if (status) - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); -#endif dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ pci_write_config32(dev, 0xF8, 0); pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ diff --git a/src/mainboard/amd/parmer/get_bus_conf.c b/src/mainboard/amd/parmer/get_bus_conf.c index bf76fe2..ce5276f 100644 --- a/src/mainboard/amd/parmer/get_bus_conf.c +++ b/src/mainboard/amd/parmer/get_bus_conf.c @@ -50,13 +50,9 @@ u32 sbdn_hudson; static u32 get_bus_conf_done = 0; -#if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; -#endif void get_bus_conf(void) { u32 apicid_base; - u32 status; device_t dev; int i, j; @@ -66,37 +62,6 @@ void get_bus_conf(void) get_bus_conf_done = 1; - /* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "main". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type != 3) { - status = agesawrapper_amdinitlate(); - if(status) { - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - status = agesawrapper_amdS3Save(); - if (status) { - printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); - } - } -#else - status = agesawrapper_amdinitlate(); - if (status) - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); -#endif sbdn_hudson = 0; diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index ac65a1d..15b1989 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -53,14 +53,9 @@ u32 sbdn_sb800; static u32 get_bus_conf_done = 0; -#if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; -#endif - void get_bus_conf(void) { u32 apicid_base; - u32 status; device_t dev; int i, j; @@ -70,35 +65,6 @@ void get_bus_conf(void) get_bus_conf_done = 1; -/* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "main". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type != 3) { - status = agesawrapper_amdinitlate(); - if(status) - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - status = agesawrapper_amdS3Save(); - if(status) - printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); - } -#else - status = agesawrapper_amdinitlate(); - if(status) - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); -#endif sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); diff --git a/src/mainboard/amd/south_station/agesawrapper.h b/src/mainboard/amd/south_station/agesawrapper.h index 48ed2f1..47332c5 100644 --- a/src/mainboard/amd/south_station/agesawrapper.h +++ b/src/mainboard/amd/south_station/agesawrapper.h @@ -53,4 +53,5 @@ UINT32 agesawrapper_amdinitmmio (void); UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); void *agesawrapper_getlateinitptr (int pick); +static inline UINT32 agesawrapper_amdS3Save(void) { return 0; } #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/mainboard/amd/south_station/get_bus_conf.c b/src/mainboard/amd/south_station/get_bus_conf.c index df8ce6e..6a3d232 100644 --- a/src/mainboard/amd/south_station/get_bus_conf.c +++ b/src/mainboard/amd/south_station/get_bus_conf.c @@ -55,7 +55,6 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - u32 status; device_t dev; int i, j; @@ -65,26 +64,6 @@ void get_bus_conf(void) get_bus_conf_done = 1; -/* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "main". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ - status = agesawrapper_amdinitlate(); - if(status) { - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c index bf76fe2..ce5276f 100644 --- a/src/mainboard/amd/thatcher/get_bus_conf.c +++ b/src/mainboard/amd/thatcher/get_bus_conf.c @@ -50,13 +50,9 @@ u32 sbdn_hudson; static u32 get_bus_conf_done = 0; -#if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; -#endif void get_bus_conf(void) { u32 apicid_base; - u32 status; device_t dev; int i, j; @@ -66,37 +62,6 @@ void get_bus_conf(void) get_bus_conf_done = 1; - /* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "main". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type != 3) { - status = agesawrapper_amdinitlate(); - if(status) { - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - status = agesawrapper_amdS3Save(); - if (status) { - printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); - } - } -#else - status = agesawrapper_amdinitlate(); - if (status) - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); -#endif sbdn_hudson = 0; diff --git a/src/mainboard/amd/torpedo/agesawrapper.h b/src/mainboard/amd/torpedo/agesawrapper.h index 9883bd1..5947b6b 100644 --- a/src/mainboard/amd/torpedo/agesawrapper.h +++ b/src/mainboard/amd/torpedo/agesawrapper.h @@ -95,4 +95,5 @@ UINT32 agesawrapper_amdinitmmio (void); UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); void *agesawrapper_getlateinitptr (int pick); +static inline UINT32 agesawrapper_amdS3Save(void) { return 0; } #endif diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c index 2b4e9fa..5404941 100644 --- a/src/mainboard/amd/torpedo/get_bus_conf.c +++ b/src/mainboard/amd/torpedo/get_bus_conf.c @@ -59,8 +59,6 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { - u32 status; - device_t dev; int i, j; @@ -70,27 +68,6 @@ void get_bus_conf(void) get_bus_conf_done = 1; printk(BIOS_DEBUG, "Mainboard - %s - %s - Start.\n", __FILE__, __func__); -/* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "main". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ - printk(BIOS_DEBUG, "agesawrapper_amdinitlate "); - status = agesawrapper_amdinitlate(); - if (status) - printk(BIOS_DEBUG, "error level: %x \n", status); - else - printk(BIOS_DEBUG, "passed.\n"); sbdn_sb900 = 0; diff --git a/src/mainboard/amd/union_station/agesawrapper.h b/src/mainboard/amd/union_station/agesawrapper.h index 48ed2f1..47332c5 100644 --- a/src/mainboard/amd/union_station/agesawrapper.h +++ b/src/mainboard/amd/union_station/agesawrapper.h @@ -53,4 +53,5 @@ UINT32 agesawrapper_amdinitmmio (void); UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); void *agesawrapper_getlateinitptr (int pick); +static inline UINT32 agesawrapper_amdS3Save(void) { return 0; } #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/mainboard/amd/union_station/get_bus_conf.c b/src/mainboard/amd/union_station/get_bus_conf.c index df8ce6e..6a3d232 100644 --- a/src/mainboard/amd/union_station/get_bus_conf.c +++ b/src/mainboard/amd/union_station/get_bus_conf.c @@ -55,7 +55,6 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - u32 status; device_t dev; int i, j; @@ -65,26 +64,6 @@ void get_bus_conf(void) get_bus_conf_done = 1; -/* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "main". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ - status = agesawrapper_amdinitlate(); - if(status) { - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); diff --git a/src/mainboard/asrock/e350m1/agesawrapper.h b/src/mainboard/asrock/e350m1/agesawrapper.h index 10158f6..b503559 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.h +++ b/src/mainboard/asrock/e350m1/agesawrapper.h @@ -84,4 +84,5 @@ UINT32 agesawrapper_amdinitcpuio (void); UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); void *agesawrapper_getlateinitptr (int pick); +static inline UINT32 agesawrapper_amdS3Save(void) { return 0; } #endif diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c index df8ce6e..6a3d232 100644 --- a/src/mainboard/asrock/e350m1/get_bus_conf.c +++ b/src/mainboard/asrock/e350m1/get_bus_conf.c @@ -55,7 +55,6 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - u32 status; device_t dev; int i, j; @@ -65,26 +64,6 @@ void get_bus_conf(void) get_bus_conf_done = 1; -/* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "main". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ - status = agesawrapper_amdinitlate(); - if(status) { - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); diff --git a/src/mainboard/asrock/imb-a180/get_bus_conf.c b/src/mainboard/asrock/imb-a180/get_bus_conf.c index a380872..226d57d 100644 --- a/src/mainboard/asrock/imb-a180/get_bus_conf.c +++ b/src/mainboard/asrock/imb-a180/get_bus_conf.c @@ -47,13 +47,9 @@ u32 sbdn_yangtze; static u32 get_bus_conf_done = 0; -#if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; -#endif void get_bus_conf(void) { u32 apicid_base; - u32 status; u32 value; device_t dev; @@ -64,37 +60,6 @@ void get_bus_conf(void) get_bus_conf_done = 1; - /* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "hardwaremain". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type != 3) { - status = agesawrapper_amdinitlate(); - if(status) { - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - status = agesawrapper_amdS3Save(); - if (status) { - printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); - } - } -#else - status = agesawrapper_amdinitlate(); - if (status) - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); -#endif dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ pci_write_config32(dev, 0xF8, 0); pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ diff --git a/src/mainboard/asus/f2a85-m/get_bus_conf.c b/src/mainboard/asus/f2a85-m/get_bus_conf.c index b915d76..5d5922b 100644 --- a/src/mainboard/asus/f2a85-m/get_bus_conf.c +++ b/src/mainboard/asus/f2a85-m/get_bus_conf.c @@ -48,13 +48,9 @@ u32 sbdn_hudson; static u32 get_bus_conf_done = 0; -#if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; -#endif void get_bus_conf(void) { u32 apicid_base; - u32 status; device_t dev; int i, j; @@ -64,37 +60,6 @@ void get_bus_conf(void) get_bus_conf_done = 1; - /* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "main". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type != 3) { - status = agesawrapper_amdinitlate(); - if(status) { - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - status = agesawrapper_amdS3Save(); - if (status) { - printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); - } - } -#else - status = agesawrapper_amdinitlate(); - if (status) - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); -#endif sbdn_hudson = 0; diff --git a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c b/src/mainboard/gizmosphere/gizmo/get_bus_conf.c index 89118aa..3b43d9d 100755 --- a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c +++ b/src/mainboard/gizmosphere/gizmo/get_bus_conf.c @@ -52,14 +52,9 @@ u32 sbdn_sb800; static u32 get_bus_conf_done = 0; -#if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; -#endif - void get_bus_conf(void) { u32 apicid_base; - u32 status; device_t dev; int i, j; @@ -69,35 +64,6 @@ void get_bus_conf(void) get_bus_conf_done = 1; -/* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "hardwaremain". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type != 3) { - status = agesawrapper_amdinitlate(); - if(status) - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - status = agesawrapper_amdS3Save(); - if(status) - printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); - } -#else - status = agesawrapper_amdinitlate(); - if(status) - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); -#endif sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c index 79a5380..34afc17 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c @@ -49,13 +49,9 @@ u32 sbdn_hudson; static u32 get_bus_conf_done = 0; -#if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; -#endif void get_bus_conf(void) { u32 apicid_base; - u32 status; device_t dev; int i, j; @@ -65,37 +61,6 @@ void get_bus_conf(void) get_bus_conf_done = 1; - /* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "main". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type != 3) { - status = agesawrapper_amdinitlate(); - if(status) { - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - status = agesawrapper_amdS3Save(); - if (status) { - printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); - } - } -#else - status = agesawrapper_amdinitlate(); - if (status) - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); -#endif sbdn_hudson = 0; diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c index 688f9dd..69a86ab 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c +++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c @@ -54,14 +54,9 @@ u32 sbdn_sb800; static u32 get_bus_conf_done = 0; -#if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; -#endif /* CONFIG_HAVE_ACPI_RESUME */ - void get_bus_conf(void) { u32 apicid_base; - u32 status; device_t dev; int i, j; @@ -72,39 +67,7 @@ void get_bus_conf(void) get_bus_conf_done = 1; - /* - * This is the call to AmdInitLate. It is really in the wrong place, - * conceptually, but functionally within the coreboot model, this is the - * best place to make the call. The logically correct place to call - * AmdInitLate is after PCI scan is done, after the decision about S3 - * resume is made, and before the system tables are written into RAM. The - * routine that is - * responsible for writing the tables is "write_tables", called near the - * end of "main". There is no platform specific entry point between the S3 - * resume decision point and the call to "write_tables", and the next - * platform specific entry points are the calls to the ACPI table write - * functions. The first of ose would seem to be the right place, but other - * table write - * functions, e.g. the PIRQ table write function, are called before the - * ACPI tables are written. This routine is called at the beginning of each - * of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type != 3) { - status = agesawrapper_amdinitlate(); - if(status) - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - status = agesawrapper_amdS3Save(); - if(status) - printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); - } -#else - status = agesawrapper_amdinitlate(); - if(status) - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); -#endif /* CONFIG_HAVE_ACPI_RESUME */ sbdn_sb800 = 0; diff --git a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c index 258d895..1e7fca4 100644 --- a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c +++ b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c @@ -51,14 +51,9 @@ u32 sbdn_sb800; static u32 get_bus_conf_done = 0; -#if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; -#endif - void get_bus_conf(void) { u32 apicid_base; - u32 status; device_t dev; int i, j; @@ -68,35 +63,6 @@ void get_bus_conf(void) get_bus_conf_done = 1; -/* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "main". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type != 3) { - status = agesawrapper_amdinitlate(); - if(status) - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - status = agesawrapper_amdS3Save(); - if(status) - printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); - } -#else - status = agesawrapper_amdinitlate(); - if(status) - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); -#endif sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); diff --git a/src/mainboard/lippert/toucan-af/get_bus_conf.c b/src/mainboard/lippert/toucan-af/get_bus_conf.c index 258d895..1e7fca4 100644 --- a/src/mainboard/lippert/toucan-af/get_bus_conf.c +++ b/src/mainboard/lippert/toucan-af/get_bus_conf.c @@ -51,14 +51,9 @@ u32 sbdn_sb800; static u32 get_bus_conf_done = 0; -#if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; -#endif - void get_bus_conf(void) { u32 apicid_base; - u32 status; device_t dev; int i, j; @@ -68,35 +63,6 @@ void get_bus_conf(void) get_bus_conf_done = 1; -/* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "main". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type != 3) { - status = agesawrapper_amdinitlate(); - if(status) - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - status = agesawrapper_amdS3Save(); - if(status) - printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); - } -#else - status = agesawrapper_amdinitlate(); - if(status) - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); -#endif sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.h b/src/mainboard/supermicro/h8qgi/agesawrapper.h index 4f5a693..51e438d 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.h +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.h @@ -79,4 +79,5 @@ UINT32 agesawrapper_amdinitmmio (void); void *agesawrapper_getlateinitptr (int pick); UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +static inline UINT32 agesawrapper_amdS3Save(void) { return 0; } #endif diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c index 25dc2a2..345c75d 100644 --- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c @@ -48,8 +48,6 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { - u32 status; - device_t dev; int i, j; @@ -58,26 +56,6 @@ void get_bus_conf(void) get_bus_conf_done = 1; - /* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "main". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ - status = agesawrapper_amdinitlate(); - if(status) { - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - sbdn_sp5100 = 0; for (i = 0; i < ARRAY_SIZE(bus_sp5100); i++) { diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.h b/src/mainboard/supermicro/h8scm/agesawrapper.h index 4f5a693..51e438d 100644 --- a/src/mainboard/supermicro/h8scm/agesawrapper.h +++ b/src/mainboard/supermicro/h8scm/agesawrapper.h @@ -79,4 +79,5 @@ UINT32 agesawrapper_amdinitmmio (void); void *agesawrapper_getlateinitptr (int pick); UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +static inline UINT32 agesawrapper_amdS3Save(void) { return 0; } #endif diff --git a/src/mainboard/supermicro/h8scm/get_bus_conf.c b/src/mainboard/supermicro/h8scm/get_bus_conf.c index 4b2cb32..4b51f2a 100644 --- a/src/mainboard/supermicro/h8scm/get_bus_conf.c +++ b/src/mainboard/supermicro/h8scm/get_bus_conf.c @@ -48,8 +48,6 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { - u32 status; - device_t dev; int i, j; @@ -58,26 +56,6 @@ void get_bus_conf(void) get_bus_conf_done = 1; - /* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "main". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ - status = agesawrapper_amdinitlate(); - if(status) { - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - sbdn_sp5100 = 0; for (i = 0; i < 0; i++) { diff --git a/src/mainboard/tyan/s8226/agesawrapper.h b/src/mainboard/tyan/s8226/agesawrapper.h index 4f5a693..51e438d 100644 --- a/src/mainboard/tyan/s8226/agesawrapper.h +++ b/src/mainboard/tyan/s8226/agesawrapper.h @@ -79,4 +79,5 @@ UINT32 agesawrapper_amdinitmmio (void); void *agesawrapper_getlateinitptr (int pick); UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +static inline UINT32 agesawrapper_amdS3Save(void) { return 0; } #endif diff --git a/src/mainboard/tyan/s8226/get_bus_conf.c b/src/mainboard/tyan/s8226/get_bus_conf.c index d45e1ad..5c416c5 100644 --- a/src/mainboard/tyan/s8226/get_bus_conf.c +++ b/src/mainboard/tyan/s8226/get_bus_conf.c @@ -47,8 +47,6 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { - u32 status; - device_t dev; int i, j; @@ -57,26 +55,6 @@ void get_bus_conf(void) get_bus_conf_done = 1; - /* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "main". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ - status = agesawrapper_amdinitlate(); - if(status) { - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - sbdn_sp5100 = 0; for (i = 0; i < 0; i++) {

1 0

Patch set updated for coreboot: 0b9b9b8 AGESA: Call get_bus_conf() just once
by Kyösti Mälkki 27 Jun '14

27 Jun '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6133 -gerrit commit 0b9b9b8a0d8d8f0360f408a8589f7757e19ace10 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 19 22:19:20 2014 +0300 AGESA: Call get_bus_conf() just once Instead of calling get_bus_conf() three times from write_tables() and executing it once, just make one call before entering write_tables(). Change-Id: I818e37128cb0fb5eaded3c1e00b6b146c1267647 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/amd_late_init.c | 3 +++ src/mainboard/amd/dinar/acpi_tables.c | 2 -- src/mainboard/amd/dinar/get_bus_conf.c | 10 ---------- src/mainboard/amd/dinar/irq_tables.c | 4 ---- src/mainboard/amd/dinar/mptable.c | 1 - src/mainboard/amd/inagua/acpi_tables.c | 2 -- src/mainboard/amd/inagua/get_bus_conf.c | 7 ------- src/mainboard/amd/inagua/irq_tables.c | 4 ---- src/mainboard/amd/inagua/mptable.c | 2 -- src/mainboard/amd/olivehill/acpi_tables.c | 2 -- src/mainboard/amd/olivehill/get_bus_conf.c | 5 ----- src/mainboard/amd/olivehill/irq_tables.c | 2 -- src/mainboard/amd/olivehill/mptable.c | 2 -- src/mainboard/amd/parmer/acpi_tables.c | 2 -- src/mainboard/amd/parmer/get_bus_conf.c | 5 ----- src/mainboard/amd/parmer/irq_tables.c | 2 -- src/mainboard/amd/parmer/mptable.c | 2 -- src/mainboard/amd/persimmon/acpi_tables.c | 2 -- src/mainboard/amd/persimmon/get_bus_conf.c | 6 ------ src/mainboard/amd/persimmon/irq_tables.c | 4 ---- src/mainboard/amd/persimmon/mptable.c | 3 --- src/mainboard/amd/south_station/acpi_tables.c | 2 -- src/mainboard/amd/south_station/get_bus_conf.c | 7 ------- src/mainboard/amd/south_station/irq_tables.c | 4 ---- src/mainboard/amd/south_station/mptable.c | 2 -- src/mainboard/amd/thatcher/acpi_tables.c | 2 -- src/mainboard/amd/thatcher/get_bus_conf.c | 7 ------- src/mainboard/amd/thatcher/irq_tables.c | 2 -- src/mainboard/amd/thatcher/mptable.c | 2 -- src/mainboard/amd/torpedo/acpi_tables.c | 2 -- src/mainboard/amd/torpedo/get_bus_conf.c | 8 -------- src/mainboard/amd/torpedo/irq_tables.c | 4 ---- src/mainboard/amd/torpedo/mptable.c | 2 -- src/mainboard/amd/union_station/acpi_tables.c | 2 -- src/mainboard/amd/union_station/get_bus_conf.c | 7 ------- src/mainboard/amd/union_station/irq_tables.c | 4 ---- src/mainboard/amd/union_station/mptable.c | 2 -- src/mainboard/asrock/e350m1/acpi_tables.c | 2 -- src/mainboard/asrock/e350m1/get_bus_conf.c | 7 ------- src/mainboard/asrock/e350m1/irq_tables.c | 4 ---- src/mainboard/asrock/e350m1/mptable.c | 2 -- src/mainboard/asrock/imb-a180/acpi_tables.c | 2 -- src/mainboard/asrock/imb-a180/get_bus_conf.c | 7 ------- src/mainboard/asrock/imb-a180/irq_tables.c | 2 -- src/mainboard/asrock/imb-a180/mptable.c | 2 -- src/mainboard/asus/f2a85-m/acpi_tables.c | 2 -- src/mainboard/asus/f2a85-m/get_bus_conf.c | 8 -------- src/mainboard/asus/f2a85-m/irq_tables.c | 2 -- src/mainboard/asus/f2a85-m/mptable.c | 2 -- src/mainboard/gizmosphere/gizmo/acpi_tables.c | 2 -- src/mainboard/gizmosphere/gizmo/get_bus_conf.c | 6 ------ src/mainboard/gizmosphere/gizmo/irq_tables.c | 4 ---- src/mainboard/gizmosphere/gizmo/mptable.c | 2 -- src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c | 2 -- src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c | 7 ------- src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c | 2 -- src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 2 -- src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c | 2 -- src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c | 9 --------- src/mainboard/jetway/nf81-t56n-lf/irq_tables.c | 6 ------ src/mainboard/jetway/nf81-t56n-lf/mptable.c | 3 --- src/mainboard/lippert/frontrunner-af/acpi_tables.c | 2 -- src/mainboard/lippert/frontrunner-af/get_bus_conf.c | 6 ------ src/mainboard/lippert/frontrunner-af/irq_tables.c | 4 ---- src/mainboard/lippert/frontrunner-af/mptable.c | 2 -- src/mainboard/lippert/toucan-af/acpi_tables.c | 2 -- src/mainboard/lippert/toucan-af/get_bus_conf.c | 7 ------- src/mainboard/lippert/toucan-af/irq_tables.c | 4 ---- src/mainboard/lippert/toucan-af/mptable.c | 2 -- src/mainboard/supermicro/h8qgi/acpi_tables.c | 2 -- src/mainboard/supermicro/h8qgi/get_bus_conf.c | 8 -------- src/mainboard/supermicro/h8qgi/irq_tables.c | 4 ---- src/mainboard/supermicro/h8qgi/mptable.c | 1 - src/mainboard/supermicro/h8scm/acpi_tables.c | 2 -- src/mainboard/supermicro/h8scm/get_bus_conf.c | 8 -------- src/mainboard/supermicro/h8scm/irq_tables.c | 2 -- src/mainboard/supermicro/h8scm/mptable.c | 1 - src/mainboard/tyan/s8226/acpi_tables.c | 2 -- src/mainboard/tyan/s8226/get_bus_conf.c | 6 ------ src/mainboard/tyan/s8226/irq_tables.c | 4 ---- src/mainboard/tyan/s8226/mptable.c | 1 - 81 files changed, 3 insertions(+), 287 deletions(-) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index e08b159..8bce364 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -36,6 +36,9 @@ static void agesawrapper_post_device(void *unused) printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); } + /* Preparation for write_tables(). */ + get_bus_conf(); + if (!acpi_s3_resume_allowed()) return; diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index 44b6306..5ec2d74 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -173,8 +173,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *alib; acpi_hest_t *hest; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/amd/dinar/get_bus_conf.c b/src/mainboard/amd/dinar/get_bus_conf.c index a4d627b..e93ca84 100644 --- a/src/mainboard/amd/dinar/get_bus_conf.c +++ b/src/mainboard/amd/dinar/get_bus_conf.c @@ -59,21 +59,11 @@ u32 bus_type[256]; u32 sbdn_sb700; u32 sbdn_rd890; -static u32 get_bus_conf_done = 0; - - - - void get_bus_conf(void) { device_t dev; int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; - printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n"); sbdn_sb700 = 0; diff --git a/src/mainboard/amd/dinar/irq_tables.c b/src/mainboard/amd/dinar/irq_tables.c index 5ee4de0..0000111 100644 --- a/src/mainboard/amd/dinar/irq_tables.c +++ b/src/mainboard/amd/dinar/irq_tables.c @@ -58,10 +58,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - - /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c index 5f9e83b..65304e1 100644 --- a/src/mainboard/amd/dinar/mptable.c +++ b/src/mainboard/amd/dinar/mptable.c @@ -48,7 +48,6 @@ static void *smp_write_config_table(void *v) mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); - get_bus_conf(); mptable_write_buses(mc, NULL, &bus_isa); /* diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 227a49b..588345e 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -133,8 +133,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *alib; acpi_hest_t *hest; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c index 8ab41d1..ac72b48 100644 --- a/src/mainboard/amd/inagua/get_bus_conf.c +++ b/src/mainboard/amd/inagua/get_bus_conf.c @@ -49,9 +49,6 @@ u32 pci1234x[] = { u32 bus_type[256]; u32 sbdn_sb800; -static u32 get_bus_conf_done = 0; - - void get_bus_conf(void) { u32 apicid_base; @@ -59,10 +56,6 @@ void get_bus_conf(void) device_t dev; int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; sbdn_sb800 = 0; diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c index 0fc6349..1318d4d 100644 --- a/src/mainboard/amd/inagua/irq_tables.c +++ b/src/mainboard/amd/inagua/irq_tables.c @@ -59,10 +59,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - - /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index 7352205..d2f8506 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -60,8 +60,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - get_bus_conf(); - mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ diff --git a/src/mainboard/amd/olivehill/acpi_tables.c b/src/mainboard/amd/olivehill/acpi_tables.c index ac5a890..07fad8e 100644 --- a/src/mainboard/amd/olivehill/acpi_tables.c +++ b/src/mainboard/amd/olivehill/acpi_tables.c @@ -138,8 +138,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ivrs; acpi_hest_t *hest; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c index 3addc97..f1643a4 100644 --- a/src/mainboard/amd/olivehill/get_bus_conf.c +++ b/src/mainboard/amd/olivehill/get_bus_conf.c @@ -48,7 +48,6 @@ u32 pci1234x[] = { u32 bus_type[256]; u32 sbdn_yangtze; -static u32 get_bus_conf_done = 0; void get_bus_conf(void) { @@ -58,10 +57,6 @@ void get_bus_conf(void) device_t dev; int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ pci_write_config32(dev, 0xF8, 0); diff --git a/src/mainboard/amd/olivehill/irq_tables.c b/src/mainboard/amd/olivehill/irq_tables.c index c14fd49..bea6eb2 100644 --- a/src/mainboard/amd/olivehill/irq_tables.c +++ b/src/mainboard/amd/olivehill/irq_tables.c @@ -57,8 +57,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index adf3b6c..3ccb910 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -84,8 +84,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - get_bus_conf(); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); diff --git a/src/mainboard/amd/parmer/acpi_tables.c b/src/mainboard/amd/parmer/acpi_tables.c index eb6b419..503ba48 100644 --- a/src/mainboard/amd/parmer/acpi_tables.c +++ b/src/mainboard/amd/parmer/acpi_tables.c @@ -134,8 +134,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ivrs; acpi_hest_t *hest; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/amd/parmer/get_bus_conf.c b/src/mainboard/amd/parmer/get_bus_conf.c index ce5276f..4c4777f 100644 --- a/src/mainboard/amd/parmer/get_bus_conf.c +++ b/src/mainboard/amd/parmer/get_bus_conf.c @@ -48,7 +48,6 @@ u32 pci1234x[] = { u32 bus_type[256]; u32 sbdn_hudson; -static u32 get_bus_conf_done = 0; void get_bus_conf(void) { @@ -57,10 +56,6 @@ void get_bus_conf(void) device_t dev; int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; sbdn_hudson = 0; diff --git a/src/mainboard/amd/parmer/irq_tables.c b/src/mainboard/amd/parmer/irq_tables.c index 6f907e2..20fbb5d 100644 --- a/src/mainboard/amd/parmer/irq_tables.c +++ b/src/mainboard/amd/parmer/irq_tables.c @@ -57,8 +57,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index 3484289..0980063 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -84,8 +84,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - get_bus_conf(); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 227a49b..588345e 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -133,8 +133,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *alib; acpi_hest_t *hest; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index 15b1989..c8369e1 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -51,8 +51,6 @@ u32 pci1234x[] = { u32 bus_type[256]; u32 sbdn_sb800; -static u32 get_bus_conf_done = 0; - void get_bus_conf(void) { u32 apicid_base; @@ -60,10 +58,6 @@ void get_bus_conf(void) device_t dev; int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; sbdn_sb800 = 0; diff --git a/src/mainboard/amd/persimmon/irq_tables.c b/src/mainboard/amd/persimmon/irq_tables.c index b8c211a..dbbb2af 100644 --- a/src/mainboard/amd/persimmon/irq_tables.c +++ b/src/mainboard/amd/persimmon/irq_tables.c @@ -59,10 +59,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - - /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 8639617..cc5eac2 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -56,9 +56,6 @@ static void *smp_write_config_table(void *v) */ smp_write_processors(mc); - /* Get Bus Configuration */ - get_bus_conf(); - /* * Type 1: Bus Entries: * Bus ID, Bus Type diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index 227a49b..588345e 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -133,8 +133,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *alib; acpi_hest_t *hest; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/amd/south_station/get_bus_conf.c b/src/mainboard/amd/south_station/get_bus_conf.c index 6a3d232..7eedcba8 100644 --- a/src/mainboard/amd/south_station/get_bus_conf.c +++ b/src/mainboard/amd/south_station/get_bus_conf.c @@ -49,9 +49,6 @@ u32 pci1234x[] = { u32 bus_type[256]; u32 sbdn_sb800; -static u32 get_bus_conf_done = 0; - - void get_bus_conf(void) { u32 apicid_base; @@ -59,10 +56,6 @@ void get_bus_conf(void) device_t dev; int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; sbdn_sb800 = 0; diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c index b8c211a..dbbb2af 100644 --- a/src/mainboard/amd/south_station/irq_tables.c +++ b/src/mainboard/amd/south_station/irq_tables.c @@ -59,10 +59,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - - /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index e9175d8..f266b4f 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -56,8 +56,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - get_bus_conf(); - mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ diff --git a/src/mainboard/amd/thatcher/acpi_tables.c b/src/mainboard/amd/thatcher/acpi_tables.c index eb6b419..503ba48 100644 --- a/src/mainboard/amd/thatcher/acpi_tables.c +++ b/src/mainboard/amd/thatcher/acpi_tables.c @@ -134,8 +134,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ivrs; acpi_hest_t *hest; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c index ce5276f..d4a5654 100644 --- a/src/mainboard/amd/thatcher/get_bus_conf.c +++ b/src/mainboard/amd/thatcher/get_bus_conf.c @@ -48,7 +48,6 @@ u32 pci1234x[] = { u32 bus_type[256]; u32 sbdn_hudson; -static u32 get_bus_conf_done = 0; void get_bus_conf(void) { @@ -57,12 +56,6 @@ void get_bus_conf(void) device_t dev; int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; - - sbdn_hudson = 0; memset(bus_hudson, 0, sizeof(bus_hudson)); diff --git a/src/mainboard/amd/thatcher/irq_tables.c b/src/mainboard/amd/thatcher/irq_tables.c index 6f907e2..20fbb5d 100644 --- a/src/mainboard/amd/thatcher/irq_tables.c +++ b/src/mainboard/amd/thatcher/irq_tables.c @@ -57,8 +57,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index 3213395..3269089 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -84,8 +84,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - get_bus_conf(); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); diff --git a/src/mainboard/amd/torpedo/acpi_tables.c b/src/mainboard/amd/torpedo/acpi_tables.c index c359563..b916bce 100644 --- a/src/mainboard/amd/torpedo/acpi_tables.c +++ b/src/mainboard/amd/torpedo/acpi_tables.c @@ -121,8 +121,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt; acpi_hest_t *hest; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c index 5404941..36613f7 100644 --- a/src/mainboard/amd/torpedo/get_bus_conf.c +++ b/src/mainboard/amd/torpedo/get_bus_conf.c @@ -54,19 +54,11 @@ u32 bus_type[256]; u32 sbdn_sb900; - -static u32 get_bus_conf_done = 0; - void get_bus_conf(void) { device_t dev; int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; - printk(BIOS_DEBUG, "Mainboard - %s - %s - Start.\n", __FILE__, __func__); sbdn_sb900 = 0; diff --git a/src/mainboard/amd/torpedo/irq_tables.c b/src/mainboard/amd/torpedo/irq_tables.c index 3027802..53cf6fa 100644 --- a/src/mainboard/amd/torpedo/irq_tables.c +++ b/src/mainboard/amd/torpedo/irq_tables.c @@ -60,10 +60,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - - /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index 24e48d1..ae00cf7 100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -104,8 +104,6 @@ static void *smp_write_config_table(void *v) cpu_flag, cpu_features, cpu_feature_flags ); - get_bus_conf(); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index 227a49b..588345e 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -133,8 +133,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *alib; acpi_hest_t *hest; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/amd/union_station/get_bus_conf.c b/src/mainboard/amd/union_station/get_bus_conf.c index 6a3d232..7eedcba8 100644 --- a/src/mainboard/amd/union_station/get_bus_conf.c +++ b/src/mainboard/amd/union_station/get_bus_conf.c @@ -49,9 +49,6 @@ u32 pci1234x[] = { u32 bus_type[256]; u32 sbdn_sb800; -static u32 get_bus_conf_done = 0; - - void get_bus_conf(void) { u32 apicid_base; @@ -59,10 +56,6 @@ void get_bus_conf(void) device_t dev; int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; sbdn_sb800 = 0; diff --git a/src/mainboard/amd/union_station/irq_tables.c b/src/mainboard/amd/union_station/irq_tables.c index b8c211a..dbbb2af 100644 --- a/src/mainboard/amd/union_station/irq_tables.c +++ b/src/mainboard/amd/union_station/irq_tables.c @@ -59,10 +59,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - - /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index e9175d8..f266b4f 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -56,8 +56,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - get_bus_conf(); - mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index 56cfc46..65cb796 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -132,8 +132,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *alib; acpi_hest_t *hest; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c index 6a3d232..7eedcba8 100644 --- a/src/mainboard/asrock/e350m1/get_bus_conf.c +++ b/src/mainboard/asrock/e350m1/get_bus_conf.c @@ -49,9 +49,6 @@ u32 pci1234x[] = { u32 bus_type[256]; u32 sbdn_sb800; -static u32 get_bus_conf_done = 0; - - void get_bus_conf(void) { u32 apicid_base; @@ -59,10 +56,6 @@ void get_bus_conf(void) device_t dev; int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; sbdn_sb800 = 0; diff --git a/src/mainboard/asrock/e350m1/irq_tables.c b/src/mainboard/asrock/e350m1/irq_tables.c index b8c211a..dbbb2af 100644 --- a/src/mainboard/asrock/e350m1/irq_tables.c +++ b/src/mainboard/asrock/e350m1/irq_tables.c @@ -59,10 +59,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - - /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index 6444be5..3402da1 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -57,8 +57,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - get_bus_conf(); - mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ diff --git a/src/mainboard/asrock/imb-a180/acpi_tables.c b/src/mainboard/asrock/imb-a180/acpi_tables.c index 1175792..41354fb 100644 --- a/src/mainboard/asrock/imb-a180/acpi_tables.c +++ b/src/mainboard/asrock/imb-a180/acpi_tables.c @@ -138,8 +138,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ivrs; acpi_hest_t *hest; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/asrock/imb-a180/get_bus_conf.c b/src/mainboard/asrock/imb-a180/get_bus_conf.c index 226d57d..eecffb5 100644 --- a/src/mainboard/asrock/imb-a180/get_bus_conf.c +++ b/src/mainboard/asrock/imb-a180/get_bus_conf.c @@ -45,8 +45,6 @@ u32 pci1234x[] = { u32 bus_type[256]; u32 sbdn_yangtze; -static u32 get_bus_conf_done = 0; - void get_bus_conf(void) { u32 apicid_base; @@ -55,11 +53,6 @@ void get_bus_conf(void) device_t dev; int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ pci_write_config32(dev, 0xF8, 0); pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ diff --git a/src/mainboard/asrock/imb-a180/irq_tables.c b/src/mainboard/asrock/imb-a180/irq_tables.c index 8454007..2b4422e 100644 --- a/src/mainboard/asrock/imb-a180/irq_tables.c +++ b/src/mainboard/asrock/imb-a180/irq_tables.c @@ -57,8 +57,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index 3e2b076..bfad50d 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -84,8 +84,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - get_bus_conf(); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); diff --git a/src/mainboard/asus/f2a85-m/acpi_tables.c b/src/mainboard/asus/f2a85-m/acpi_tables.c index 1f95b1d..428721e 100644 --- a/src/mainboard/asus/f2a85-m/acpi_tables.c +++ b/src/mainboard/asus/f2a85-m/acpi_tables.c @@ -131,8 +131,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ivrs; acpi_hest_t *hest; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/asus/f2a85-m/get_bus_conf.c b/src/mainboard/asus/f2a85-m/get_bus_conf.c index 5d5922b..08e5795 100644 --- a/src/mainboard/asus/f2a85-m/get_bus_conf.c +++ b/src/mainboard/asus/f2a85-m/get_bus_conf.c @@ -46,8 +46,6 @@ u32 pci1234x[] = { u32 bus_type[256]; u32 sbdn_hudson; -static u32 get_bus_conf_done = 0; - void get_bus_conf(void) { u32 apicid_base; @@ -55,12 +53,6 @@ void get_bus_conf(void) device_t dev; int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; - - sbdn_hudson = 0; memset(bus_hudson, 0, sizeof(bus_hudson)); diff --git a/src/mainboard/asus/f2a85-m/irq_tables.c b/src/mainboard/asus/f2a85-m/irq_tables.c index 3f70d16..40dd6e9 100644 --- a/src/mainboard/asus/f2a85-m/irq_tables.c +++ b/src/mainboard/asus/f2a85-m/irq_tables.c @@ -56,8 +56,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index 5056b08..25778ca 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -83,8 +83,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - get_bus_conf(); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); diff --git a/src/mainboard/gizmosphere/gizmo/acpi_tables.c b/src/mainboard/gizmosphere/gizmo/acpi_tables.c index 805837d..a9174c0 100755 --- a/src/mainboard/gizmosphere/gizmo/acpi_tables.c +++ b/src/mainboard/gizmosphere/gizmo/acpi_tables.c @@ -134,8 +134,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *alib; acpi_hest_t *hest; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c b/src/mainboard/gizmosphere/gizmo/get_bus_conf.c index 3b43d9d..ca20a0c 100755 --- a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c +++ b/src/mainboard/gizmosphere/gizmo/get_bus_conf.c @@ -50,7 +50,6 @@ u32 pci1234x[] = { u32 bus_type[256]; u32 sbdn_sb800; -static u32 get_bus_conf_done = 0; void get_bus_conf(void) { @@ -59,11 +58,6 @@ void get_bus_conf(void) device_t dev; int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); diff --git a/src/mainboard/gizmosphere/gizmo/irq_tables.c b/src/mainboard/gizmosphere/gizmo/irq_tables.c index dd62ed8..09fb4e2 100755 --- a/src/mainboard/gizmosphere/gizmo/irq_tables.c +++ b/src/mainboard/gizmosphere/gizmo/irq_tables.c @@ -60,10 +60,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - - /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c index 6dfd11d..c56060e 100755 --- a/src/mainboard/gizmosphere/gizmo/mptable.c +++ b/src/mainboard/gizmosphere/gizmo/mptable.c @@ -57,8 +57,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - get_bus_conf(); - mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c b/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c index 01281ea..dbe550c 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c @@ -131,8 +131,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ivrs; acpi_hest_t *hest; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c index 34afc17..78193eb 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c @@ -47,7 +47,6 @@ u32 pci1234x[] = { u32 bus_type[256]; u32 sbdn_hudson; -static u32 get_bus_conf_done = 0; void get_bus_conf(void) { @@ -56,12 +55,6 @@ void get_bus_conf(void) device_t dev; int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; - - sbdn_hudson = 0; memset(bus_hudson, 0, sizeof(bus_hudson)); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c b/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c index 076edc5..1d99b4c 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c @@ -56,8 +56,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c index 2d7646a..d90a453 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c @@ -84,8 +84,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - get_bus_conf(); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c index c246270..95f2a0e 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c @@ -133,8 +133,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *alib; acpi_hest_t *hest; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c index 69a86ab..43aa984 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c +++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c @@ -52,7 +52,6 @@ u32 pci1234x[] = { u32 bus_type[256]; u32 sbdn_sb800; -static u32 get_bus_conf_done = 0; void get_bus_conf(void) { @@ -61,14 +60,6 @@ void get_bus_conf(void) device_t dev; int i, j; - /* Be sure func is called exactly once */ - if (get_bus_conf_done == 1) - return; - - get_bus_conf_done = 1; - - - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); diff --git a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c index 259034b..36d104d 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c @@ -58,12 +58,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - /* Find all Bus num and APIC's that are share with - * mptable.c and acpi_tables.c - */ - get_bus_conf(); - - /* Align table on 16 byte boundary. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index a97810c..70d57a7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -58,9 +58,6 @@ static void *smp_write_config_table(void *v) */ smp_write_processors(mc); - /* Get Bus Configuration */ - get_bus_conf(); - /* * Type 1: Bus Entries: * Bus ID, Bus Type diff --git a/src/mainboard/lippert/frontrunner-af/acpi_tables.c b/src/mainboard/lippert/frontrunner-af/acpi_tables.c index 227a49b..588345e 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi_tables.c +++ b/src/mainboard/lippert/frontrunner-af/acpi_tables.c @@ -133,8 +133,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *alib; acpi_hest_t *hest; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c index 1e7fca4..bddcee1 100644 --- a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c +++ b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c @@ -49,7 +49,6 @@ u32 pci1234x[] = { u32 bus_type[256]; u32 sbdn_sb800; -static u32 get_bus_conf_done = 0; void get_bus_conf(void) { @@ -58,11 +57,6 @@ void get_bus_conf(void) device_t dev; int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); diff --git a/src/mainboard/lippert/frontrunner-af/irq_tables.c b/src/mainboard/lippert/frontrunner-af/irq_tables.c index b8c211a..dbbb2af 100644 --- a/src/mainboard/lippert/frontrunner-af/irq_tables.c +++ b/src/mainboard/lippert/frontrunner-af/irq_tables.c @@ -59,10 +59,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - - /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c index 6b8aaa6..498ae58 100644 --- a/src/mainboard/lippert/frontrunner-af/mptable.c +++ b/src/mainboard/lippert/frontrunner-af/mptable.c @@ -56,8 +56,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - get_bus_conf(); - mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ diff --git a/src/mainboard/lippert/toucan-af/acpi_tables.c b/src/mainboard/lippert/toucan-af/acpi_tables.c index 227a49b..588345e 100644 --- a/src/mainboard/lippert/toucan-af/acpi_tables.c +++ b/src/mainboard/lippert/toucan-af/acpi_tables.c @@ -133,8 +133,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *alib; acpi_hest_t *hest; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/lippert/toucan-af/get_bus_conf.c b/src/mainboard/lippert/toucan-af/get_bus_conf.c index 1e7fca4..f0de0e5 100644 --- a/src/mainboard/lippert/toucan-af/get_bus_conf.c +++ b/src/mainboard/lippert/toucan-af/get_bus_conf.c @@ -49,8 +49,6 @@ u32 pci1234x[] = { u32 bus_type[256]; u32 sbdn_sb800; -static u32 get_bus_conf_done = 0; - void get_bus_conf(void) { u32 apicid_base; @@ -58,11 +56,6 @@ void get_bus_conf(void) device_t dev; int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); diff --git a/src/mainboard/lippert/toucan-af/irq_tables.c b/src/mainboard/lippert/toucan-af/irq_tables.c index b8c211a..dbbb2af 100644 --- a/src/mainboard/lippert/toucan-af/irq_tables.c +++ b/src/mainboard/lippert/toucan-af/irq_tables.c @@ -59,10 +59,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - - /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c index 6b8aaa6..498ae58 100644 --- a/src/mainboard/lippert/toucan-af/mptable.c +++ b/src/mainboard/lippert/toucan-af/mptable.c @@ -56,8 +56,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - get_bus_conf(); - mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index 1e1b323..335c5ec 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -172,8 +172,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *alib; acpi_hest_t *hest; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c index 345c75d..7a69a7c 100644 --- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c @@ -43,19 +43,11 @@ u32 bus_type[256]; u32 sbdn_sr5650; u32 sbdn_sp5100; -static u32 get_bus_conf_done = 0; - - void get_bus_conf(void) { device_t dev; int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; - sbdn_sp5100 = 0; for (i = 0; i < ARRAY_SIZE(bus_sp5100); i++) { diff --git a/src/mainboard/supermicro/h8qgi/irq_tables.c b/src/mainboard/supermicro/h8qgi/irq_tables.c index 44c7753..3c2caa2 100644 --- a/src/mainboard/supermicro/h8qgi/irq_tables.c +++ b/src/mainboard/supermicro/h8qgi/irq_tables.c @@ -59,10 +59,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - - /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index 0365ae6..2206b58 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -48,7 +48,6 @@ static void *smp_write_config_table(void *v) mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); - get_bus_conf(); mptable_write_buses(mc, NULL, &bus_isa); /* diff --git a/src/mainboard/supermicro/h8scm/acpi_tables.c b/src/mainboard/supermicro/h8scm/acpi_tables.c index 975dcbe..d051cef 100644 --- a/src/mainboard/supermicro/h8scm/acpi_tables.c +++ b/src/mainboard/supermicro/h8scm/acpi_tables.c @@ -153,8 +153,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt2; acpi_header_t *alib; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/supermicro/h8scm/get_bus_conf.c b/src/mainboard/supermicro/h8scm/get_bus_conf.c index 4b51f2a..932e2de 100644 --- a/src/mainboard/supermicro/h8scm/get_bus_conf.c +++ b/src/mainboard/supermicro/h8scm/get_bus_conf.c @@ -43,19 +43,11 @@ u32 bus_type[256]; u32 sbdn_sr5650; u32 sbdn_sp5100; -static u32 get_bus_conf_done = 0; - - void get_bus_conf(void) { device_t dev; int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; - sbdn_sp5100 = 0; for (i = 0; i < 0; i++) { diff --git a/src/mainboard/supermicro/h8scm/irq_tables.c b/src/mainboard/supermicro/h8scm/irq_tables.c index fc079d6..53ce5c7 100644 --- a/src/mainboard/supermicro/h8scm/irq_tables.c +++ b/src/mainboard/supermicro/h8scm/irq_tables.c @@ -59,8 +59,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c index 0365ae6..2206b58 100644 --- a/src/mainboard/supermicro/h8scm/mptable.c +++ b/src/mainboard/supermicro/h8scm/mptable.c @@ -48,7 +48,6 @@ static void *smp_write_config_table(void *v) mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); - get_bus_conf(); mptable_write_buses(mc, NULL, &bus_isa); /* diff --git a/src/mainboard/tyan/s8226/acpi_tables.c b/src/mainboard/tyan/s8226/acpi_tables.c index 2273b9e..a49b112 100644 --- a/src/mainboard/tyan/s8226/acpi_tables.c +++ b/src/mainboard/tyan/s8226/acpi_tables.c @@ -153,8 +153,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt2; acpi_header_t *alib; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; diff --git a/src/mainboard/tyan/s8226/get_bus_conf.c b/src/mainboard/tyan/s8226/get_bus_conf.c index 5c416c5..508f379 100644 --- a/src/mainboard/tyan/s8226/get_bus_conf.c +++ b/src/mainboard/tyan/s8226/get_bus_conf.c @@ -43,18 +43,12 @@ u32 sbdn_sr5650; u32 sbdn_sp5100; void get_bus_conf(void); -static u32 get_bus_conf_done = 0; void get_bus_conf(void) { device_t dev; int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; - sbdn_sp5100 = 0; for (i = 0; i < 0; i++) { diff --git a/src/mainboard/tyan/s8226/irq_tables.c b/src/mainboard/tyan/s8226/irq_tables.c index 44c7753..3c2caa2 100644 --- a/src/mainboard/tyan/s8226/irq_tables.c +++ b/src/mainboard/tyan/s8226/irq_tables.c @@ -59,10 +59,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; - - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - - /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c index 0365ae6..2206b58 100644 --- a/src/mainboard/tyan/s8226/mptable.c +++ b/src/mainboard/tyan/s8226/mptable.c @@ -48,7 +48,6 @@ static void *smp_write_config_table(void *v) mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); - get_bus_conf(); mptable_write_buses(mc, NULL, &bus_isa); /*

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coreboot-gerrit June 2014