Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6030
-gerrit
commit fb3c930ef928ca68ff201598e0953cc4d39bc993
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sun Jun 15 12:06:12 2014 +0300
intel/nehalem: Add get_top_top_ram() in ramstage
Needed to resolve CBMEM location early in ramstage. With DYNAMIC_CBMEM
set_top_of_ram() will no longer be available.
Change-Id: If50f1c5455a587b096348ffedadbe1dd2350a714
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/northbridge/intel/nehalem/Makefile.inc | 2 ++
src/northbridge/intel/nehalem/ram_calc.c | 31 ++++++++++++++++++++++++++++++
src/northbridge/intel/nehalem/raminit.c | 9 ---------
3 files changed, 33 insertions(+), 9 deletions(-)
diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc
index 0115501..c6dcfd4 100644
--- a/src/northbridge/intel/nehalem/Makefile.inc
+++ b/src/northbridge/intel/nehalem/Makefile.inc
@@ -17,12 +17,14 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
+ramstage-y += ram_calc.c
ramstage-y += northbridge.c
ramstage-y += gma.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += ../sandybridge/mrccache.c
+romstage-y += ram_calc.c
romstage-y += raminit.c
romstage-y += early_init.c
romstage-y += ../sandybridge/mrccache.c
diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c
new file mode 100644
index 0000000..db57a3d
--- /dev/null
+++ b/src/northbridge/intel/nehalem/ram_calc.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Vladimir Serbinenko.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define __SIMPLE_DEVICE__
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include "nehalem.h"
+
+unsigned long get_top_of_ram(void)
+{
+ /* Base of TSEG is top of usable DRAM */
+ u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
+ return (unsigned long) tom;
+}
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 978ffbf..21cc987 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -4979,12 +4979,3 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
save_timings(&info);
#endif
}
-
-#if REAL
-unsigned long get_top_of_ram(void)
-{
- /* Base of TSEG is top of usable DRAM */
- u32 tom = pci_read_config32(PCI_DEV(0, 0, 0), TSEG);
- return (unsigned long)tom;
-}
-#endif
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6026
-gerrit
commit 2213fffbb930f1de8fa79608056ba743907a2ce8
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Sat Jun 14 19:15:08 2014 -0500
panther: fix VGA BIOS ID/name
The VGA BIOS name listed (0166) is neither the correct VGA ID for
panther, nor matches the VGA BIOS name used in the stock Google
firmware. Change VGA BIOS name to match name used in stock
firmware, since panther can have multiple actual VGA IDs depending
on which GPU is present.
Change-Id: I4ec5f61b3fa872c38ee560fbc61e51872c7c034b
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/mainboard/google/panther/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig
index 024c79b..298dd7a 100644
--- a/src/mainboard/google/panther/Kconfig
+++ b/src/mainboard/google/panther/Kconfig
@@ -44,6 +44,6 @@ config MAX_CPUS
config VGA_BIOS_FILE
string
- default "pci8086,0166.rom"
+ default "pci8086,0406.rom"
endif
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5998
-gerrit
commit 06dcd6118893d175a6eff623c2be96401d9a3496
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Tue Jan 7 09:53:06 2014 -0800
panther: Add ACPI code to support wake-on-lan
There needs to be an ACPI linkage to provide the power resource
needed to wake this device so the kernel will enable the SCI
before going to suspend.
A link is added for both NIC and WLAN, but it is only tested
on the NIC.
This is a forward port from Duncan's beltino patch.
BUG=chrome-os-partner:24657
BRANCH=panther
TEST=build and boot on panther, suspend and wake with etherwake
Change-Id: I2804d2e904e26d6e34f5a177f0dabc1aaa3f0288
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181752
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
---
src/mainboard/google/panther/acpi/mainboard.asl | 45 +++++++++++++++++++++++++
src/mainboard/google/panther/dsdt.asl | 4 ++-
src/mainboard/google/panther/onboard.h | 12 +++++++
3 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/panther/acpi/mainboard.asl b/src/mainboard/google/panther/acpi/mainboard.asl
index 59ed710..867c1e0 100644
--- a/src/mainboard/google/panther/acpi/mainboard.asl
+++ b/src/mainboard/google/panther/acpi/mainboard.asl
@@ -19,11 +19,56 @@
* MA 02110-1301 USA
*/
+#include <mainboard/google/panther/onboard.h>
+
Scope (\_SB)
{
Device (PWRB)
{
Name(_HID, EisaId("PNP0C0C"))
}
+}
+
+/*
+ * LAN connected to Root Port 3, becomes Root Port 1 after coalesce
+ */
+Scope (\_SB.PCI0.RP01)
+{
+ Device (ETH0)
+ {
+ Name (_ADR, 0x00000000)
+ Name (_PRW, Package() { PANTHER_NIC_WAKE_GPIO, 3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (PANTHER_NIC_WAKE_GPIO, Local0)
+
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GWAK (Local0)
+ }
+ }
+ }
+}
+/*
+ * WLAN connected to Root Port 4, becomes Root Port 2 after coalesce
+ */
+Scope (\_SB.PCI0.RP02)
+{
+ Device (WLAN)
+ {
+ Name (_ADR, 0x00000000)
+ Name (_PRW, Package() { PANTHER_WLAN_WAKE_GPIO, 3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (PANTHER_WLAN_WAKE_GPIO, Local0)
+
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GWAK (Local0)
+ }
+ }
+ }
}
diff --git a/src/mainboard/google/panther/dsdt.asl b/src/mainboard/google/panther/dsdt.asl
index 1316ebf..87076fe 100644
--- a/src/mainboard/google/panther/dsdt.asl
+++ b/src/mainboard/google/panther/dsdt.asl
@@ -31,7 +31,6 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
- #include "acpi/mainboard.asl"
// global NVS and variables
#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
@@ -50,6 +49,9 @@ DefinitionBlock(
}
}
+ // Mainboard devices
+ #include "acpi/mainboard.asl"
+
// Thermal handler
#include "acpi/thermal.asl"
diff --git a/src/mainboard/google/panther/onboard.h b/src/mainboard/google/panther/onboard.h
index 794dd8d..0b67017 100644
--- a/src/mainboard/google/panther/onboard.h
+++ b/src/mainboard/google/panther/onboard.h
@@ -1,4 +1,9 @@
+#ifndef __MAINBOARD_ONBOARD_H
+#define __MAINBOARD_ONBOARD_H
+
+#ifndef __ACPI__
void lan_init(void);
+#endif
/* defines for programming the MAC address */
#define PANTHER_NIC_VENDOR_ID 0x10EC
@@ -7,3 +12,10 @@ void lan_init(void);
/* 0x00: White LINK LED and Amber ACTIVE LED */
#define PANTHER_NIC_LED_MODE 0x00
+/* NIC wake is GPIO 8 */
+#define PANTHER_NIC_WAKE_GPIO 8
+
+/* WLAN wake is GPIO 10 */
+#define PANTHER_WLAN_WAKE_GPIO 10
+
+#endif
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5999
-gerrit
commit 0de47e10155a17b4a6fc34ecfa8810ff7ecdbd99
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Wed Jan 8 15:20:59 2014 -0800
google/panther: Disable DEVSLP for SATA
Some SSD modules don't support DEVSLP correctly due to their
firmware. Since the power savings are minimal, don't use
DEVSLP to prevent potential problems. Some of the symptoms
are that sometimes this causes USB devices to not work properly.
BUG=chrome-os-partner:23186,
BRANCH=panther
TEST=Boot tested on Panther
Change-Id: Iba3f721c73e0e760b6a9861ca23480ddb923df40
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/181957
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/panther/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index f461c58..9fbe8e6 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -55,6 +55,7 @@ chip northbridge/intel/haswell
register "ide_legacy_combined" = "0x0"
register "sata_ahci" = "0x1"
register "sata_port_map" = "0x1"
+ register "sata_devslp_disable" = "0x1"
register "sio_acpi_mode" = "0"
register "sio_i2c0_voltage" = "0" # 3.3V
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5996
-gerrit
commit 4b897b84145c7b160b15254e5a23a3c5552759c8
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Wed Dec 11 11:09:45 2013 -0800
panther: Disable power-failure gating for the PSON# signal
When the system loses AC power, the system will power back on
automatically as soon as the AC power is reapplied.
BUG=chrome-os-partner:24066
BRANCH=firmware-panther-4920.24.B
TEST=boot tested on panther
Change-Id: I37ddc5a162afcce01c2df5f509bfd7f2d0c15ba1
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/179537
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
---
src/mainboard/google/panther/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index 1966a30..f461c58 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -111,6 +111,7 @@ chip northbridge/intel/haswell
io 0x60 = 0x700
io 0x62 = 0x710
irq 0x70 = 0x09
+ irq 0xf4 = 0x20
irq 0xfa = 0x12
end
device pnp 2e.7 on # GPIO