Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5994
-gerrit
commit 82b99aeaebd67d2c84f714fe3a316d04d97fb853
Author: Mohammed Habibulla <moch(a)chromium.org>
Date: Wed Nov 20 16:24:58 2013 -0800
panther: Set default interrupt value for Environmental Controller
This writes the default value to the register, but it gets rid of
the error that disturbs some of our tests:
ERROR: PNP: 002e.4 70 irq size: 0x0000000001 not assigned
(panther port of Ieab1c776b553c996a7d06e4059110943aaf41338)
BRANCH=none
BUG=chrome-os-partner:23945
TEST=boot test on Panther
Change-Id: Id45c3bdc0d2feaf6f75d984c41d1f6ffef592d4d
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/177468
Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org>
Commit-Queue: Mohammed Habibulla <moch(a)google.com>
Tested-by: Mohammed Habibulla <moch(a)google.com>
---
src/mainboard/google/panther/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index 8bce691..1966a30 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -110,6 +110,7 @@ chip northbridge/intel/haswell
device pnp 2e.4 on # Environment Controller
io 0x60 = 0x700
io 0x62 = 0x710
+ irq 0x70 = 0x09
irq 0xfa = 0x12
end
device pnp 2e.7 on # GPIO
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5992
-gerrit
commit 32317344d32e8f6e2cf96b39946446feaa526c7f
Author: Mohammed Habibulla <moch(a)chromium.org>
Date: Tue Oct 29 11:13:14 2013 -0700
panther: Disable LPSS I2C controllers
There is nothing attached to these devices so we can disable
them as well as the function 0 DMA controller.
Also remove the EC SMI/SCI mappings since there is no EC.
(panther port of Iedfe711058676f7ee118b0b66ab0f8a1e792ea87)
BUG=chrome-os-partner:23563
TEST=none
BRANCH=panther
Change-Id: Ie66f9b66744db98f8638495c05f3a075b6fa6db9
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/174944
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Commit-Queue: Mohammed Habibulla <moch(a)chromium.org>
Tested-by: Mohammed Habibulla <moch(a)chromium.org>
---
src/mainboard/google/panther/devicetree.cb | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index 95f1084..39d4f06 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -46,11 +46,9 @@ chip northbridge/intel/haswell
# SuperIO range is 0x700-0x73f
register "gen2_dec" = "0x003c0701"
- # EC_SMI is GPIO34
- register "alt_gp_smi_en" = "0x0004"
+ register "alt_gp_smi_en" = "0x0000"
register "gpe0_en_1" = "0x00000000"
- # EC_SCI is GPIO36
- register "gpe0_en_2" = "0x00000010"
+ register "gpe0_en_2" = "0x00000000"
register "gpe0_en_3" = "0x00000000"
register "gpe0_en_4" = "0x00000000"
@@ -73,9 +71,9 @@ chip northbridge/intel/haswell
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
- device pci 15.0 on end # Serial I/O DMA
- device pci 15.1 on end # I2C0
- device pci 15.2 on end # I2C1
+ device pci 15.0 off end # Serial I/O DMA
+ device pci 15.1 off end # I2C0
+ device pci 15.2 off end # I2C1
device pci 15.3 off end # GSPI0
device pci 15.4 off end # GSPI1
device pci 15.5 off end # UART0
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5993
-gerrit
commit 64a443e398029391c2f315a6ca8839783f54fabf
Author: Mohammed Habibulla <moch(a)chromium.org>
Date: Tue Nov 12 13:29:43 2013 -0800
panther: make sure the S5 power status is on track
(panther port of I933c475f693b0271f86b5166eb2c9b3873f1c2c6)
BUG=none
BRANCH=none
TEST=boot test on panther
Change-Id: I5958a8d701901706eaa38df4323120c8352fea5c
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/176563
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Commit-Queue: Mohammed Habibulla <moch(a)chromium.org>
Tested-by: Mohammed Habibulla <moch(a)chromium.org>
---
src/mainboard/google/panther/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index 39d4f06..8bce691 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -110,6 +110,7 @@ chip northbridge/intel/haswell
device pnp 2e.4 on # Environment Controller
io 0x60 = 0x700
io 0x62 = 0x710
+ irq 0xfa = 0x12
end
device pnp 2e.7 on # GPIO
io 0x60 = 0x720
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6007
-gerrit
commit a13f7fdc30e859fb2e8c17accd6710a33743c548
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Wed Feb 19 15:05:15 2014 -0800
google/panther: Force enable ASPM on PCIe Root Port 4
BUG=chrome-os-partner:21535
BUG=chrome-os-partner:25990
BRANCH=panther
TEST=manual: Boot on Panther and look in /sys/firmware/log for
the string "PCIe Root Port 4 ASPM is enabled"
Change-Id: I294571c113a8909adb2e97afca92aef9a1af917c
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/187153
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
---
src/mainboard/google/panther/devicetree.cb | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index aa196a1..d37b622 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -61,6 +61,9 @@ chip northbridge/intel/haswell
register "sio_i2c0_voltage" = "0" # 3.3V
register "sio_i2c1_voltage" = "0" # 3.3V
+ # Force enable ASPM for PCIe Port 4
+ register "pcie_port_force_aspm" = "0x10"
+
# Enable port coalescing
register "pcie_port_coalesce" = "1"
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6006
-gerrit
commit 7c3c97170802c7b36a834f69def3fd4bf9bda2ae
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Fri Feb 14 13:41:39 2014 -0800
panther: acpi: Fix unstable fan behavior on boot + resume
FLVL is used to keep track of which thermal zones are active, but it is
not initialized upon boot / resume. An initial value of zero corresponds
to all zones being active, which causes the fan to spin at max speed
until the OS changes zones. Fix this annoyance by initializing FLVL to
the lowest temperature zone.
Also, fix a related bug where FLVL may jump to an undesired value. For
example, if FLVL=3 (zones 3 + 4 active), and zone 0 is set to off (it's
already off!), FLVL would previously become 1 (zones 1 + 2 + 3 + 4
active!). Fix this by not taking zone ON / OFF actions if our zone is
already ON / OFF.
BUG=chrome-os-partner:25766, chrome-os-partner:24775
TEST=Suspend / resume on Panther 20 times, verify that thermal zone after
resume matches expectation based upon temperature. Also, stress system
and verify thermal zones become active according to temperature
increase.
Change-Id: Ic60686aa5a67bf40c17497832b086ba09d56111a
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186455
Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186669
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
---
src/mainboard/google/panther/acpi/platform.asl | 3 +
src/mainboard/google/panther/acpi/thermal.asl | 98 ++++++++++++++++++--------
2 files changed, 71 insertions(+), 30 deletions(-)
diff --git a/src/mainboard/google/panther/acpi/platform.asl b/src/mainboard/google/panther/acpi/platform.asl
index e6aaf75..1c70d49 100644
--- a/src/mainboard/google/panther/acpi/platform.asl
+++ b/src/mainboard/google/panther/acpi/platform.asl
@@ -68,5 +68,8 @@ Method(_PTS,1)
Method(_WAK,1)
{
+ /* Initialize thermal defaults */
+ \_TZ.THRM._INI ()
+
Return(Package(){0,0})
}
diff --git a/src/mainboard/google/panther/acpi/thermal.asl b/src/mainboard/google/panther/acpi/thermal.asl
index 7f02170..d4f030a 100644
--- a/src/mainboard/google/panther/acpi/thermal.asl
+++ b/src/mainboard/google/panther/acpi/thermal.asl
@@ -61,6 +61,14 @@ Scope (\_TZ)
Return (\PPKG ())
}
+ // Start fan at state 4 = lowest temp state
+ Method (_INI)
+ {
+ Store (4, \FLVL)
+ Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
+
Method (TCHK, 0, Serialized)
{
// Get CPU Temperature from PECI via SuperIO TMPIN3
@@ -170,14 +178,20 @@ Scope (\_TZ)
}
}
Method (_ON) {
- Store (0, \FLVL)
- Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (LNot (_STA ())) {
+ Store (0, \FLVL)
+ Store (\F0PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
Method (_OFF) {
- Store (1, \FLVL)
- Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (_STA ()) {
+ Store (1, \FLVL)
+ Store (\F1PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
}
@@ -191,14 +205,20 @@ Scope (\_TZ)
}
}
Method (_ON) {
- Store (1, \FLVL)
- Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (LNot (_STA ())) {
+ Store (1, \FLVL)
+ Store (\F1PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
Method (_OFF) {
- Store (2, \FLVL)
- Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (_STA ()) {
+ Store (2, \FLVL)
+ Store (\F2PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
}
@@ -212,14 +232,20 @@ Scope (\_TZ)
}
}
Method (_ON) {
- Store (2, \FLVL)
- Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (LNot (_STA ())) {
+ Store (2, \FLVL)
+ Store (\F2PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
Method (_OFF) {
- Store (3, \FLVL)
- Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (_STA ()) {
+ Store (3, \FLVL)
+ Store (\F3PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
}
@@ -233,14 +259,20 @@ Scope (\_TZ)
}
}
Method (_ON) {
- Store (3, \FLVL)
- Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (LNot (_STA ())) {
+ Store (3, \FLVL)
+ Store (\F3PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
Method (_OFF) {
- Store (4, \FLVL)
- Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (_STA ()) {
+ Store (4, \FLVL)
+ Store (\F4PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
}
@@ -254,14 +286,20 @@ Scope (\_TZ)
}
}
Method (_ON) {
- Store (4, \FLVL)
- Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (LNot (_STA ())) {
+ Store (4, \FLVL)
+ Store (\F4PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
Method (_OFF) {
- Store (4, \FLVL)
- Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (_STA ()) {
+ Store (4, \FLVL)
+ Store (\F4PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
}
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6005
-gerrit
commit ba12ad1882b662caa15b95763a3384f35ce3d62f
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Fri Feb 14 13:22:30 2014 -0800
google/panther: Fix RW ramstage index
Without this patch coreboot will always use the read-only version
of ramstage, even if there is a read-write version available.
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
BRANCH=panther
BUG=chrome-os-partner:25870
TEST=Install different RO and RW version, check in cbmem log that
coreboot's romstage and ramstage have different timestamps
in their banners.
Change-Id: I723a3d4479d59534660728d891a9f40a077b4ef0
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/186664
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/panther/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig
index 7dd59e7..024c79b 100644
--- a/src/mainboard/google/panther/Kconfig
+++ b/src/mainboard/google/panther/Kconfig
@@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
config VBOOT_RAMSTAGE_INDEX
hex
- default 0x2
+ default 0x1
config MAINBOARD_DIR
string
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6004
-gerrit
commit 2f52cd46c59654b6273c9041afa6912f6b7d9817
Author: Mohammed Habibulla <moch(a)chromium.org>
Date: Wed Feb 12 10:07:34 2014 -0800
google/panther: new thermal values
Based on latest thermal report
BUG=chrome-os-partner:24532
TEST=boot tested on panther
BRANCH=panther
Change-Id: I4b8639f926fc3cf57eb5329818b9b912bfbe222d
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Mohammed Habibulla <moch(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186113
Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org>
---
src/mainboard/google/panther/thermal.h | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/src/mainboard/google/panther/thermal.h b/src/mainboard/google/panther/thermal.h
index 075e304..2d345c0 100644
--- a/src/mainboard/google/panther/thermal.h
+++ b/src/mainboard/google/panther/thermal.h
@@ -28,21 +28,21 @@
/* Fan is at LOW speed */
#define FAN3_THRESHOLD_OFF 40
#define FAN3_THRESHOLD_ON 50
-#define FAN3_PWM 0x6b
+#define FAN3_PWM 0x5a
/* Fan is at MEDIUM speed */
-#define FAN2_THRESHOLD_OFF 75
-#define FAN2_THRESHOLD_ON 83
-#define FAN2_PWM 0xcc
+#define FAN2_THRESHOLD_OFF 58
+#define FAN2_THRESHOLD_ON 67
+#define FAN2_PWM 0xa6
/* Fan is at HIGH speed */
-#define FAN1_THRESHOLD_OFF 86
-#define FAN1_THRESHOLD_ON 90
-#define FAN1_PWM 0xe5
+#define FAN1_THRESHOLD_OFF 67
+#define FAN1_THRESHOLD_ON 75
+#define FAN1_PWM 0xc0
/* Fan is at FULL speed */
-#define FAN0_THRESHOLD_OFF 93
-#define FAN0_THRESHOLD_ON 96
+#define FAN0_THRESHOLD_OFF 85
+#define FAN0_THRESHOLD_ON 90
#define FAN0_PWM 0xff
/* Temperature which OS will shutdown at */