Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6025
-gerrit
commit 0a5221a5471b244cfe6553257018e6dd89f44cae
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Thu Jun 12 12:24:29 2014 -0500
vendorcode/google: allow FMAP calls to be used without CONFIG_CHROMEOS set
Some ChromeOS devices, like panther and zako, use fmap calls in
lan initization, and need it compiled/included for non-CHROMEOS builds.
Modify Makefile.inc to build fmap if CONFIG_MAINBOARD_HAS_CHROMEOS is set,
but only build vboot and related components if CONFIG_CHROMEOS and
CONFIG_VBOOT_VERIFY_FIRMWARE are set.
Change-Id: Id9fca877f0f58e0f7e48c284279b7fb89499ada4
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/vendorcode/google/Makefile.inc | 2 +-
src/vendorcode/google/chromeos/Makefile.inc | 10 ++++++----
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/src/vendorcode/google/Makefile.inc b/src/vendorcode/google/Makefile.inc
index 20d40a8..a2a60e4 100644
--- a/src/vendorcode/google/Makefile.inc
+++ b/src/vendorcode/google/Makefile.inc
@@ -17,4 +17,4 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-subdirs-$(CONFIG_CHROMEOS) += chromeos
+subdirs-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index 9bd5091..5682a86 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -17,10 +17,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vbnv.c
-ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += vbnv.c
-romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vboot.c
-ramstage-y += gnvs.c
+
+ramstage-$(CONFIG_CHROMEOS) += gnvs.c
romstage-y += fmap.c
ramstage-y += fmap.c
ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c
@@ -33,6 +31,10 @@ CFLAGS_common += -DMOCK_TPM=0
endif
ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y)
+romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vbnv.c
+ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += vbnv.c
+romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vboot.c
+
romstage-y += vboot_handoff.c
ramstage-y += vboot_handoff.c
romstage-y += vboot_loader.c
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6017
-gerrit
commit 3e0677ae39ff4afeb91827891c21431e3267714a
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Sep 25 14:08:32 2013 -0700
lynxpoint: work around XHCI resume issues
When USB3 devices are attached while in suspend, or two USB3 devices
that are both plugged in are switched to the other port while in
suspend the kernel does not seem to notice this -- despite the cold
attach status bit. This results in the devices showing up in the USB
list at the old enumerated device numbers and higher layers continuing
to think they are present but not reseponding.
With the kernel workaround to deal with devices that are logically
disconnected it is possible for firmware to send a warm port reset to
devices that are in this state and then the kernel will see them disappear
and handle it properly.
This same issue exists in the EFI firmware on the Whitetip Mountain 2
reference board so it is not specifically a coreboot bug. If this
behavior is fixed in the kernel then this workaround could be removed
since it is in RW firmware.
BUG=chrome-os-partner:22818
BRANCH=falco,peppy,wolf,leon
TEST=manual:
1) attach two USB3 devices
2) suspend system
3) switch the ports that the USB3 devices are attatched to
4) resume system
5) confirm that the devices are re-enumerated and come up properly
Original-Change-Id: Ifba3ffc94a06dc0b2436d7d7d464d824657362af
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170335
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit 203d200268f4af6445224962190cbc66ad2a83e4)
Change-Id: I54fd2847ee25a60f25c2cefebdc1a3c18455464a
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170579
---
src/southbridge/intel/lynxpoint/usb_xhci.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index e091340..405277c 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -37,8 +37,6 @@ static u32 usb_xhci_mem_base(device_t dev)
return mem_base & ~0xf;
}
-#ifdef __SMM__
-
static int usb_xhci_port_count_usb3(device_t dev)
{
if (pch_is_lp()) {
@@ -127,7 +125,8 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
continue;
status = read32(portsc) & XHCI_USB3_PORTSC_PLS;
/* Reset all or only disconnected ports */
- if (all || status == XHCI_PLSR_RXDETECT)
+ if (all || (status == XHCI_PLSR_RXDETECT ||
+ status == XHCI_PLSR_POLLING))
usb_xhci_reset_port_usb3(mem_base, port);
else
port_disabled |= 1 << port;
@@ -156,6 +155,8 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
usb_xhci_reset_status_usb3(mem_base, port);
}
+#ifdef __SMM__
+
/* Handler for XHCI controller on entry to S3/S4/S5 */
void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
{
@@ -350,6 +351,14 @@ static void usb_xhci_init(device_t dev)
reg32 &= ~(1 << 23); /* unsupported request */
reg32 |= (1 << 31);
pci_write_config32(dev, 0x40, reg32);
+
+#if CONFIG_HAVE_ACPI_RESUME
+ if (acpi_slp_type == 3) {
+ /* Reset ports that are disabled or
+ * polling before returning to the OS. */
+ usb_xhci_reset_usb3(dev, 0);
+ }
+#endif
}
static void usb_xhci_set_subsystem(device_t dev, unsigned vendor,
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6021
-gerrit
commit a3b64c5e05d070b0867c82f37206d65ca7982e1a
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Thu Jun 12 12:07:16 2014 -0500
panther: fix comment typo
Add missing double quote at end of comment
Change-Id: Ia3f27910d996e84ccf3250b4bdc8008ca27474d0
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/mainboard/google/panther/acpi/thermal.asl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/panther/acpi/thermal.asl b/src/mainboard/google/panther/acpi/thermal.asl
index d4f030a..ddf4473 100644
--- a/src/mainboard/google/panther/acpi/thermal.asl
+++ b/src/mainboard/google/panther/acpi/thermal.asl
@@ -74,7 +74,7 @@ Scope (\_TZ)
// Get CPU Temperature from PECI via SuperIO TMPIN3
Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0)
- // Check for "no reading available
+ // Check for "no reading available"
If (LEqual (Local0, 0x80)) {
Return (CTOK (\F2ON))
}
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6023
-gerrit
commit 46ee651b57f8f75a3cba4b9ac55f91028f0b6bbb
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Thu Jun 12 12:12:44 2014 -0500
panther: adjust critical temp
Set critical temp to match newer devices
Change-Id: I11f32297a9b8c9a3554821b5d1cd723d8d9e2b69
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/mainboard/google/panther/thermal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/panther/thermal.h b/src/mainboard/google/panther/thermal.h
index 2d345c0..7a96561 100644
--- a/src/mainboard/google/panther/thermal.h
+++ b/src/mainboard/google/panther/thermal.h
@@ -46,7 +46,7 @@
#define FAN0_PWM 0xff
/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE 100
+#define CRITICAL_TEMPERATURE 98
/* Temperature which OS will throttle CPU */
#define PASSIVE_TEMPERATURE 90
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4132
-gerrit
commit d9743ba20bcf5ee43e9c59bdc789926c66c45a75
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Apr 19 11:03:40 2013 -0700
lynxpoint: Build intermediate step to add LynxPoint ME image
This is needed to successfully build fox_wtm2 from external repo.
BUG=chrome-os-partner:18638
BRANCH=none
TEST=manual: successfully compile coreboot for fox_wtm2 and
create an image with chromeos-bootimage/cros_bundle_firmware
Change-Id: Iaa4e9983faa1d86c2b29d8fd4f577be035497e38
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48676
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/southbridge/intel/lynxpoint/Makefile.inc | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index ce948f4..f0b6a7a 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -20,8 +20,7 @@
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware
# image outside of CBFS
-# FIXME, uncomment as soon as we have ME firmware in the blobs repo
-# INTERMEDIATE:=lynxpoint_add_me
+INTERMEDIATE:=lynxpoint_add_me
ramstage-y += pch.c
ramstage-y += azalia.c