Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6012
-gerrit
commit 7adb6ae4bbbb323be17d0edf506f90b2058d730f
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Aug 22 09:56:42 2013 -0700
Add CONFIG_LOCK_MANAGEMENT_ENGINE entry to Kconfig
This was missing from lynxpoint.
BUG=chrome-os-partner:21796
BRANCH=falco,peppy
TEST=emerge-falco chromeos-coreboot-falco
Change-Id: Id1b261a5310ce1482f11c8c032c13f49046742fc
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66669
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/southbridge/intel/lynxpoint/Kconfig | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index f0c62e4..8261bd2 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -78,4 +78,17 @@ config FINALIZE_USB_ROUTE_XHCI
If you set this option to y, the USB ports will be routed
to the XHCI controller during the finalize SMM callback.
+config LOCK_MANAGEMENT_ENGINE
+ bool "Lock Management Engine section"
+ default n
+ help
+ The Intel Management Engine supports preventing write accesses
+ from the host to the Management Engine section in the firmware
+ descriptor. If the ME section is locked, it can only be overwritten
+ with an external SPI flash programmer. You will want this if you
+ want to increase security of your ROM image once you are sure
+ that the ME firmware is no longer going to change.
+
+ If unsure, say N.
+
endif
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6011
-gerrit
commit 442f73db0dfc4982b472379ff88af8dea3e14c25
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Aug 21 13:16:21 2013 -0700
lynxpoint: Use separate SMI callback for USB XHCI routing
This will allow the legacy mode boot path to leave USB
ports routed to EHCI so they can be used by SeaBIOS.
BUG=chrome-os-partner:22085
BRANCH=falco,peppy
TEST=manual: Build and boot from USB and SeaBIOS on falco
Change-Id: I46870eccd1b846dc8a7f8d7948969c8e623e18cd
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66547
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/southbridge/intel/lynxpoint/smihandler.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index d1e9bbc..00e4a83 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -316,10 +316,8 @@ static void southbridge_smi_apmc(void)
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
break;
- case APM_CNT_FINALIZE:
-#if CONFIG_FINALIZE_USB_ROUTE_XHCI
+ case 0xca:
usb_xhci_route_all();
-#endif
break;
#if CONFIG_ELOG_GSMI
case ELOG_GSMI_APM_CNT:
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6010
-gerrit
commit 12d93c8bda3a293f7e95f98ef51a03b9a41acda3
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Tue Feb 11 16:18:07 2014 -0800
haswell: Allow overriding PRE_GRAPHICS_DELAY in config
Without a prompt the config option will always stay 0
due to the way Kconfig works.
BUG=chrome-os-partner:25387
BRANCH=panther
TEST=Boot into dev mode with Mohammed's TV screen, see
the dev mode screen appear.
Change-Id: Ib7d9ec82b4a4a29daddc29aa7702fc420279017d
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/185970
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
---
src/northbridge/intel/haswell/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index e8d84d1..e06db75 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -108,7 +108,7 @@ config CBFS_SIZE
firmware image.
config PRE_GRAPHICS_DELAY
- int
+ int "Graphics initialization delay in ms"
default 0
help
On some systems, coreboot boots so fast that connected monitors
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6009
-gerrit
commit 6777755a36e67224c1c4a9369b074ef16a793dc4
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Wed Jan 22 15:16:30 2014 -0800
haswell: Allow pre-graphics delay
Some slow monitors/TVs can't wake up quickly enough for coreboot,
so when the VBIOS is run it won't detect them. Hence, add an option
to wait for a while before running the VBIOS.
BUG=none
BRANCH=panther
TEST=Boot to dev mode on one of the systems that exposed the problem
and see it go away.
Change-Id: Ib9524f1c7ee08bedf96a6468da8b4ccf712fe0e2
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/183545
Reviewed-by: Mohammed Habibulla <moch(a)google.com>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/northbridge/intel/haswell/Kconfig | 9 +++++++++
src/northbridge/intel/haswell/gma.c | 1 +
2 files changed, 10 insertions(+)
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 4b15c7b..e8d84d1 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -107,4 +107,13 @@ config CBFS_SIZE
This option allows to limit the size of the CBFS portion in the
firmware image.
+config PRE_GRAPHICS_DELAY
+ int
+ default 0
+ help
+ On some systems, coreboot boots so fast that connected monitors
+ (mostly TVs) won't be able to wake up fast enough to talk to the
+ VBIOS. On those systems we need to wait for a bit before executing
+ the VBIOS.
+
endif
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 0c56f76..95c7b22 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -414,6 +414,7 @@ static void gma_func0_init(struct device *dev)
#endif
if (! lightup_ok) {
printk(BIOS_SPEW, "FUI did not run; using VBIOS\n");
+ mdelay(CONFIG_PRE_GRAPHICS_DELAY);
pci_dev_init(dev);
}
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6025
-gerrit
commit 505396bcc5c42f5c2e4b80f0f752eaf98c45af85
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Thu Jun 12 12:24:29 2014 -0500
vendorcode/google: allow FMAP calls to be used without CONFIG_CHROMEOS set
Some ChromeOS devices, like panther and zako, use fmap calls in
lan initization, and need it compiled/included for non-CHROMEOS builds.
Modify Makefile.inc to build fmap if CONFIG_MAINBOARD_HAS_CHROMEOS is set,
but only build vboot and related components if CONFIG_CHROMEOS and
CONFIG_VBOOT_VERIFY_FIRMWARE are set.
Change-Id: Id9fca877f0f58e0f7e48c284279b7fb89499ada4
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/vendorcode/google/Makefile.inc | 2 +-
src/vendorcode/google/chromeos/Makefile.inc | 10 ++++++----
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/src/vendorcode/google/Makefile.inc b/src/vendorcode/google/Makefile.inc
index 20d40a8..a2a60e4 100644
--- a/src/vendorcode/google/Makefile.inc
+++ b/src/vendorcode/google/Makefile.inc
@@ -17,4 +17,4 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-subdirs-$(CONFIG_CHROMEOS) += chromeos
+subdirs-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index 9bd5091..5682a86 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -17,10 +17,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vbnv.c
-ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += vbnv.c
-romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vboot.c
-ramstage-y += gnvs.c
+
+ramstage-$(CONFIG_CHROMEOS) += gnvs.c
romstage-y += fmap.c
ramstage-y += fmap.c
ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c
@@ -33,6 +31,10 @@ CFLAGS_common += -DMOCK_TPM=0
endif
ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y)
+romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vbnv.c
+ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += vbnv.c
+romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vboot.c
+
romstage-y += vboot_handoff.c
ramstage-y += vboot_handoff.c
romstage-y += vboot_loader.c
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6017
-gerrit
commit 0bbbca4a7cb0cb4758991b18b0660ff5f65cfe36
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Sep 25 14:08:32 2013 -0700
lynxpoint: work around XHCI resume issues
When USB3 devices are attached while in suspend, or two USB3 devices
that are both plugged in are switched to the other port while in
suspend the kernel does not seem to notice this -- despite the cold
attach status bit. This results in the devices showing up in the USB
list at the old enumerated device numbers and higher layers continuing
to think they are present but not reseponding.
With the kernel workaround to deal with devices that are logically
disconnected it is possible for firmware to send a warm port reset to
devices that are in this state and then the kernel will see them disappear
and handle it properly.
This same issue exists in the EFI firmware on the Whitetip Mountain 2
reference board so it is not specifically a coreboot bug. If this
behavior is fixed in the kernel then this workaround could be removed
since it is in RW firmware.
BUG=chrome-os-partner:22818
BRANCH=falco,peppy,wolf,leon
TEST=manual:
1) attach two USB3 devices
2) suspend system
3) switch the ports that the USB3 devices are attatched to
4) resume system
5) confirm that the devices are re-enumerated and come up properly
Original-Change-Id: Ifba3ffc94a06dc0b2436d7d7d464d824657362af
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170335
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit 203d200268f4af6445224962190cbc66ad2a83e4)
Change-Id: I54fd2847ee25a60f25c2cefebdc1a3c18455464a
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170579
---
src/southbridge/intel/lynxpoint/usb_xhci.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index e091340..405277c 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -37,8 +37,6 @@ static u32 usb_xhci_mem_base(device_t dev)
return mem_base & ~0xf;
}
-#ifdef __SMM__
-
static int usb_xhci_port_count_usb3(device_t dev)
{
if (pch_is_lp()) {
@@ -127,7 +125,8 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
continue;
status = read32(portsc) & XHCI_USB3_PORTSC_PLS;
/* Reset all or only disconnected ports */
- if (all || status == XHCI_PLSR_RXDETECT)
+ if (all || (status == XHCI_PLSR_RXDETECT ||
+ status == XHCI_PLSR_POLLING))
usb_xhci_reset_port_usb3(mem_base, port);
else
port_disabled |= 1 << port;
@@ -156,6 +155,8 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
usb_xhci_reset_status_usb3(mem_base, port);
}
+#ifdef __SMM__
+
/* Handler for XHCI controller on entry to S3/S4/S5 */
void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
{
@@ -350,6 +351,14 @@ static void usb_xhci_init(device_t dev)
reg32 &= ~(1 << 23); /* unsupported request */
reg32 |= (1 << 31);
pci_write_config32(dev, 0x40, reg32);
+
+#if CONFIG_HAVE_ACPI_RESUME
+ if (acpi_slp_type == 3) {
+ /* Reset ports that are disabled or
+ * polling before returning to the OS. */
+ usb_xhci_reset_usb3(dev, 0);
+ }
+#endif
}
static void usb_xhci_set_subsystem(device_t dev, unsigned vendor,