Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6019
-gerrit
commit 39a632b3a0a7d0427f3f6d5884711153d5b07bd2
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon Oct 7 16:29:54 2013 -0700
lynxpoint: Export pch_enable_lpc() for SuperIO systems
In order to enable a SuperIO in non ChromeEC systems we
need to make pch_enable_lpc() available to the mainboard
romstage.c
BUG=none
BRANCH=none
TEST=boot ChromeOS on Beltino
Change-Id: I34e7d23012e1852c69e82ba7cdc81a05751846de
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/172180
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
---
src/southbridge/intel/lynxpoint/early_pch.c | 2 +-
src/southbridge/intel/lynxpoint/pch.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 9909bb6..fdbb2a3 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -102,7 +102,7 @@ static int sleep_type_s3(void)
return is_s3;
}
-static void pch_enable_lpc(void)
+void pch_enable_lpc(void)
{
const struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
const struct southbridge_intel_lynxpoint_config *config = NULL;
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 3396367..9b5cb6f 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -213,6 +213,7 @@ int smbus_read_byte(unsigned device, unsigned address);
int early_spi_read(u32 offset, u32 size, u8 *buffer);
int early_pch_init(const void *gpio_map,
const struct rcba_config_instruction *rcba_config);
+void pch_enable_lpc(void);
#endif /* !__PRE_RAM__ && !__SMM__ */
#endif /* __ASSEMBLER__ */
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6021
-gerrit
commit b2b83c4f6e7750c747311ee6a3c6a8dd89561345
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Thu Jun 12 12:07:16 2014 -0500
panther: fit comment typo
Add missing double quote at end of comment
Change-Id: Ia3f27910d996e84ccf3250b4bdc8008ca27474d0
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/mainboard/google/panther/acpi/thermal.asl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/panther/acpi/thermal.asl b/src/mainboard/google/panther/acpi/thermal.asl
index d4f030a..ddf4473 100644
--- a/src/mainboard/google/panther/acpi/thermal.asl
+++ b/src/mainboard/google/panther/acpi/thermal.asl
@@ -74,7 +74,7 @@ Scope (\_TZ)
// Get CPU Temperature from PECI via SuperIO TMPIN3
Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0)
- // Check for "no reading available
+ // Check for "no reading available"
If (LEqual (Local0, 0x80)) {
Return (CTOK (\F2ON))
}
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6023
-gerrit
commit 7a0653258391fcff562592969c763fe3a99daf85
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Thu Jun 12 12:12:44 2014 -0500
panther: adjust critical temp
Set critical temp to match newer devices
Change-Id: I11f32297a9b8c9a3554821b5d1cd723d8d9e2b69
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/mainboard/google/panther/thermal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/panther/thermal.h b/src/mainboard/google/panther/thermal.h
index 2d345c0..7a96561 100644
--- a/src/mainboard/google/panther/thermal.h
+++ b/src/mainboard/google/panther/thermal.h
@@ -46,7 +46,7 @@
#define FAN0_PWM 0xff
/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE 100
+#define CRITICAL_TEMPERATURE 98
/* Temperature which OS will throttle CPU */
#define PASSIVE_TEMPERATURE 90
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4132
-gerrit
commit 62415c2d15b60e445f21c9c4beed5446173c21b8
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Apr 19 11:03:40 2013 -0700
lynxpoint: Build intermediate step to add LynxPoint ME image
This is needed to successfully build fox_wtm2 from external repo.
BUG=chrome-os-partner:18638
BRANCH=none
TEST=manual: successfully compile coreboot for fox_wtm2 and
create an image with chromeos-bootimage/cros_bundle_firmware
Change-Id: Iaa4e9983faa1d86c2b29d8fd4f577be035497e38
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48676
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/southbridge/intel/lynxpoint/Makefile.inc | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index ce948f4..f0b6a7a 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -20,8 +20,7 @@
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware
# image outside of CBFS
-# FIXME, uncomment as soon as we have ME firmware in the blobs repo
-# INTERMEDIATE:=lynxpoint_add_me
+INTERMEDIATE:=lynxpoint_add_me
ramstage-y += pch.c
ramstage-y += azalia.c
the following patch was just integrated into master:
commit f7d8f09d7637915c98fca4832d4085aec949c7e0
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Sat May 31 13:57:52 2014 +1000
amd/agesa,cimx: Rename ACPI OS detection methods
Try to 'standardize' the otherwise peculiar method naming to be somewhat
more in-line with other ACPI implementations. This makes it easier to
compare with vendor DSDT dumps for example.
Change-Id: I5ba54f7361796669ac0cab7ff91e7de43b22e846
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5888
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
See http://review.coreboot.org/5888 for details.
-gerrit
the following patch was just integrated into master:
commit 7a22b0976c16d09eed5ab07beb28942fe70b8b43
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Fri Jun 6 09:51:23 2014 +1000
amd/agesa/f15tn: Invalid inline asm in gcc-intrin.h
Forward port commit:
db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm
Change-Id: I87bf101b15bac7c06afa9cec10e2bd4e0cdfd6c7
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5941
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
See http://review.coreboot.org/5941 for details.
-gerrit