Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6015
-gerrit
commit a0de93509ba396ec610b93e05ab1c38b2b8a244b
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Sep 16 13:51:08 2013 -0700
lynxpoint: xhci: Port reset changes on suspend/resume
Some USB3 devices are not showing up after suspend/resume cycles.
In particular if a device uses a lower power state like U2 it may
take longer to come up and the firmware needs to wait after sending
a warm port reset.
In addition skipping port reset to connected ports in the way into
suspend was causing problems so instead send all ports a reset
before suspend.
BUG=chrome-os-partner:22402
BRANCH=falco,peppy,leon,wolf
TEST=manual:
Suspend/resume with ADATA HE720 HDD (and other devices) both
connected at suspend and connecting while in suspend and ensure
that the devices always show up in the kernel.
Change-Id: Ib7b15dc65792742b4ceb7dcfc4b2c83192eafcc2
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169548
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/southbridge/intel/lynxpoint/usb_xhci.c | 63 ++++++++++++++++++++++--------
1 file changed, 46 insertions(+), 17 deletions(-)
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index 23016fb..a8849c9 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -75,11 +75,11 @@ static void usb_xhci_reset_port_usb3(u32 mem_base, int port)
write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR);
}
-#ifdef __SMM__
-
#define XHCI_RESET_DELAY_US 1000 /* 1ms */
#define XHCI_RESET_TIMEOUT 100 /* 100ms */
+#ifdef __SMM__
+
/*
* 1) Wait until port is done polling
* 2) If port is disconnected
@@ -87,7 +87,7 @@ static void usb_xhci_reset_port_usb3(u32 mem_base, int port)
* b) Poll for warm reset complete
* c) Write 1 to port change status bits
*/
-static void usb_xhci_reset_usb3(device_t dev, int all)
+static void usb_xhci_reset_usb3(device_t dev)
{
u32 status, port_disabled;
int timeout, port;
@@ -127,10 +127,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
continue;
status = read32(portsc) & XHCI_USB3_PORTSC_PLS;
/* Reset all or only disconnected ports */
- if (all || status == XHCI_PLSR_RXDETECT)
- usb_xhci_reset_port_usb3(mem_base, port);
- else
- port_disabled |= 1 << port; /* No reset */
+ usb_xhci_reset_port_usb3(mem_base, port);
}
/* Wait for warm reset complete on all reset ports */
@@ -184,7 +181,7 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
write32(mem_base + 0x816c, reg32);
/* Reset disconnected USB3 ports */
- usb_xhci_reset_usb3(dev, 0);
+ usb_xhci_reset_usb3(dev);
/* Set MMIO 0x80e0[15] */
reg32 = read32(mem_base + 0x80e0);
@@ -236,7 +233,7 @@ void usb_xhci_route_all(void)
usb_ehci_disable(PCH_EHCI2_DEV);
/* Reset and clear port change status */
- usb_xhci_reset_usb3(PCH_XHCI_DEV, 1);
+ usb_xhci_reset_usb3(PCH_XHCI_DEV);
}
#else /* !__SMM__ */
@@ -296,6 +293,8 @@ static void usb_xhci_enable_ports_usb3(device_t dev)
u32 portsc, status, disabled;
u32 mem_base = usb_xhci_mem_base(dev);
int port_count = usb_xhci_port_count_usb3(dev);
+ u8 port_reset = 0;
+ int timeout;
if (!mem_base || !port_count)
return;
@@ -309,25 +308,55 @@ static void usb_xhci_enable_ports_usb3(device_t dev)
continue;
portsc = mem_base + XHCI_USB3_PORTSC(port);
status = read32(portsc) & XHCI_USB3_PORTSC_PLS;
-
switch (status) {
case XHCI_PLSR_RXDETECT:
/* Clear change status */
- printk(BIOS_DEBUG, "usb_xhci reset port %d\n", port);
+ printk(BIOS_DEBUG, "usb_xhci reset status %d\n", port);
usb_xhci_reset_status_usb3(mem_base, port);
break;
case XHCI_PLSR_DISABLED:
default:
- /* Transition to enabled */
- printk(BIOS_DEBUG, "usb_xhci enable port %d\n", port);
+ /* Reset port */
+ printk(BIOS_DEBUG, "usb_xhci reset port %d\n", port);
usb_xhci_reset_port_usb3(mem_base, port);
- status = read32(portsc);
- status &= ~XHCI_USB3_PORTSC_PLS;
- status |= XHCI_PLSW_ENABLE | XHCI_USB3_PORTSC_LWS;
- write32(portsc, status);
+ port_reset |= 1 << port;
break;
}
}
+
+ if (!port_reset)
+ return;
+
+ /* Wait for warm reset complete on all reset ports */
+ for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) {
+ int complete = 1;
+ for (port = 0; port < port_count; port++) {
+ /* Only check ports that were reset */
+ if (!(port_reset & (1 << port)))
+ continue;
+ /* Check if warm reset is complete */
+ status = read32(mem_base + XHCI_USB3_PORTSC(port));
+ if (!(status & XHCI_USB3_PORTSC_WRC))
+ complete = 0;
+ }
+ /* Check for warm reset complete in any port */
+ if (complete)
+ break;
+ udelay(XHCI_RESET_DELAY_US);
+ }
+
+ /* Enable ports that were reset */
+ for (port = 0; port < port_count; port++) {
+ /* Only check ports that were reset */
+ if (!(port_reset & (1 << port)))
+ continue;
+ /* Transition to enabled */
+ portsc = mem_base + XHCI_USB3_PORTSC(port);
+ status = read32(portsc);
+ status &= ~(XHCI_USB3_PORTSC_PLS | XHCI_USB3_PORTSC_PED);
+ status |= XHCI_PLSW_ENABLE | XHCI_USB3_PORTSC_LWS;
+ write32(portsc, status);
+ }
#endif
}
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6012
-gerrit
commit 3f3ab4887c6760ecf87ff5f7cb2362c339d2dcbe
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Aug 22 09:56:42 2013 -0700
Add CONFIG_LOCK_MANAGEMENT_ENGINE entry to Kconfig
This was missing from lynxpoint.
BUG=chrome-os-partner:21796
BRANCH=falco,peppy
TEST=emerge-falco chromeos-coreboot-falco
Change-Id: Id1b261a5310ce1482f11c8c032c13f49046742fc
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66669
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/southbridge/intel/lynxpoint/Kconfig | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index f0c62e4..8261bd2 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -78,4 +78,17 @@ config FINALIZE_USB_ROUTE_XHCI
If you set this option to y, the USB ports will be routed
to the XHCI controller during the finalize SMM callback.
+config LOCK_MANAGEMENT_ENGINE
+ bool "Lock Management Engine section"
+ default n
+ help
+ The Intel Management Engine supports preventing write accesses
+ from the host to the Management Engine section in the firmware
+ descriptor. If the ME section is locked, it can only be overwritten
+ with an external SPI flash programmer. You will want this if you
+ want to increase security of your ROM image once you are sure
+ that the ME firmware is no longer going to change.
+
+ If unsure, say N.
+
endif
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6011
-gerrit
commit a9f415b2aa0deba7d22d97dbefec759318400108
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Aug 21 13:16:21 2013 -0700
lynxpoint: Use separate SMI callback for USB XHCI routing
This will allow the legacy mode boot path to leave USB
ports routed to EHCI so they can be used by SeaBIOS.
BUG=chrome-os-partner:22085
BRANCH=falco,peppy
TEST=manual: Build and boot from USB and SeaBIOS on falco
Change-Id: I46870eccd1b846dc8a7f8d7948969c8e623e18cd
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66547
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/southbridge/intel/lynxpoint/smihandler.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index d1e9bbc..00e4a83 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -316,10 +316,8 @@ static void southbridge_smi_apmc(void)
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
break;
- case APM_CNT_FINALIZE:
-#if CONFIG_FINALIZE_USB_ROUTE_XHCI
+ case 0xca:
usb_xhci_route_all();
-#endif
break;
#if CONFIG_ELOG_GSMI
case ELOG_GSMI_APM_CNT:
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6010
-gerrit
commit bc69e3560f11de3dfdde2a3963bbbbfeb6e2d59d
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Tue Feb 11 16:18:07 2014 -0800
haswell: Allow overriding PRE_GRAPHICS_DELAY in config
Without a prompt the config option will always stay 0
due to the way Kconfig works.
BUG=chrome-os-partner:25387
BRANCH=panther
TEST=Boot into dev mode with Mohammed's TV screen, see
the dev mode screen appear.
Change-Id: Ib7d9ec82b4a4a29daddc29aa7702fc420279017d
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/185970
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
---
src/northbridge/intel/haswell/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index e8d84d1..e06db75 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -108,7 +108,7 @@ config CBFS_SIZE
firmware image.
config PRE_GRAPHICS_DELAY
- int
+ int "Graphics initialization delay in ms"
default 0
help
On some systems, coreboot boots so fast that connected monitors
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6009
-gerrit
commit 7bbf142aa2dab0ee46839d7c801938c3976ee2f9
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Wed Jan 22 15:16:30 2014 -0800
haswell: Allow pre-graphics delay
Some slow monitors/TVs can't wake up quickly enough for coreboot,
so when the VBIOS is run it won't detect them. Hence, add an option
to wait for a while before running the VBIOS.
BUG=none
BRANCH=panther
TEST=Boot to dev mode on one of the systems that exposed the problem
and see it go away.
Change-Id: Ib9524f1c7ee08bedf96a6468da8b4ccf712fe0e2
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/183545
Reviewed-by: Mohammed Habibulla <moch(a)google.com>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/northbridge/intel/haswell/Kconfig | 9 +++++++++
src/northbridge/intel/haswell/gma.c | 1 +
2 files changed, 10 insertions(+)
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 4b15c7b..e8d84d1 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -107,4 +107,13 @@ config CBFS_SIZE
This option allows to limit the size of the CBFS portion in the
firmware image.
+config PRE_GRAPHICS_DELAY
+ int
+ default 0
+ help
+ On some systems, coreboot boots so fast that connected monitors
+ (mostly TVs) won't be able to wake up fast enough to talk to the
+ VBIOS. On those systems we need to wait for a bit before executing
+ the VBIOS.
+
endif
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 0c56f76..95c7b22 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -414,6 +414,7 @@ static void gma_func0_init(struct device *dev)
#endif
if (! lightup_ok) {
printk(BIOS_SPEW, "FUI did not run; using VBIOS\n");
+ mdelay(CONFIG_PRE_GRAPHICS_DELAY);
pci_dev_init(dev);
}
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6026
-gerrit
commit c0cbad7e0c6adb10f3d389e01b1e47f407c90fa3
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Sat Jun 14 19:15:08 2014 -0500
panther: fix VGA BIOS ID/name
The VGA BIOS name listed (0166) is neither the correct VGA ID for
panther, nor matches the VGA BIOS name used in the stock Google
firmware. Change VGA BIOS name to match name used in stock
firmware, since panther can have multiple actual VGA IDs depending
on which GPU is present.
Change-Id: I4ec5f61b3fa872c38ee560fbc61e51872c7c034b
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/mainboard/google/panther/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig
index 024c79b..298dd7a 100644
--- a/src/mainboard/google/panther/Kconfig
+++ b/src/mainboard/google/panther/Kconfig
@@ -44,6 +44,6 @@ config MAX_CPUS
config VGA_BIOS_FILE
string
- default "pci8086,0166.rom"
+ default "pci8086,0406.rom"
endif
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6017
-gerrit
commit bb3f786fab12faeeb89976bcd15f49d859b20657
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Sep 25 14:08:32 2013 -0700
lynxpoint: work around XHCI resume issues
When USB3 devices are attached while in suspend, or two USB3 devices
that are both plugged in are switched to the other port while in
suspend the kernel does not seem to notice this -- despite the cold
attach status bit. This results in the devices showing up in the USB
list at the old enumerated device numbers and higher layers continuing
to think they are present but not reseponding.
With the kernel workaround to deal with devices that are logically
disconnected it is possible for firmware to send a warm port reset to
devices that are in this state and then the kernel will see them disappear
and handle it properly.
This same issue exists in the EFI firmware on the Whitetip Mountain 2
reference board so it is not specifically a coreboot bug. If this
behavior is fixed in the kernel then this workaround could be removed
since it is in RW firmware.
BUG=chrome-os-partner:22818
BRANCH=falco,peppy,wolf,leon
TEST=manual:
1) attach two USB3 devices
2) suspend system
3) switch the ports that the USB3 devices are attatched to
4) resume system
5) confirm that the devices are re-enumerated and come up properly
Original-Change-Id: Ifba3ffc94a06dc0b2436d7d7d464d824657362af
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170335
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit 203d200268f4af6445224962190cbc66ad2a83e4)
Change-Id: I54fd2847ee25a60f25c2cefebdc1a3c18455464a
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170579
---
src/southbridge/intel/lynxpoint/usb_xhci.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index e091340..405277c 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -37,8 +37,6 @@ static u32 usb_xhci_mem_base(device_t dev)
return mem_base & ~0xf;
}
-#ifdef __SMM__
-
static int usb_xhci_port_count_usb3(device_t dev)
{
if (pch_is_lp()) {
@@ -127,7 +125,8 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
continue;
status = read32(portsc) & XHCI_USB3_PORTSC_PLS;
/* Reset all or only disconnected ports */
- if (all || status == XHCI_PLSR_RXDETECT)
+ if (all || (status == XHCI_PLSR_RXDETECT ||
+ status == XHCI_PLSR_POLLING))
usb_xhci_reset_port_usb3(mem_base, port);
else
port_disabled |= 1 << port;
@@ -156,6 +155,8 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
usb_xhci_reset_status_usb3(mem_base, port);
}
+#ifdef __SMM__
+
/* Handler for XHCI controller on entry to S3/S4/S5 */
void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
{
@@ -350,6 +351,14 @@ static void usb_xhci_init(device_t dev)
reg32 &= ~(1 << 23); /* unsupported request */
reg32 |= (1 << 31);
pci_write_config32(dev, 0x40, reg32);
+
+#if CONFIG_HAVE_ACPI_RESUME
+ if (acpi_slp_type == 3) {
+ /* Reset ports that are disabled or
+ * polling before returning to the OS. */
+ usb_xhci_reset_usb3(dev, 0);
+ }
+#endif
}
static void usb_xhci_set_subsystem(device_t dev, unsigned vendor,