Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5927
-gerrit
commit c07816f2056a902f1e2e5ecb7d35f502e435920d
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Thu Jun 5 22:45:35 2014 +0200
lenovo/x60/i915.c: Place GTT below top of memory
Since commit 17fec8a0 [1]
drm/i915: Use Graphics Base of Stolen Memory on all gen3+
present in the Linux kernel since version 3.12, 3D does not work
anymore [2].
Comparing the graphics registers, in this case that means output of
`intel_reg_dumper`, the vendor Video BIOS is setting the register
PGTBL_CTL/PGETBL_CTL, only document in the i965 datasheet [3], to
`0x3ffc0001`, while it is set to `0x3f800001` by the native graphics
init code.
Currently native graphis init sets the GTT right above the base
address of stolen memory. The Video BIOS sets it below top of memory.
The Linux Intel driver expects it to be below top of memory, so do it
this way, by setting the address to TOM minus the size of the GTT,
which is hardcoded to 256 KiB.
There is still an error PTE error reported during boot, but 3D works
with Linux 3.12+ and no user visible problems are shown.
Currently there are the two defines `PGETBL_CTL` and `PGETLB_CTL`.
Use the one using TBL as the abbreviation for *table* and which is
the name used in the Intel 965 datasheet.
[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=…
[2] https://bugs.freedesktop.org/show_bug.cgi?id=79038
[3] https://01.org/linuxgraphics/sites/default/files/documentation/965_g35_vol_…
Intel ® 965 Express Chipset Family and
Intel ® G35 Express Chipset Graphics Controller
Programmer’s Reference Manual
Volume 1: Graphics Core
Revision 1.0a
Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
src/mainboard/lenovo/x60/i915.c | 10 +++++++++-
src/mainboard/lenovo/x60/i915_reg.h | 2 ++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c
index 8fbd2a1..c4a67c7 100644
--- a/src/mainboard/lenovo/x60/i915.c
+++ b/src/mainboard/lenovo/x60/i915.c
@@ -138,7 +138,15 @@ int gtt_setup(unsigned int mmiobase)
PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED;
PGETBL_save |= PGETBL_ENABLED;
- PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000;
+ /* The Video BIOS places the GTT right below top of memory.
+ * It is not documented in the Intel 945 datasheet, but the Intel
+ * developers said that it is normally placed there.
+ *
+ * TODO: Add option table value to make the GTT size runtime
+ * configurable.
+ */
+ tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24;
+ pgetbl_ctl |= tom - 256 * KiB;
PGETBL_save |= 2; /* set GTT to 256kb */
write32(mmiobase + GFX_FLSH_CNTL, 0);
diff --git a/src/mainboard/lenovo/x60/i915_reg.h b/src/mainboard/lenovo/x60/i915_reg.h
index 382b822..a12ba55 100644
--- a/src/mainboard/lenovo/x60/i915_reg.h
+++ b/src/mainboard/lenovo/x60/i915_reg.h
@@ -27,6 +27,8 @@
#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
+#define TOLUD 0x9c
+
/*
* The Bridge device's PCI config space has information about the
* fb aperture size and the amount of pre-reserved memory.
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5932
-gerrit
commit dd91ffdb58bfcc453ebc7d398dc5622c11612071
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Thu Jun 5 08:50:17 2014 +0200
lenovo/x60/i915.c: Use define for `BSM`
Although it builds without any further changes, including the header
src/northbridge/intel/i945/i945.h
where `BSM` is defined, would be useful. Unfortunately that conflicts
with the already included header `southbridge/intel/bd82x6x/pch.h`,
so it is left as is.
Change-Id: I7c0a795338c34038169e082446907987364a0e88
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
src/mainboard/lenovo/x60/i915.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c
index b41a0ba..8fbd2a1 100644
--- a/src/mainboard/lenovo/x60/i915.c
+++ b/src/mainboard/lenovo/x60/i915.c
@@ -138,7 +138,7 @@ int gtt_setup(unsigned int mmiobase)
PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED;
PGETBL_save |= PGETBL_ENABLED;
- PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000;
+ PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000;
PGETBL_save |= 2; /* set GTT to 256kb */
write32(mmiobase + GFX_FLSH_CNTL, 0);
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5998
-gerrit
commit 3bef80d765449c4f6d19583af4777ca756b54255
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Tue Jan 7 09:53:06 2014 -0800
panther: Add ACPI code to support wake-on-lan
There needs to be an ACPI linkage to provide the power resource
needed to wake this device so the kernel will enable the SCI
before going to suspend.
A link is added for both NIC and WLAN, but it is only tested
on the NIC.
This is a forward port from Duncan's beltino patch.
BUG=chrome-os-partner:24657
BRANCH=panther
TEST=build and boot on panther, suspend and wake with etherwake
Change-Id: I2804d2e904e26d6e34f5a177f0dabc1aaa3f0288
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181752
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
---
src/mainboard/google/panther/acpi/mainboard.asl | 45 +++++++++++++++++++++++++
src/mainboard/google/panther/dsdt.asl | 4 ++-
src/mainboard/google/panther/onboard.h | 9 +++++
3 files changed, 57 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/panther/acpi/mainboard.asl b/src/mainboard/google/panther/acpi/mainboard.asl
index 59ed710..867c1e0 100644
--- a/src/mainboard/google/panther/acpi/mainboard.asl
+++ b/src/mainboard/google/panther/acpi/mainboard.asl
@@ -19,11 +19,56 @@
* MA 02110-1301 USA
*/
+#include <mainboard/google/panther/onboard.h>
+
Scope (\_SB)
{
Device (PWRB)
{
Name(_HID, EisaId("PNP0C0C"))
}
+}
+
+/*
+ * LAN connected to Root Port 3, becomes Root Port 1 after coalesce
+ */
+Scope (\_SB.PCI0.RP01)
+{
+ Device (ETH0)
+ {
+ Name (_ADR, 0x00000000)
+ Name (_PRW, Package() { PANTHER_NIC_WAKE_GPIO, 3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (PANTHER_NIC_WAKE_GPIO, Local0)
+
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GWAK (Local0)
+ }
+ }
+ }
+}
+/*
+ * WLAN connected to Root Port 4, becomes Root Port 2 after coalesce
+ */
+Scope (\_SB.PCI0.RP02)
+{
+ Device (WLAN)
+ {
+ Name (_ADR, 0x00000000)
+ Name (_PRW, Package() { PANTHER_WLAN_WAKE_GPIO, 3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (PANTHER_WLAN_WAKE_GPIO, Local0)
+
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GWAK (Local0)
+ }
+ }
+ }
}
diff --git a/src/mainboard/google/panther/dsdt.asl b/src/mainboard/google/panther/dsdt.asl
index 1316ebf..87076fe 100644
--- a/src/mainboard/google/panther/dsdt.asl
+++ b/src/mainboard/google/panther/dsdt.asl
@@ -31,7 +31,6 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
- #include "acpi/mainboard.asl"
// global NVS and variables
#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
@@ -50,6 +49,9 @@ DefinitionBlock(
}
}
+ // Mainboard devices
+ #include "acpi/mainboard.asl"
+
// Thermal handler
#include "acpi/thermal.asl"
diff --git a/src/mainboard/google/panther/onboard.h b/src/mainboard/google/panther/onboard.h
index 39ae623..276084a 100644
--- a/src/mainboard/google/panther/onboard.h
+++ b/src/mainboard/google/panther/onboard.h
@@ -8,7 +8,16 @@
/* 0x00: White LINK LED and Amber ACTIVE LED */
#define PANTHER_NIC_LED_MODE 0x00
+/* NIC wake is GPIO 8 */
+#define PANTHER_NIC_WAKE_GPIO 8
+
+/* WLAN wake is GPIO 10 */
+#define PANTHER_WLAN_WAKE_GPIO 10
+
+#ifndef __ACPI__
void lan_init(void);
+#endif
+/* __ACPI__ */
#endif
/* MAINBOARD_ONBOARD_H */
\ No newline at end of file
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5999
-gerrit
commit 64218ff9713df61d08cffb64f347f8fcc0963f3e
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Wed Jan 8 15:20:59 2014 -0800
google/panther: Disable DEVSLP for SATA
Some SSD modules don't support DEVSLP correctly due to their
firmware. Since the power savings are minimal, don't use
DEVSLP to prevent potential problems. Some of the symptoms
are that sometimes this causes USB devices to not work properly.
BUG=chrome-os-partner:23186,
BRANCH=panther
TEST=Boot tested on Panther
Change-Id: Iba3f721c73e0e760b6a9861ca23480ddb923df40
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/181957
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/panther/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index f461c58..9fbe8e6 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -55,6 +55,7 @@ chip northbridge/intel/haswell
register "ide_legacy_combined" = "0x0"
register "sata_ahci" = "0x1"
register "sata_port_map" = "0x1"
+ register "sata_devslp_disable" = "0x1"
register "sio_acpi_mode" = "0"
register "sio_i2c0_voltage" = "0" # 3.3V
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5996
-gerrit
commit 7ac527c1264ce0c14bdacd34ce28a0babe9d90f2
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Wed Dec 11 11:09:45 2013 -0800
panther: Disable power-failure gating for the PSON# signal
When the system loses AC power, the system will power back on
automatically as soon as the AC power is reapplied.
BUG=chrome-os-partner:24066
BRANCH=firmware-panther-4920.24.B
TEST=boot tested on panther
Change-Id: I37ddc5a162afcce01c2df5f509bfd7f2d0c15ba1
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/179537
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
---
src/mainboard/google/panther/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index 1966a30..f461c58 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -111,6 +111,7 @@ chip northbridge/intel/haswell
io 0x60 = 0x700
io 0x62 = 0x710
irq 0x70 = 0x09
+ irq 0xf4 = 0x20
irq 0xfa = 0x12
end
device pnp 2e.7 on # GPIO
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5994
-gerrit
commit 983d8731d361911fd161dba007e4837d4e72ee5f
Author: Mohammed Habibulla <moch(a)chromium.org>
Date: Wed Nov 20 16:24:58 2013 -0800
panther: Set default interrupt value for Environmental Controller
This writes the default value to the register, but it gets rid of
the error that disturbs some of our tests:
ERROR: PNP: 002e.4 70 irq size: 0x0000000001 not assigned
(panther port of Ieab1c776b553c996a7d06e4059110943aaf41338)
BRANCH=none
BUG=chrome-os-partner:23945
TEST=boot test on Panther
Change-Id: Id45c3bdc0d2feaf6f75d984c41d1f6ffef592d4d
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/177468
Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org>
Commit-Queue: Mohammed Habibulla <moch(a)google.com>
Tested-by: Mohammed Habibulla <moch(a)google.com>
---
src/mainboard/google/panther/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index 8bce691..1966a30 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -110,6 +110,7 @@ chip northbridge/intel/haswell
device pnp 2e.4 on # Environment Controller
io 0x60 = 0x700
io 0x62 = 0x710
+ irq 0x70 = 0x09
irq 0xfa = 0x12
end
device pnp 2e.7 on # GPIO