Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6006
-gerrit
commit 05f187f5480ae33abc88062444e2354978a16437
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Fri Feb 14 13:41:39 2014 -0800
google/panther: acpi: Fix unstable fan behavior on boot + resume
FLVL is used to keep track of which thermal zones are active, but it is
not initialized upon boot / resume. An initial value of zero corresponds
to all zones being active, which causes the fan to spin at max speed
until the OS changes zones. Fix this annoyance by initializing FLVL to
the lowest temperature zone.
Also, fix a related bug where FLVL may jump to an undesired value. For
example, if FLVL=3 (zones 3 + 4 active), and zone 0 is set to off (it's
already off!), FLVL would previously become 1 (zones 1 + 2 + 3 + 4
active!). Fix this by not taking zone ON / OFF actions if our zone is
already ON / OFF.
BUG=chrome-os-partner:25766, chrome-os-partner:24775
TEST=Suspend / resume on Panther 20 times, verify that thermal zone after
resume matches expectation based upon temperature. Also, stress system
and verify thermal zones become active according to temperature
increase.
Change-Id: Ic60686aa5a67bf40c17497832b086ba09d56111a
Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186455
Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186669
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
---
src/mainboard/google/panther/acpi/platform.asl | 3 +
src/mainboard/google/panther/acpi/thermal.asl | 98 ++++++++++++++++++--------
2 files changed, 71 insertions(+), 30 deletions(-)
diff --git a/src/mainboard/google/panther/acpi/platform.asl b/src/mainboard/google/panther/acpi/platform.asl
index e6aaf75..1c70d49 100644
--- a/src/mainboard/google/panther/acpi/platform.asl
+++ b/src/mainboard/google/panther/acpi/platform.asl
@@ -68,5 +68,8 @@ Method(_PTS,1)
Method(_WAK,1)
{
+ /* Initialize thermal defaults */
+ \_TZ.THRM._INI ()
+
Return(Package(){0,0})
}
diff --git a/src/mainboard/google/panther/acpi/thermal.asl b/src/mainboard/google/panther/acpi/thermal.asl
index e0ea2f5..ddf4473 100644
--- a/src/mainboard/google/panther/acpi/thermal.asl
+++ b/src/mainboard/google/panther/acpi/thermal.asl
@@ -61,6 +61,14 @@ Scope (\_TZ)
Return (\PPKG ())
}
+ // Start fan at state 4 = lowest temp state
+ Method (_INI)
+ {
+ Store (4, \FLVL)
+ Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
+
Method (TCHK, 0, Serialized)
{
// Get CPU Temperature from PECI via SuperIO TMPIN3
@@ -170,14 +178,20 @@ Scope (\_TZ)
}
}
Method (_ON) {
- Store (0, \FLVL)
- Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (LNot (_STA ())) {
+ Store (0, \FLVL)
+ Store (\F0PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
Method (_OFF) {
- Store (1, \FLVL)
- Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (_STA ()) {
+ Store (1, \FLVL)
+ Store (\F1PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
}
@@ -191,14 +205,20 @@ Scope (\_TZ)
}
}
Method (_ON) {
- Store (1, \FLVL)
- Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (LNot (_STA ())) {
+ Store (1, \FLVL)
+ Store (\F1PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
Method (_OFF) {
- Store (2, \FLVL)
- Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (_STA ()) {
+ Store (2, \FLVL)
+ Store (\F2PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
}
@@ -212,14 +232,20 @@ Scope (\_TZ)
}
}
Method (_ON) {
- Store (2, \FLVL)
- Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (LNot (_STA ())) {
+ Store (2, \FLVL)
+ Store (\F2PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
Method (_OFF) {
- Store (3, \FLVL)
- Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (_STA ()) {
+ Store (3, \FLVL)
+ Store (\F3PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
}
@@ -233,14 +259,20 @@ Scope (\_TZ)
}
}
Method (_ON) {
- Store (3, \FLVL)
- Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (LNot (_STA ())) {
+ Store (3, \FLVL)
+ Store (\F3PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
Method (_OFF) {
- Store (4, \FLVL)
- Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (_STA ()) {
+ Store (4, \FLVL)
+ Store (\F4PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
}
@@ -254,14 +286,20 @@ Scope (\_TZ)
}
}
Method (_ON) {
- Store (4, \FLVL)
- Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (LNot (_STA ())) {
+ Store (4, \FLVL)
+ Store (\F4PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
Method (_OFF) {
- Store (4, \FLVL)
- Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (_STA ()) {
+ Store (4, \FLVL)
+ Store (\F4PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
}
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6005
-gerrit
commit a7f969800b12c11f6097ccfe63caa1df582d3df7
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Fri Feb 14 13:22:30 2014 -0800
google/panther: Fix RW ramstage index
Without this patch coreboot will always use the read-only version
of ramstage, even if there is a read-write version available.
BRANCH=panther
BUG=chrome-os-partner:25870
TEST=Install different RO and RW version, check in cbmem log that
coreboot's romstage and ramstage have different timestamps
in their banners.
Change-Id: I723a3d4479d59534660728d891a9f40a077b4ef0
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186664
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/panther/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig
index 4c507c7..db44396 100644
--- a/src/mainboard/google/panther/Kconfig
+++ b/src/mainboard/google/panther/Kconfig
@@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
config VBOOT_RAMSTAGE_INDEX
hex
- default 0x2
+ default 0x1
config MAINBOARD_DIR
string
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6004
-gerrit
commit 01223322ee0b5e3a54f2afa68bef7053794e9511
Author: Mohammed Habibulla <moch(a)chromium.org>
Date: Wed Feb 12 10:07:34 2014 -0800
google/panther: new thermal values
Based on latest thermal report
BUG=chrome-os-partner:24532
TEST=boot tested on panther
BRANCH=panther
Change-Id: I4b8639f926fc3cf57eb5329818b9b912bfbe222d
Signed-off-by: Mohammed Habibulla <moch(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186113
Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org>
---
src/mainboard/google/panther/thermal.h | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/src/mainboard/google/panther/thermal.h b/src/mainboard/google/panther/thermal.h
index 075e304..2d345c0 100644
--- a/src/mainboard/google/panther/thermal.h
+++ b/src/mainboard/google/panther/thermal.h
@@ -28,21 +28,21 @@
/* Fan is at LOW speed */
#define FAN3_THRESHOLD_OFF 40
#define FAN3_THRESHOLD_ON 50
-#define FAN3_PWM 0x6b
+#define FAN3_PWM 0x5a
/* Fan is at MEDIUM speed */
-#define FAN2_THRESHOLD_OFF 75
-#define FAN2_THRESHOLD_ON 83
-#define FAN2_PWM 0xcc
+#define FAN2_THRESHOLD_OFF 58
+#define FAN2_THRESHOLD_ON 67
+#define FAN2_PWM 0xa6
/* Fan is at HIGH speed */
-#define FAN1_THRESHOLD_OFF 86
-#define FAN1_THRESHOLD_ON 90
-#define FAN1_PWM 0xe5
+#define FAN1_THRESHOLD_OFF 67
+#define FAN1_THRESHOLD_ON 75
+#define FAN1_PWM 0xc0
/* Fan is at FULL speed */
-#define FAN0_THRESHOLD_OFF 93
-#define FAN0_THRESHOLD_ON 96
+#define FAN0_THRESHOLD_OFF 85
+#define FAN0_THRESHOLD_ON 90
#define FAN0_PWM 0xff
/* Temperature which OS will shutdown at */
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6002
-gerrit
commit 1ce038059f0a145c0126b20c8afa6e4fec5c7c2a
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon Jan 13 17:40:37 2014 -0800
google/panther: Avoid shutdown when thermal sensor is unavailable
When the thermal sensor on Panther is unavailable (early on resume)
it will return 0x80 which causes our AML thermal code to overflow,
which causes the system to shut down. Instead, return a reasonable
value in those cases so that the system will continue running until
the sensor gets back on its feet.
BUG=chrome-os-partner:24918
BRANCH=panther
TEST=suspend_resume_test survived more than 100 iterations on Panther
Change-Id: Ib2d714c39d353ce2415361bc6590784a3f6837d2
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182369
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
---
src/mainboard/google/panther/acpi/thermal.asl | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/src/mainboard/google/panther/acpi/thermal.asl b/src/mainboard/google/panther/acpi/thermal.asl
index a6ea851..e0ea2f5 100644
--- a/src/mainboard/google/panther/acpi/thermal.asl
+++ b/src/mainboard/google/panther/acpi/thermal.asl
@@ -66,6 +66,11 @@ Scope (\_TZ)
// Get CPU Temperature from PECI via SuperIO TMPIN3
Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0)
+ // Check for "no reading available"
+ If (LEqual (Local0, 0x80)) {
+ Return (CTOK (\F2ON))
+ }
+
// Check for invalid readings
If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) {
Return (CTOK (\F2ON))
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6001
-gerrit
commit 2d0f0a2c9d8ff59b85bc8adcde2a366e42f508dc
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Fri Jan 10 16:06:03 2014 -0800
google/panther: Re-read temperature if current reading would cause power-off
Sometimes the SuperIO seems to provide wrong readings, especially early
on after a resume from suspend. This will cause the system to power off.
If that happens, wait for 1s and read again, to make sure the high
temperature value was not just a flaky read.
BUG=chrome-os-partner:24918
BRANCH=panther
TEST=Boot tested on Panther.
Change-Id: Ib3768528d90e34448e96ad587b2503d8d8b1a775
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182188
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
---
src/mainboard/google/panther/acpi/thermal.asl | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/panther/acpi/thermal.asl b/src/mainboard/google/panther/acpi/thermal.asl
index d5b1290..a6ea851 100644
--- a/src/mainboard/google/panther/acpi/thermal.asl
+++ b/src/mainboard/google/panther/acpi/thermal.asl
@@ -61,7 +61,7 @@ Scope (\_TZ)
Return (\PPKG ())
}
- Method (_TMP, 0, Serialized)
+ Method (TCHK, 0, Serialized)
{
// Get CPU Temperature from PECI via SuperIO TMPIN3
Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0)
@@ -84,6 +84,31 @@ Scope (\_TZ)
Return (CTOK (Local0))
}
+ Method (_TMP, 0, Serialized)
+ {
+ // Get temperature from SuperIO in deci-kelvin
+ Store (TCHK (), Local0)
+
+ // Critical temperature in deci-kelvin
+ Store (CTOK (\TMAX), Local1)
+
+ If (LGreaterEqual (Local0, Local1)) {
+ Store ("CRITICAL TEMPERATURE", Debug)
+ Store (Local0, Debug)
+
+ // Wait 1 second for SuperIO to re-poll
+ Sleep (1000)
+
+ // Re-read temperature from SuperIO
+ Store (TCHK (), Local0)
+
+ Store ("RE-READ TEMPERATURE", Debug)
+ Store (Local0, Debug)
+ }
+
+ Return (Local0)
+ }
+
Method (_AC0) {
If (LLessEqual (\FLVL, 0)) {
Return (CTOK (\F0OF))
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4132
-gerrit
commit 401e9bda3e8e31426e02a2ee46f8f9cbd24669d0
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Apr 19 11:03:40 2013 -0700
intel/lynxpoint: Build intermediate step to add Lynx Point ME image
This is needed to successfully build fox_wtm2 from external repo.
BUG=chrome-os-partner:18638
BRANCH=none
TEST=manual: successfully compile coreboot for fox_wtm2 and
create an image with chromeos-bootimage/cros_bundle_firmware
Change-Id: Iaa4e9983faa1d86c2b29d8fd4f577be035497e38
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48676
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/southbridge/intel/lynxpoint/Makefile.inc | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index 0358267..e504db0 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -20,8 +20,7 @@
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware
# image outside of CBFS
-# FIXME, uncomment as soon as we have ME firmware in the blobs repo
-# INTERMEDIATE:=lynxpoint_add_me
+INTERMEDIATE:=lynxpoint_add_me
ramstage-y += pch.c
ramstage-y += azalia.c
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6041
-gerrit
commit 217430cfa1a174f1974cfe8afeccd53c4d3894be
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Mon Jun 16 14:13:06 2014 +1000
src/superio/ite/it8772f: Separate mainboard from SIO at obj level
Remove #include early_serial.c and rename to early_init.c as no actual
UART configuration is done here. Note that this SIO component still
hard codes its base address to 0x2e.
Change-Id: Icc817e6f31007f90ff326a36e9c3cc824cae4fa4
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/mainboard/samsung/stumpy/romstage.c | 2 -
src/mainboard/samsung/stumpy/smihandler.c | 17 +++---
src/superio/ite/it8772f/Makefile.inc | 1 +
src/superio/ite/it8772f/early_init.c | 87 ++++++++++++++++++++++++++++++
src/superio/ite/it8772f/early_serial.c | 88 -------------------------------
src/superio/ite/it8772f/it8772f.h | 11 +++-
6 files changed, 105 insertions(+), 101 deletions(-)
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 0ae71a8..09cae66 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -33,8 +33,6 @@
#include <bootmode.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8772f/it8772f.h>
-/* FIXME: SUPERIO include.c */
-#include "superio/ite/it8772f/early_serial.c"
#include "northbridge/intel/sandybridge/sandybridge.h"
#include "northbridge/intel/sandybridge/raminit.h"
#include "southbridge/intel/bd82x6x/pch.h"
diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c
index 5c3e1b3..45a851f 100644
--- a/src/mainboard/samsung/stumpy/smihandler.c
+++ b/src/mainboard/samsung/stumpy/smihandler.c
@@ -26,8 +26,7 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
-/* Include romstage serial for SIO helper functions */
-#include <superio/ite/it8772f/early_serial.c>
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
int mainboard_io_trap_handler(int smif)
{
@@ -64,18 +63,18 @@ void mainboard_smi_sleep(u8 slp_typ)
case 3:
case 4:
/* Blink LED */
- it8772f_enter_conf();
- it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
+ it8772f_enter_conf(DUMMY_DEV);
+ it8772f_sio_write(DUMMY_DEV, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
/* Enable blink pin map */
- it8772f_sio_write(IT8772F_GPIO_LED_BLINK1_PINMAP,
+ it8772f_sio_write(DUMMY_DEV, IT8772F_GPIO_LED_BLINK1_PINMAP,
SIO_GPIO_BLINK_GPIO45);
/* Enable 4HZ blink */
- it8772f_sio_write(IT8772F_GPIO_LED_BLINK1_CONTROL, 0x02);
+ it8772f_sio_write(DUMMY_DEV, IT8772F_GPIO_LED_BLINK1_CONTROL, 0x02);
/* Set GPIO to alternate function */
- reg8 = it8772f_sio_read(GPIO_REG_ENABLE(3));
+ reg8 = it8772f_sio_read(DUMMY_DEV, GPIO_REG_ENABLE(3));
reg8 &= ~(1 << 5);
- it8772f_sio_write(GPIO_REG_ENABLE(3), reg8);
- it8772f_exit_conf();
+ it8772f_sio_write(DUMMY_DEV, GPIO_REG_ENABLE(3), reg8);
+ it8772f_exit_conf(DUMMY_DEV);
break;
case 5:
diff --git a/src/superio/ite/it8772f/Makefile.inc b/src/superio/ite/it8772f/Makefile.inc
index 7b6be2c..438ba84 100644
--- a/src/superio/ite/it8772f/Makefile.inc
+++ b/src/superio/ite/it8772f/Makefile.inc
@@ -18,4 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+romstage-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c
ramstage-$(CONFIG_SUPERIO_ITE_IT8772F) += superio.c
diff --git a/src/superio/ite/it8772f/early_init.c b/src/superio/ite/it8772f/early_init.c
new file mode 100644
index 0000000..190a23d
--- /dev/null
+++ b/src/superio/ite/it8772f/early_init.c
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include "it8772f.h"
+
+/* NOTICE: This file is deprecated, use ite/common instead */
+
+/* Global configuration registers. */
+#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
+#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
+
+/* RAMstage equiv */
+/* u8 pnp_read_config(device_t dev, u8 reg) */
+u8 it8772f_sio_read(device_t dev, u8 reg)
+{
+ u16 port = dev >> 8;
+ outb(reg, port);
+ return inb(port + 1);
+}
+
+/* RAMstage equiv */
+/* void pnp_write_config(device_t dev, u8 reg, u8 value) */
+void it8772f_sio_write(device_t dev, u8 reg, u8 value)
+{
+ outb(reg, port);
+ outb(value, port + 1);
+}
+
+void it8772f_enter_conf(device_t dev)
+{
+ u16 port = dev >> 8;
+
+ outb(0x87, port);
+ outb(0x01, port);
+ outb(0x55, port);
+ outb((port == 0x4e) ? 0xaa : 0x55, port);
+}
+
+void it8772f_exit_conf(void)
+{
+ it8772f_sio_write(IT8772F_CONFIG_REG_CC, 0x02);
+}
+
+/* Set AC resume to be up to the Southbridge */
+void it8772f_ac_resume_southbridge(void)
+{
+ it8772f_enter_conf();
+ it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_EC);
+ it8772f_sio_write(0xf4, 0x60);
+ it8772f_exit_conf();
+}
+
+/* Configure a set of GPIOs */
+void it8772f_gpio_setup(int set, u8 select, u8 polarity, u8 pullup,
+ u8 output, u8 enable)
+{
+ set--; /* Set 1 is offset 0 */
+ it8772f_enter_conf();
+ it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
+ if (set < 5) {
+ it8772f_sio_write(GPIO_REG_SELECT(set), select);
+ it8772f_sio_write(GPIO_REG_ENABLE(set), enable);
+ it8772f_sio_write(GPIO_REG_POLARITY(set), polarity);
+ }
+ it8772f_sio_write(GPIO_REG_OUTPUT(set), output);
+ it8772f_sio_write(GPIO_REG_PULLUP(set), pullup);
+ it8772f_exit_conf();
+}
diff --git a/src/superio/ite/it8772f/early_serial.c b/src/superio/ite/it8772f/early_serial.c
deleted file mode 100644
index ee9dbc5..0000000
--- a/src/superio/ite/it8772f/early_serial.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include "it8772f.h"
-
-/* NOTICE: This file is deprecated, use ite/common instead */
-
-/* The base address is 0x2e or 0x4e, depending on config bytes. */
-/* FIXME: SUPERIO include.c */
-#define SIO_BASE 0x2e
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
-#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
-
-u8 it8772f_sio_read(u8 index)
-{
- outb(index, SIO_BASE);
- return inb(SIO_DATA);
-}
-
-void it8772f_sio_write(u8 index, u8 value)
-{
- outb(index, SIO_BASE);
- outb(value, SIO_DATA);
-}
-
-static void it8772f_enter_conf(void)
-{
- u16 port = SIO_BASE;
-
- outb(0x87, port);
- outb(0x01, port);
- outb(0x55, port);
- outb((port == 0x4e) ? 0xaa : 0x55, port);
-}
-
-static void it8772f_exit_conf(void)
-{
- it8772f_sio_write(IT8772F_CONFIG_REG_CC, 0x02);
-}
-
-/* Set AC resume to be up to the Southbridge */
-void it8772f_ac_resume_southbridge(void)
-{
- it8772f_enter_conf();
- it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_EC);
- it8772f_sio_write(0xf4, 0x60);
- it8772f_exit_conf();
-}
-
-/* Configure a set of GPIOs */
-void it8772f_gpio_setup(int set, u8 select, u8 polarity, u8 pullup,
- u8 output, u8 enable)
-{
- set--; /* Set 1 is offset 0 */
- it8772f_enter_conf();
- it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
- if (set < 5) {
- it8772f_sio_write(GPIO_REG_SELECT(set), select);
- it8772f_sio_write(GPIO_REG_ENABLE(set), enable);
- it8772f_sio_write(GPIO_REG_POLARITY(set), polarity);
- }
- it8772f_sio_write(GPIO_REG_OUTPUT(set), output);
- it8772f_sio_write(GPIO_REG_PULLUP(set), pullup);
- it8772f_exit_conf();
-}
diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h
index 221a932..d43c996 100644
--- a/src/superio/ite/it8772f/it8772f.h
+++ b/src/superio/ite/it8772f/it8772f.h
@@ -103,10 +103,17 @@
#define GPIO_REG_ENABLE(x) (0xc0 + (x))
#define GPIO_REG_OUTPUT(x) (0xc8 + (x))
-u8 it8772f_sio_read(u8 index);
-void it8772f_sio_write(u8 index, u8 value);
+#include <arch/io.h>
+#include <stdint.h>
+
+u8 it8772f_sio_read(device_t dev, u8 reg);
+void it8772f_sio_write(device_t dev, u8 reg, u8 value);
void it8772f_ac_resume_southbridge(void);
void it8772f_gpio_setup(int set, u8 func_select, u8 polarity, u8 pullup,
u8 output, u8 enable);
+/* FIXME: should be static so will be removed later.. */
+void it8772f_enter_conf(device_t dev);
+void it8772f_exit_conf(void);
+
#endif /* SUPERIO_ITE_IT8772F_H */
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6007
-gerrit
commit 61ff89b77f75297372f45765a24db3fe60899b0f
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Wed Feb 19 15:05:15 2014 -0800
google/panther: Force enable ASPM on PCIe Root Port 4
BUG=chrome-os-partner:21535
BUG=chrome-os-partner:25990
BRANCH=panther
TEST=manual: Boot on Panther and look in /sys/firmware/log for
the string "PCIe Root Port 4 ASPM is enabled"
Change-Id: I294571c113a8909adb2e97afca92aef9a1af917c
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187153
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
---
src/mainboard/google/panther/devicetree.cb | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index 9fbe8e6..7cc3672 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -61,6 +61,9 @@ chip northbridge/intel/haswell
register "sio_i2c0_voltage" = "0" # 3.3V
register "sio_i2c1_voltage" = "0" # 3.3V
+ # Force enable ASPM for PCIe Port 4
+ register "pcie_port_force_aspm" = "0x10"
+
# Enable port coalescing
register "pcie_port_coalesce" = "1"