Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5999
-gerrit
commit fb0a0c86a80a5165b149867e098ec431e5056909
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Wed Jan 8 15:20:59 2014 -0800
google/panther: Disable DEVSLP for SATA
Some SSD modules don't support DEVSLP correctly due to their
firmware. Since the power savings are minimal, don't use
DEVSLP to prevent potential problems. Some of the symptoms
are that sometimes this causes USB devices to not work properly.
BUG=chrome-os-partner:23186,
BRANCH=panther
TEST=Boot tested on Panther
Change-Id: Iba3f721c73e0e760b6a9861ca23480ddb923df40
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181957
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/panther/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index f461c58..9fbe8e6 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -55,6 +55,7 @@ chip northbridge/intel/haswell
register "ide_legacy_combined" = "0x0"
register "sata_ahci" = "0x1"
register "sata_port_map" = "0x1"
+ register "sata_devslp_disable" = "0x1"
register "sio_acpi_mode" = "0"
register "sio_i2c0_voltage" = "0" # 3.3V
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5996
-gerrit
commit 1861eb62af47db8c86043e1da4861eba8be8b7fc
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Wed Dec 11 11:09:45 2013 -0800
google/panther: Disable power-failure gating for the PSON# signal
When the system loses AC power, the system will power back on
automatically as soon as the AC power is reapplied.
BUG=chrome-os-partner:24066
BRANCH=firmware-panther-4920.24.B
TEST=boot tested on panther
Change-Id: I37ddc5a162afcce01c2df5f509bfd7f2d0c15ba1
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179537
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
---
src/mainboard/google/panther/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index 1966a30..f461c58 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -111,6 +111,7 @@ chip northbridge/intel/haswell
io 0x60 = 0x700
io 0x62 = 0x710
irq 0x70 = 0x09
+ irq 0xf4 = 0x20
irq 0xfa = 0x12
end
device pnp 2e.7 on # GPIO
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5994
-gerrit
commit 3cdb4bbc70f5311a8166780a39a0f5071484a5f8
Author: Mohammed Habibulla <moch(a)chromium.org>
Date: Wed Nov 20 16:24:58 2013 -0800
google/panther: Set default interrupt value for Environmental Controller
This writes the default value to the register, but it gets rid of
the error that disturbs some of our tests:
ERROR: PNP: 002e.4 70 irq size: 0x0000000001 not assigned
(panther port of Ieab1c776b553c996a7d06e4059110943aaf41338)
BRANCH=none
BUG=chrome-os-partner:23945
TEST=boot test on Panther
Change-Id: Id45c3bdc0d2feaf6f75d984c41d1f6ffef592d4d
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/177468
Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org>
Commit-Queue: Mohammed Habibulla <moch(a)google.com>
Tested-by: Mohammed Habibulla <moch(a)google.com>
---
src/mainboard/google/panther/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index 8bce691..1966a30 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -110,6 +110,7 @@ chip northbridge/intel/haswell
device pnp 2e.4 on # Environment Controller
io 0x60 = 0x700
io 0x62 = 0x710
+ irq 0x70 = 0x09
irq 0xfa = 0x12
end
device pnp 2e.7 on # GPIO
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5993
-gerrit
commit d1c8d18247c1e149fa04282e34c0beb06b5b28d0
Author: Mohammed Habibulla <moch(a)chromium.org>
Date: Tue Nov 12 13:29:43 2013 -0800
google/panther: make sure the S5 power status is on track
(panther port of I933c475f693b0271f86b5166eb2c9b3873f1c2c6)
BUG=none
BRANCH=none
TEST=boot test on panther
Change-Id: I5958a8d701901706eaa38df4323120c8352fea5c
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/176563
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Commit-Queue: Mohammed Habibulla <moch(a)chromium.org>
Tested-by: Mohammed Habibulla <moch(a)chromium.org>
---
src/mainboard/google/panther/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index 39d4f06..8bce691 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -110,6 +110,7 @@ chip northbridge/intel/haswell
device pnp 2e.4 on # Environment Controller
io 0x60 = 0x700
io 0x62 = 0x710
+ irq 0xfa = 0x12
end
device pnp 2e.7 on # GPIO
io 0x60 = 0x720
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5992
-gerrit
commit 84c66c2824d2119c5e653ebd20b55fc93d3629e9
Author: Mohammed Habibulla <moch(a)chromium.org>
Date: Tue Oct 29 11:13:14 2013 -0700
google/panther: Disable LPSS I2C controllers
There is nothing attached to these devices so we can disable
them as well as the function 0 DMA controller.
Also remove the EC SMI/SCI mappings since there is no EC.
(panther port of Iedfe711058676f7ee118b0b66ab0f8a1e792ea87)
BUG=chrome-os-partner:23563
TEST=none
BRANCH=panther
Change-Id: Ie66f9b66744db98f8638495c05f3a075b6fa6db9
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/174944
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Commit-Queue: Mohammed Habibulla <moch(a)chromium.org>
Tested-by: Mohammed Habibulla <moch(a)chromium.org>
---
src/mainboard/google/panther/devicetree.cb | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index 95f1084..39d4f06 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -46,11 +46,9 @@ chip northbridge/intel/haswell
# SuperIO range is 0x700-0x73f
register "gen2_dec" = "0x003c0701"
- # EC_SMI is GPIO34
- register "alt_gp_smi_en" = "0x0004"
+ register "alt_gp_smi_en" = "0x0000"
register "gpe0_en_1" = "0x00000000"
- # EC_SCI is GPIO36
- register "gpe0_en_2" = "0x00000010"
+ register "gpe0_en_2" = "0x00000000"
register "gpe0_en_3" = "0x00000000"
register "gpe0_en_4" = "0x00000000"
@@ -73,9 +71,9 @@ chip northbridge/intel/haswell
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
- device pci 15.0 on end # Serial I/O DMA
- device pci 15.1 on end # I2C0
- device pci 15.2 on end # I2C1
+ device pci 15.0 off end # Serial I/O DMA
+ device pci 15.1 off end # I2C0
+ device pci 15.2 off end # I2C1
device pci 15.3 off end # GSPI0
device pci 15.4 off end # GSPI1
device pci 15.5 off end # UART0
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6025
-gerrit
commit f2dd3f67b44b87b720294f347933ec25144f0551
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Thu Jun 12 12:24:29 2014 -0500
vendorcode/google: allow FMAP calls to be used without CONFIG_CHROMEOS set
Some ChromeOS devices, like panther and zako, use fmap calls in
lan initization, and need it compiled/included for non-CHROMEOS builds.
Modify Makefile.inc to build fmap if CONFIG_MAINBOARD_HAS_CHROMEOS is set,
but only build vboot and related components if CONFIG_CHROMEOS and
CONFIG_VBOOT_VERIFY_FIRMWARE are set.
Change-Id: Id9fca877f0f58e0f7e48c284279b7fb89499ada4
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/vendorcode/google/Makefile.inc | 2 +-
src/vendorcode/google/chromeos/Makefile.inc | 10 ++++++----
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/src/vendorcode/google/Makefile.inc b/src/vendorcode/google/Makefile.inc
index 20d40a8..a2a60e4 100644
--- a/src/vendorcode/google/Makefile.inc
+++ b/src/vendorcode/google/Makefile.inc
@@ -17,4 +17,4 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-subdirs-$(CONFIG_CHROMEOS) += chromeos
+subdirs-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index 9bd5091..5682a86 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -17,10 +17,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vbnv.c
-ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += vbnv.c
-romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vboot.c
-ramstage-y += gnvs.c
+
+ramstage-$(CONFIG_CHROMEOS) += gnvs.c
romstage-y += fmap.c
ramstage-y += fmap.c
ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c
@@ -33,6 +31,10 @@ CFLAGS_common += -DMOCK_TPM=0
endif
ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y)
+romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vbnv.c
+ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += vbnv.c
+romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vboot.c
+
romstage-y += vboot_handoff.c
ramstage-y += vboot_handoff.c
romstage-y += vboot_loader.c