Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6006
-gerrit
commit 70db0accbfa64201d93026419ee37d75c815eef8
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Fri Feb 14 13:41:39 2014 -0800
google/panther: acpi: Fix unstable fan behavior on boot + resume
FLVL is used to keep track of which thermal zones are active, but it is
not initialized upon boot / resume. An initial value of zero corresponds
to all zones being active, which causes the fan to spin at max speed
until the OS changes zones. Fix this annoyance by initializing FLVL to
the lowest temperature zone.
Also, fix a related bug where FLVL may jump to an undesired value. For
example, if FLVL=3 (zones 3 + 4 active), and zone 0 is set to off (it's
already off!), FLVL would previously become 1 (zones 1 + 2 + 3 + 4
active!). Fix this by not taking zone ON / OFF actions if our zone is
already ON / OFF.
BUG=chrome-os-partner:25766, chrome-os-partner:24775
TEST=Suspend / resume on Panther 20 times, verify that thermal zone after
resume matches expectation based upon temperature. Also, stress system
and verify thermal zones become active according to temperature
increase.
Change-Id: Ic60686aa5a67bf40c17497832b086ba09d56111a
Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186455
Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186669
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
---
src/mainboard/google/panther/acpi/platform.asl | 3 +
src/mainboard/google/panther/acpi/thermal.asl | 98 ++++++++++++++++++--------
2 files changed, 71 insertions(+), 30 deletions(-)
diff --git a/src/mainboard/google/panther/acpi/platform.asl b/src/mainboard/google/panther/acpi/platform.asl
index e6aaf75..1c70d49 100644
--- a/src/mainboard/google/panther/acpi/platform.asl
+++ b/src/mainboard/google/panther/acpi/platform.asl
@@ -68,5 +68,8 @@ Method(_PTS,1)
Method(_WAK,1)
{
+ /* Initialize thermal defaults */
+ \_TZ.THRM._INI ()
+
Return(Package(){0,0})
}
diff --git a/src/mainboard/google/panther/acpi/thermal.asl b/src/mainboard/google/panther/acpi/thermal.asl
index e0ea2f5..ddf4473 100644
--- a/src/mainboard/google/panther/acpi/thermal.asl
+++ b/src/mainboard/google/panther/acpi/thermal.asl
@@ -61,6 +61,14 @@ Scope (\_TZ)
Return (\PPKG ())
}
+ // Start fan at state 4 = lowest temp state
+ Method (_INI)
+ {
+ Store (4, \FLVL)
+ Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
+
Method (TCHK, 0, Serialized)
{
// Get CPU Temperature from PECI via SuperIO TMPIN3
@@ -170,14 +178,20 @@ Scope (\_TZ)
}
}
Method (_ON) {
- Store (0, \FLVL)
- Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (LNot (_STA ())) {
+ Store (0, \FLVL)
+ Store (\F0PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
Method (_OFF) {
- Store (1, \FLVL)
- Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (_STA ()) {
+ Store (1, \FLVL)
+ Store (\F1PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
}
@@ -191,14 +205,20 @@ Scope (\_TZ)
}
}
Method (_ON) {
- Store (1, \FLVL)
- Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (LNot (_STA ())) {
+ Store (1, \FLVL)
+ Store (\F1PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
Method (_OFF) {
- Store (2, \FLVL)
- Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (_STA ()) {
+ Store (2, \FLVL)
+ Store (\F2PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
}
@@ -212,14 +232,20 @@ Scope (\_TZ)
}
}
Method (_ON) {
- Store (2, \FLVL)
- Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (LNot (_STA ())) {
+ Store (2, \FLVL)
+ Store (\F2PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
Method (_OFF) {
- Store (3, \FLVL)
- Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (_STA ()) {
+ Store (3, \FLVL)
+ Store (\F3PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
}
@@ -233,14 +259,20 @@ Scope (\_TZ)
}
}
Method (_ON) {
- Store (3, \FLVL)
- Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (LNot (_STA ())) {
+ Store (3, \FLVL)
+ Store (\F3PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
Method (_OFF) {
- Store (4, \FLVL)
- Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (_STA ()) {
+ Store (4, \FLVL)
+ Store (\F4PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
}
@@ -254,14 +286,20 @@ Scope (\_TZ)
}
}
Method (_ON) {
- Store (4, \FLVL)
- Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (LNot (_STA ())) {
+ Store (4, \FLVL)
+ Store (\F4PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
Method (_OFF) {
- Store (4, \FLVL)
- Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
- Notify (\_TZ.THRM, 0x81)
+ If (_STA ()) {
+ Store (4, \FLVL)
+ Store (\F4PW,
+ \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+ Notify (\_TZ.THRM, 0x81)
+ }
}
}
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6020
-gerrit
commit f0d084164d3b616f7991ddaa7e1d89b65d1c8cc9
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Thu Jun 12 12:03:05 2014 -0500
google/panther: Change PCI ID in name of Video BIOS
Change-Id: Iedc7f14dd48f422b741750e4ee93c9f447fe5c42
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/mainboard/google/panther/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig
index db44396..9b3ee15 100644
--- a/src/mainboard/google/panther/Kconfig
+++ b/src/mainboard/google/panther/Kconfig
@@ -44,7 +44,7 @@ config MAX_CPUS
config VGA_BIOS_FILE
string
- default "pci8086,0166.rom"
+ default "pci8086,0406.rom"
config HAVE_IFD_BIN
bool
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6023
-gerrit
commit 71a361cd4b0e90e6237f8114a6c41e12eea918d5
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Thu Jun 12 12:12:44 2014 -0500
google/panther: adjust critical temp
Set critical temp to match newer devices
Change-Id: I11f32297a9b8c9a3554821b5d1cd723d8d9e2b69
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/mainboard/google/panther/thermal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/panther/thermal.h b/src/mainboard/google/panther/thermal.h
index 2d345c0..7a96561 100644
--- a/src/mainboard/google/panther/thermal.h
+++ b/src/mainboard/google/panther/thermal.h
@@ -46,7 +46,7 @@
#define FAN0_PWM 0xff
/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE 100
+#define CRITICAL_TEMPERATURE 98
/* Temperature which OS will throttle CPU */
#define PASSIVE_TEMPERATURE 90
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6005
-gerrit
commit 78ea852683ed68ea506ef0031211b6f58e06bc5c
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Fri Feb 14 13:22:30 2014 -0800
google/panther: Fix RW ramstage index
Without this patch coreboot will always use the read-only version
of ramstage, even if there is a read-write version available.
BRANCH=panther
BUG=chrome-os-partner:25870
TEST=Install different RO and RW version, check in cbmem log that
coreboot's romstage and ramstage have different timestamps
in their banners.
Change-Id: I723a3d4479d59534660728d891a9f40a077b4ef0
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186664
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/panther/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig
index 4c507c7..db44396 100644
--- a/src/mainboard/google/panther/Kconfig
+++ b/src/mainboard/google/panther/Kconfig
@@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
config VBOOT_RAMSTAGE_INDEX
hex
- default 0x2
+ default 0x1
config MAINBOARD_DIR
string
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6004
-gerrit
commit 68ea712b7b7e4d1a60580ad78dcabebf1d05d7c6
Author: Mohammed Habibulla <moch(a)chromium.org>
Date: Wed Feb 12 10:07:34 2014 -0800
google/panther: new thermal values
Based on latest thermal report
BUG=chrome-os-partner:24532
TEST=boot tested on panther
BRANCH=panther
Change-Id: I4b8639f926fc3cf57eb5329818b9b912bfbe222d
Signed-off-by: Mohammed Habibulla <moch(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186113
Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org>
---
src/mainboard/google/panther/thermal.h | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/src/mainboard/google/panther/thermal.h b/src/mainboard/google/panther/thermal.h
index 075e304..2d345c0 100644
--- a/src/mainboard/google/panther/thermal.h
+++ b/src/mainboard/google/panther/thermal.h
@@ -28,21 +28,21 @@
/* Fan is at LOW speed */
#define FAN3_THRESHOLD_OFF 40
#define FAN3_THRESHOLD_ON 50
-#define FAN3_PWM 0x6b
+#define FAN3_PWM 0x5a
/* Fan is at MEDIUM speed */
-#define FAN2_THRESHOLD_OFF 75
-#define FAN2_THRESHOLD_ON 83
-#define FAN2_PWM 0xcc
+#define FAN2_THRESHOLD_OFF 58
+#define FAN2_THRESHOLD_ON 67
+#define FAN2_PWM 0xa6
/* Fan is at HIGH speed */
-#define FAN1_THRESHOLD_OFF 86
-#define FAN1_THRESHOLD_ON 90
-#define FAN1_PWM 0xe5
+#define FAN1_THRESHOLD_OFF 67
+#define FAN1_THRESHOLD_ON 75
+#define FAN1_PWM 0xc0
/* Fan is at FULL speed */
-#define FAN0_THRESHOLD_OFF 93
-#define FAN0_THRESHOLD_ON 96
+#define FAN0_THRESHOLD_OFF 85
+#define FAN0_THRESHOLD_ON 90
#define FAN0_PWM 0xff
/* Temperature which OS will shutdown at */
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6002
-gerrit
commit f0f8eab6e3fba2fb8cecc451e8a11d0b58f6c13d
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon Jan 13 17:40:37 2014 -0800
google/panther: Avoid shutdown when thermal sensor is unavailable
When the thermal sensor on Panther is unavailable (early on resume)
it will return 0x80 which causes our AML thermal code to overflow,
which causes the system to shut down. Instead, return a reasonable
value in those cases so that the system will continue running until
the sensor gets back on its feet.
BUG=chrome-os-partner:24918
BRANCH=panther
TEST=suspend_resume_test survived more than 100 iterations on Panther
Change-Id: Ib2d714c39d353ce2415361bc6590784a3f6837d2
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182369
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
---
src/mainboard/google/panther/acpi/thermal.asl | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/src/mainboard/google/panther/acpi/thermal.asl b/src/mainboard/google/panther/acpi/thermal.asl
index a6ea851..e0ea2f5 100644
--- a/src/mainboard/google/panther/acpi/thermal.asl
+++ b/src/mainboard/google/panther/acpi/thermal.asl
@@ -66,6 +66,11 @@ Scope (\_TZ)
// Get CPU Temperature from PECI via SuperIO TMPIN3
Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0)
+ // Check for "no reading available"
+ If (LEqual (Local0, 0x80)) {
+ Return (CTOK (\F2ON))
+ }
+
// Check for invalid readings
If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) {
Return (CTOK (\F2ON))
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6001
-gerrit
commit 07d382e852d4e437f9edd26041ad00d628418cb0
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Fri Jan 10 16:06:03 2014 -0800
google/panther: Re-read temperature if current reading would cause power-off
Sometimes the SuperIO seems to provide wrong readings, especially early
on after a resume from suspend. This will cause the system to power off.
If that happens, wait for 1s and read again, to make sure the high
temperature value was not just a flaky read.
BUG=chrome-os-partner:24918
BRANCH=panther
TEST=Boot tested on Panther.
Change-Id: Ib3768528d90e34448e96ad587b2503d8d8b1a775
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182188
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
---
src/mainboard/google/panther/acpi/thermal.asl | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/panther/acpi/thermal.asl b/src/mainboard/google/panther/acpi/thermal.asl
index d5b1290..a6ea851 100644
--- a/src/mainboard/google/panther/acpi/thermal.asl
+++ b/src/mainboard/google/panther/acpi/thermal.asl
@@ -61,7 +61,7 @@ Scope (\_TZ)
Return (\PPKG ())
}
- Method (_TMP, 0, Serialized)
+ Method (TCHK, 0, Serialized)
{
// Get CPU Temperature from PECI via SuperIO TMPIN3
Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0)
@@ -84,6 +84,31 @@ Scope (\_TZ)
Return (CTOK (Local0))
}
+ Method (_TMP, 0, Serialized)
+ {
+ // Get temperature from SuperIO in deci-kelvin
+ Store (TCHK (), Local0)
+
+ // Critical temperature in deci-kelvin
+ Store (CTOK (\TMAX), Local1)
+
+ If (LGreaterEqual (Local0, Local1)) {
+ Store ("CRITICAL TEMPERATURE", Debug)
+ Store (Local0, Debug)
+
+ // Wait 1 second for SuperIO to re-poll
+ Sleep (1000)
+
+ // Re-read temperature from SuperIO
+ Store (TCHK (), Local0)
+
+ Store ("RE-READ TEMPERATURE", Debug)
+ Store (Local0, Debug)
+ }
+
+ Return (Local0)
+ }
+
Method (_AC0) {
If (LLessEqual (\FLVL, 0)) {
Return (CTOK (\F0OF))
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5998
-gerrit
commit c548a1408945343027e22161c66f612fb97a66e3
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Tue Jan 7 09:53:06 2014 -0800
google/panther: Add ACPI code to support wake-on-lan
There needs to be an ACPI linkage to provide the power resource
needed to wake this device so the kernel will enable the SCI
before going to suspend.
A link is added for both NIC and WLAN, but it is only tested
on the NIC.
This is a forward port from Duncan's beltino patch.
BUG=chrome-os-partner:24657
BRANCH=panther
TEST=build and boot on panther, suspend and wake with etherwake
Change-Id: I2804d2e904e26d6e34f5a177f0dabc1aaa3f0288
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181752
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
---
src/mainboard/google/panther/acpi/mainboard.asl | 45 +++++++++++++++++++++++++
src/mainboard/google/panther/dsdt.asl | 4 ++-
src/mainboard/google/panther/onboard.h | 12 +++++++
3 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/panther/acpi/mainboard.asl b/src/mainboard/google/panther/acpi/mainboard.asl
index 59ed710..867c1e0 100644
--- a/src/mainboard/google/panther/acpi/mainboard.asl
+++ b/src/mainboard/google/panther/acpi/mainboard.asl
@@ -19,11 +19,56 @@
* MA 02110-1301 USA
*/
+#include <mainboard/google/panther/onboard.h>
+
Scope (\_SB)
{
Device (PWRB)
{
Name(_HID, EisaId("PNP0C0C"))
}
+}
+
+/*
+ * LAN connected to Root Port 3, becomes Root Port 1 after coalesce
+ */
+Scope (\_SB.PCI0.RP01)
+{
+ Device (ETH0)
+ {
+ Name (_ADR, 0x00000000)
+ Name (_PRW, Package() { PANTHER_NIC_WAKE_GPIO, 3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (PANTHER_NIC_WAKE_GPIO, Local0)
+
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GWAK (Local0)
+ }
+ }
+ }
+}
+/*
+ * WLAN connected to Root Port 4, becomes Root Port 2 after coalesce
+ */
+Scope (\_SB.PCI0.RP02)
+{
+ Device (WLAN)
+ {
+ Name (_ADR, 0x00000000)
+ Name (_PRW, Package() { PANTHER_WLAN_WAKE_GPIO, 3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (PANTHER_WLAN_WAKE_GPIO, Local0)
+
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GWAK (Local0)
+ }
+ }
+ }
}
diff --git a/src/mainboard/google/panther/dsdt.asl b/src/mainboard/google/panther/dsdt.asl
index 1316ebf..87076fe 100644
--- a/src/mainboard/google/panther/dsdt.asl
+++ b/src/mainboard/google/panther/dsdt.asl
@@ -31,7 +31,6 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
- #include "acpi/mainboard.asl"
// global NVS and variables
#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
@@ -50,6 +49,9 @@ DefinitionBlock(
}
}
+ // Mainboard devices
+ #include "acpi/mainboard.asl"
+
// Thermal handler
#include "acpi/thermal.asl"
diff --git a/src/mainboard/google/panther/onboard.h b/src/mainboard/google/panther/onboard.h
index 794dd8d..0b67017 100644
--- a/src/mainboard/google/panther/onboard.h
+++ b/src/mainboard/google/panther/onboard.h
@@ -1,4 +1,9 @@
+#ifndef __MAINBOARD_ONBOARD_H
+#define __MAINBOARD_ONBOARD_H
+
+#ifndef __ACPI__
void lan_init(void);
+#endif
/* defines for programming the MAC address */
#define PANTHER_NIC_VENDOR_ID 0x10EC
@@ -7,3 +12,10 @@ void lan_init(void);
/* 0x00: White LINK LED and Amber ACTIVE LED */
#define PANTHER_NIC_LED_MODE 0x00
+/* NIC wake is GPIO 8 */
+#define PANTHER_NIC_WAKE_GPIO 8
+
+/* WLAN wake is GPIO 10 */
+#define PANTHER_WLAN_WAKE_GPIO 10
+
+#endif