the following patch was just integrated into master:
commit cbc783f3e1b31b03e163af928fee8d67dfd6678e
Author: Mike Loptien <mike.loptien(a)se-eng.com>
Date: Fri Jun 6 15:21:28 2014 -0600
Persimmon: Change MPTable to use mainboard IRQ routing
With the addition of the mainboard PCI IRQ routing tables
for AMD Persimmon, the MPTables can be set to use this
information to accurately reflect the real hardware settings
of the system. Additionally, the IOAPIC gets defined before
the MPTable gets generated so the settings can be read
directly from the IOAPIC registers instead of 'guessing' at
them as was done before.
Change-Id: I96ec046a2208eddf4b5e442214ff43d2a349ca4d
Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/5878
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
See http://review.coreboot.org/5878 for details.
-gerrit
the following patch was just integrated into master:
commit d0167d3ae268e3fcdef5c02e381b47dbb04ab1a4
Author: Mike Loptien <mike.loptien(a)se-eng.com>
Date: Wed Jun 11 14:20:48 2014 -0600
MP Spec: Correct the Virtual Wire assignment
Virtual Wire mode is set by writing 0 to the the MPTable
Feature2 bit field 'IMCR'. The virtualwire variable was
initially defined as writing a 1 to this bit field which
would actually set PIC mode instead of Virtual Wire mode.
However, nearly every mainboard called the MPTables with
virtualwire = 0, which actually had the effect of setting
Virtual Wire mode. I am correcting the definition but
leaving the call to write the MPTables with virtualwire = 0,
which is how most mainboards are already setting the tables
up.
See the MP Spec table 4-1 for more details:
Bit 7: IMCRP. When the IMCR presence bit is
set, the IMCR is present and PIC Mode is
implemented; otherwise, Virtual Wire Mode is
implemented.
http://download.intel.com/design/archives/processors/pro/docs/24201606.pdf
Change-Id: I039d88134aabd55166c2b68aa842bacbfcc0f42b
Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/5977
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/5977 for details.
-gerrit
the following patch was just integrated into master:
commit 915973406544d1d6a60a539ad9fb8a33c3caf2c9
Author: Mike Loptien <mike.loptien(a)se-eng.com>
Date: Thu Jun 12 10:22:27 2014 -0600
MP Spec: Add copyright header
Adding the copyright header to the MP Spec files because
they were not included before.
Change-Id: Ifcd217a53bf8df19b28e251a7cac8b92be68d1fc
Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/5981
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
See http://review.coreboot.org/5981 for details.
-gerrit
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5998
-gerrit
commit 120624c1aa76bb9e22dfd33884d357a88db6255e
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Tue Jan 7 09:53:06 2014 -0800
google/panther: Add ACPI code to support wake-on-lan
There needs to be an ACPI linkage to provide the power resource
needed to wake this device so the kernel will enable the SCI
before going to suspend.
A link is added for both NIC and WLAN, but it is only tested
on the NIC.
This is a forward port from Duncan's beltino patch.
BUG=chrome-os-partner:24657
BRANCH=panther
TEST=build and boot on panther, suspend and wake with etherwake
Change-Id: I2804d2e904e26d6e34f5a177f0dabc1aaa3f0288
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181752
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
---
src/mainboard/google/panther/acpi/mainboard.asl | 45 +++++++++++++++++++++++++
src/mainboard/google/panther/dsdt.asl | 4 ++-
src/mainboard/google/panther/onboard.h | 12 +++++++
3 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/panther/acpi/mainboard.asl b/src/mainboard/google/panther/acpi/mainboard.asl
index 59ed710..867c1e0 100644
--- a/src/mainboard/google/panther/acpi/mainboard.asl
+++ b/src/mainboard/google/panther/acpi/mainboard.asl
@@ -19,11 +19,56 @@
* MA 02110-1301 USA
*/
+#include <mainboard/google/panther/onboard.h>
+
Scope (\_SB)
{
Device (PWRB)
{
Name(_HID, EisaId("PNP0C0C"))
}
+}
+
+/*
+ * LAN connected to Root Port 3, becomes Root Port 1 after coalesce
+ */
+Scope (\_SB.PCI0.RP01)
+{
+ Device (ETH0)
+ {
+ Name (_ADR, 0x00000000)
+ Name (_PRW, Package() { PANTHER_NIC_WAKE_GPIO, 3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (PANTHER_NIC_WAKE_GPIO, Local0)
+
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GWAK (Local0)
+ }
+ }
+ }
+}
+/*
+ * WLAN connected to Root Port 4, becomes Root Port 2 after coalesce
+ */
+Scope (\_SB.PCI0.RP02)
+{
+ Device (WLAN)
+ {
+ Name (_ADR, 0x00000000)
+ Name (_PRW, Package() { PANTHER_WLAN_WAKE_GPIO, 3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (PANTHER_WLAN_WAKE_GPIO, Local0)
+
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GWAK (Local0)
+ }
+ }
+ }
}
diff --git a/src/mainboard/google/panther/dsdt.asl b/src/mainboard/google/panther/dsdt.asl
index 1316ebf..87076fe 100644
--- a/src/mainboard/google/panther/dsdt.asl
+++ b/src/mainboard/google/panther/dsdt.asl
@@ -31,7 +31,6 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
- #include "acpi/mainboard.asl"
// global NVS and variables
#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
@@ -50,6 +49,9 @@ DefinitionBlock(
}
}
+ // Mainboard devices
+ #include "acpi/mainboard.asl"
+
// Thermal handler
#include "acpi/thermal.asl"
diff --git a/src/mainboard/google/panther/onboard.h b/src/mainboard/google/panther/onboard.h
index 794dd8d..0b67017 100644
--- a/src/mainboard/google/panther/onboard.h
+++ b/src/mainboard/google/panther/onboard.h
@@ -1,4 +1,9 @@
+#ifndef __MAINBOARD_ONBOARD_H
+#define __MAINBOARD_ONBOARD_H
+
+#ifndef __ACPI__
void lan_init(void);
+#endif
/* defines for programming the MAC address */
#define PANTHER_NIC_VENDOR_ID 0x10EC
@@ -7,3 +12,10 @@ void lan_init(void);
/* 0x00: White LINK LED and Amber ACTIVE LED */
#define PANTHER_NIC_LED_MODE 0x00
+/* NIC wake is GPIO 8 */
+#define PANTHER_NIC_WAKE_GPIO 8
+
+/* WLAN wake is GPIO 10 */
+#define PANTHER_WLAN_WAKE_GPIO 10
+
+#endif