Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5999
-gerrit
commit c380962fbc22f35cd82c96e9cda163f26365ab06
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Wed Jan 8 15:20:59 2014 -0800
google/panther: Disable DEVSLP for SATA
Some SSD modules don't support DEVSLP correctly due to their
firmware. Since the power savings are minimal, don't use
DEVSLP to prevent potential problems. Some of the symptoms
are that sometimes this causes USB devices to not work properly.
BUG=chrome-os-partner:23186,
BRANCH=panther
TEST=Boot tested on Panther
Change-Id: Iba3f721c73e0e760b6a9861ca23480ddb923df40
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181957
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/panther/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index f461c58..9fbe8e6 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -55,6 +55,7 @@ chip northbridge/intel/haswell
register "ide_legacy_combined" = "0x0"
register "sata_ahci" = "0x1"
register "sata_port_map" = "0x1"
+ register "sata_devslp_disable" = "0x1"
register "sio_acpi_mode" = "0"
register "sio_i2c0_voltage" = "0" # 3.3V
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5996
-gerrit
commit 1368e8da4d3641fef36ad6c1dd0d5b2de5ad1371
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Wed Dec 11 11:09:45 2013 -0800
google/panther: Disable power-failure gating for the PSON# signal
When the system loses AC power, the system will power back on
automatically as soon as the AC power is reapplied.
BUG=chrome-os-partner:24066
BRANCH=firmware-panther-4920.24.B
TEST=boot tested on panther
Change-Id: I37ddc5a162afcce01c2df5f509bfd7f2d0c15ba1
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179537
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
---
src/mainboard/google/panther/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index 1966a30..f461c58 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -111,6 +111,7 @@ chip northbridge/intel/haswell
io 0x60 = 0x700
io 0x62 = 0x710
irq 0x70 = 0x09
+ irq 0xf4 = 0x20
irq 0xfa = 0x12
end
device pnp 2e.7 on # GPIO
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5994
-gerrit
commit d1ca39d18009d32f0d443e5ef7c4acb38f9c0254
Author: Mohammed Habibulla <moch(a)chromium.org>
Date: Wed Nov 20 16:24:58 2013 -0800
google/panther: Set default interrupt value for Environmental Controller
This writes the default value to the register, but it gets rid of
the error that disturbs some of our tests:
ERROR: PNP: 002e.4 70 irq size: 0x0000000001 not assigned
(panther port of Ieab1c776b553c996a7d06e4059110943aaf41338)
BRANCH=none
BUG=chrome-os-partner:23945
TEST=boot test on Panther
Change-Id: Id45c3bdc0d2feaf6f75d984c41d1f6ffef592d4d
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/177468
Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org>
Commit-Queue: Mohammed Habibulla <moch(a)google.com>
Tested-by: Mohammed Habibulla <moch(a)google.com>
---
src/mainboard/google/panther/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index 8bce691..1966a30 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -110,6 +110,7 @@ chip northbridge/intel/haswell
device pnp 2e.4 on # Environment Controller
io 0x60 = 0x700
io 0x62 = 0x710
+ irq 0x70 = 0x09
irq 0xfa = 0x12
end
device pnp 2e.7 on # GPIO
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6020
-gerrit
commit b2323c358e5a517205b80b86775c9423727ad783
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Thu Jun 12 12:03:05 2014 -0500
google/panther: Change PCI ID in name of Video BIOS
Change-Id: Iedc7f14dd48f422b741750e4ee93c9f447fe5c42
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/mainboard/google/panther/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig
index db44396..9b3ee15 100644
--- a/src/mainboard/google/panther/Kconfig
+++ b/src/mainboard/google/panther/Kconfig
@@ -44,7 +44,7 @@ config MAX_CPUS
config VGA_BIOS_FILE
string
- default "pci8086,0166.rom"
+ default "pci8086,0406.rom"
config HAVE_IFD_BIN
bool
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5992
-gerrit
commit 8c140ff0f2b7e97efec08282728847d466a44b04
Author: Mohammed Habibulla <moch(a)chromium.org>
Date: Tue Oct 29 11:13:14 2013 -0700
google/panther: Disable LPSS I2C controllers
There is nothing attached to these devices so we can disable
them as well as the function 0 DMA controller.
Also remove the EC SMI/SCI mappings since there is no EC.
(panther port of Iedfe711058676f7ee118b0b66ab0f8a1e792ea87)
BUG=chrome-os-partner:23563
TEST=none
BRANCH=panther
Change-Id: Ie66f9b66744db98f8638495c05f3a075b6fa6db9
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/174944
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Commit-Queue: Mohammed Habibulla <moch(a)chromium.org>
Tested-by: Mohammed Habibulla <moch(a)chromium.org>
---
src/mainboard/google/panther/devicetree.cb | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index 95f1084..39d4f06 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -46,11 +46,9 @@ chip northbridge/intel/haswell
# SuperIO range is 0x700-0x73f
register "gen2_dec" = "0x003c0701"
- # EC_SMI is GPIO34
- register "alt_gp_smi_en" = "0x0004"
+ register "alt_gp_smi_en" = "0x0000"
register "gpe0_en_1" = "0x00000000"
- # EC_SCI is GPIO36
- register "gpe0_en_2" = "0x00000010"
+ register "gpe0_en_2" = "0x00000000"
register "gpe0_en_3" = "0x00000000"
register "gpe0_en_4" = "0x00000000"
@@ -73,9 +71,9 @@ chip northbridge/intel/haswell
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
- device pci 15.0 on end # Serial I/O DMA
- device pci 15.1 on end # I2C0
- device pci 15.2 on end # I2C1
+ device pci 15.0 off end # Serial I/O DMA
+ device pci 15.1 off end # I2C0
+ device pci 15.2 off end # I2C1
device pci 15.3 off end # GSPI0
device pci 15.4 off end # GSPI1
device pci 15.5 off end # UART0
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6023
-gerrit
commit 96778d7a875719979c58268b2487c3f5446c4c48
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Thu Jun 12 12:12:44 2014 -0500
google/panther: adjust critical temp
Set critical temp to match newer devices
Change-Id: I11f32297a9b8c9a3554821b5d1cd723d8d9e2b69
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/mainboard/google/panther/thermal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/panther/thermal.h b/src/mainboard/google/panther/thermal.h
index 2d345c0..7a96561 100644
--- a/src/mainboard/google/panther/thermal.h
+++ b/src/mainboard/google/panther/thermal.h
@@ -46,7 +46,7 @@
#define FAN0_PWM 0xff
/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE 100
+#define CRITICAL_TEMPERATURE 98
/* Temperature which OS will throttle CPU */
#define PASSIVE_TEMPERATURE 90
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5993
-gerrit
commit c027b03274ced5852d222a90d2811c7a7fb8428d
Author: Mohammed Habibulla <moch(a)chromium.org>
Date: Tue Nov 12 13:29:43 2013 -0800
google/panther: make sure the S5 power status is on track
(panther port of I933c475f693b0271f86b5166eb2c9b3873f1c2c6)
BUG=none
BRANCH=none
TEST=boot test on panther
Change-Id: I5958a8d701901706eaa38df4323120c8352fea5c
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/176563
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Commit-Queue: Mohammed Habibulla <moch(a)chromium.org>
Tested-by: Mohammed Habibulla <moch(a)chromium.org>
---
src/mainboard/google/panther/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index 39d4f06..8bce691 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -110,6 +110,7 @@ chip northbridge/intel/haswell
device pnp 2e.4 on # Environment Controller
io 0x60 = 0x700
io 0x62 = 0x710
+ irq 0xfa = 0x12
end
device pnp 2e.7 on # GPIO
io 0x60 = 0x720
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6007
-gerrit
commit 9e83527620ec1b6b051f46eafd5a934113bd2625
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Wed Feb 19 15:05:15 2014 -0800
google/panther: Force enable ASPM on PCIe Root Port 4
BUG=chrome-os-partner:21535
BUG=chrome-os-partner:25990
BRANCH=panther
TEST=manual: Boot on Panther and look in /sys/firmware/log for
the string "PCIe Root Port 4 ASPM is enabled"
Change-Id: I294571c113a8909adb2e97afca92aef9a1af917c
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187153
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)chromium.org>
Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org>
---
src/mainboard/google/panther/devicetree.cb | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index 9fbe8e6..7cc3672 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -61,6 +61,9 @@ chip northbridge/intel/haswell
register "sio_i2c0_voltage" = "0" # 3.3V
register "sio_i2c1_voltage" = "0" # 3.3V
+ # Force enable ASPM for PCIe Port 4
+ register "pcie_port_force_aspm" = "0x10"
+
# Enable port coalescing
register "pcie_port_coalesce" = "1"